Bit Set and Clear Instructions for 68HC11

The 68HC11 has instructions that will set or clear selected bits in a memory
register. These instructions contain a mask byte that selects the bits to be operated
on. The meaning of the name mask in these instructions is different from its
meaning when used with the AND and ORA instruction.

BSET Set all bits in a memory byte that correspond to 1s in the mask. The
BSET instruction ORs the mask from inside the instruction to the
addressed memory byte and puts the result into the memory byte.

BCLR Clear all bits in a memory byte that correspond to 1s in the mask. The
BCLR instruction ANDs the complement of the mask from inside the
instruction to the addressed memory byte and puts the result into the
memory byte.

The mask byte selects the bits that the instruction operates on. For all instructions
that contain a mask, 1s in the mask enable the operation and 0s disable the
operation. Masks that are all 1s or all 0s are seldom used. If the mask contains all
0s, the instruction does nothing. A BSET instruction with a mask of all 1s is
useful, but a BCLR instruction with a mask or all 1s may be replaced by a CLR
instruction.

Addressing Modes for Bit Instructions

The BSET and BCLR instructions each have two addressing modes for a single
instruction. No other instructions in the 68HC11 have two addressing modes.
These bit instructions need a memory address of the register to be operated on and
a mask byte to select the bits.

The instruction code contains the constant mask byte. Therefore, the immediate
addressing is used to access the mask byte. The mask byte makes these instructions
one byte longer than expected. The bit instructions can use either direct addressing
or indexed addressing to access the memory byte to be operated on. An instruction
that can use only direct or indexed addressing has an unusual combination of
addressing modes. In particular, the extended addressing mode is not available to
these instructions. The 68HC11 instruction set table lists only the addressing mode
for the memory byte to be operated on. Because immediate addressing is always

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used to access the mask, the instruction set tables does not show the addressing
mode for the mask.

The Assembly Language Format

The assembly language for the bit instructions has a new format to accommodate
the mask byte, which makes the instruction statement longer. The format is the
same as for other direct or indexed addressed instructions, except the mask byte is
added at the end of the statement after a comma. For example, the statement

EX1 BSET LIGHTS, $10

sets bit 4 of the memory location labeled LIGHTS using direct addressing. The
value of the mask byte is specified numerically or symbolically; however, the #
symbol for immediate addressing is not used. The order of the symbols in the
assembly language − namely, op code, address, and mask − is the same as the order
of the instruction bytes in memory.

Bit Testing and Branching Instructions for 68HC11

Practical programs frequently need to test one or more memory bits and then
branch on the outcome of the test. The 68HC11 has instructions that combine the
testing and branching operations into one instruction. Here are the bit test-and-
branch instructions:

BRSET Branch if all the bits in a memory byte that correspond to 1s in the
mask are set. The BRSET instruction ANDs the mask from inside the
instruction, with the complement of the addressed memory byte and
if the result is zero, it branches.

BRCLR Branch if all bits in a memory byte that correspond to 1s in the mask
are clear. The BRCLR instruction ANDs the mask from inside the
instruction, with the addressed memory byte and if the result is zero, it
branches.

As in the BSET and BCLR instructions, the mask in the BRSET and BRCLR
instructions selects the bits in the memory byte to be tested. All selected bits must
meet the required condition for the branch to occur. The most common mask
contains only a single 1, so one bit is tested.

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Addressing Modes for Branch on Bit Instructions

The BRSET and BRCLR instructions each have three addressing modes for a
single instruction. No other instructions in the 68HC11 have three addressing
modes. These two instructions and the address of the memory register to be
operated on, a mask byte to select the bits in that memory register, and an offset for
the relative addressed branch operation.

The instruction code contains the constant mask byte. Therefore, the mask byte is
accessed by immediate addressing mode. The memory byte tested is accessed by
either direct or indexed addressing mode. The branching operation used program
relative addressing the same as the other branch instructions. The multiple
addressing modes make these instructions either four or five bytes long. The
instruction set table shows the memory format for these instructions.

The Assembly Language Format

The assembly language format for these instructions is unique because of the
required addressing modes. Be careful that your assembler uses this format
because some assemblers require the index register at the end of the statement. The
format here is the same as the BSET and BCLR instructions with a relative address
symbol added at the end. For example, the statement

EX2 BRCLR 1,Y,MASK1,NEXT

Creates an instruction using indexed by Y addressing with an offset of 1 to access a

memory register. The bits in the register that correspond to the 1s in the value of
the symbol MASK1 are tested. If all those bits are 0s, then the instruction branches
to location NEXT; otherwise execution continues at the next instruction.

The order of the symbols in the assembly language statement is the same as the
order of the instruction bytes in memory. Therefore, the order of the hexadecimal
codes in the instruction set table implies the order of the symbols.

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RMB directive

RMB is an acronym for reserve memory bytes. The format of the statement is

[label] RMB expression

where the expression determines a number the assembler adds to the location
counter. Adjusting the location counter causes the assembler to skip the number of
bytes determined by the expression. In effect, RMB reserves a block of memory
registers for use elsewhere in the program. The loader does not affect the memory
bytes skipped by an RMB. Some assemblers leave the contents column of the listing
blank to indicate that nothing happens to these registers during loading.

The label on an RMB refers to the first of the bytes reserved. For example, the
statement

WORKCT RMB 2

Reserves a double-byte in memory that probably is a working counter. The

instructions that initialize and adjust the counter will use the label WORKCT to
access it. The RMB directive is used because running the program must initialize
the working counter. Loading a program into memory should not initialize the
working counter.