A Carrier-Based PWM Method with Optimal

Switching Sequence for a Multi-level Four-leg VSI

Jang-Hwan Kim*, Seung-Ki Sul* and Prasad N. Enjeti**

*School of Electrical Engineering & Computer Science **Department of Electrical Engineering

Seoul National University, Texas A&M University,
Gwanak-gu, Seoul 151-744, KOREA. College Station, TX. 77843-3128, USA.
e-mail:ghks95@eepel.snu.ac.kr e-mail:enjeti@ee.tamu.edu

Abstract This paper suggests a multi-level four-leg PWM

voltage source inverter (VSI) as a topology for the high power
Vdc
applications where a function is required to control a zero 2
sequence component as well as dq components. It proposes a
carrier-based PWM method for a multi-level four-leg PWM VSI
along with introducing a new offset voltage. The proposed offset
voltage makes it possible for the switching sequence of all the legs
to be optimized for the minimization of the harmonic distortion of Vdc
the output voltage independently of the number of inverter levels. 2
The feasibility of the proposed PWM method is verified
throughout the spectral analysis, simulation and experimental (a) three-level diode clamped VSI
results. Vdc
4
I. INTRODUCTION
Vdc
Compared to a two-level Voltage Source Inverter (VSI), 4

Multi-level VSI enables to synthesize output voltages with

reduced harmonic distortion and lower Electro-Magnetic
Vdc
Interference (EMI), and also can operate at higher dc link 4

voltages using series connected switches. Even though there

Vdc
are a few disadvantages such as a increased number of 4

switches, a complicated PWM method, and a voltage balancing (b) 5-level diode clamped VSI
problems at the neutral point [3,4], all the benefits make the Fig.1 Circuit diagram of a three-phase multi-level three-leg VSI
multi-level VSI be an attractive topology for a high power
19]. Therefore this paper suggests the multi-level four-leg VSI
application, and it has been used for high power applications
as a power circuit topology for the high power applications in
[2-8] since its first introduction in 1981 [1]. Multi-level diode-
three-phase four-wire system, and also proposes a carrier-based
clamped VSI are shown in Fig.1. Many previous works about
PWM strategy for the multi-level four-leg VSI.
multi-level VSI have been focusing on the three-phase three
wire system [5-9], even though most of high power II. PWM METHODS FOR A THREE-PHASE MULTI-LEVEL THREE-
LEG VSI
applications such as distributed generation, distribution and
Various PWM strategies for a three-phase multi-level
transmission system as well are set up as a four-wire system
three-leg VSI have been developed [5-8]. They could be
[10-13] and practically a zero sequence voltage/current appears
generally classified into two groups, which are space vector
due to unbalanced and/or nonlinear load or unbalanced source
method [6,7] and carrier-based method[5,7,8], according to
in the three-phase four-wire system. When power quality
how to implement them. The space vector method needs to find
circuits such as an active power filter, a static VAR
three switching vectors (dotted in Fig.2) adjacent to desired
compensator, and an UPS are required to be installed in the
output voltage vector on a dq voltage plane as shown in Fig.2.
power system in order to control both dq components and the
Once three switching vectors are identified, the duties of the
zero sequence components, a four-leg VSI is a promising
respective switching vectors should be calculated and then it
candidate that enables to control the three output voltages
finally needs to arrange the respective switching vectors within
independently. Compared with some other topologies in which
a switching period. How to arrange the switching vectors with
a zero sequence component is controllable, the superiority of
minimizing the harmonic distortion of the output waveform,
the four-leg VSI was well described in some literatures [17-
which will be referred to as ‘optimal switching sequence’, is a
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 q generated throughout the comparison between the respective
v 2
Vdc
3 (1) can not guarantee the optimal switching sequence in a case
d
(a) two-level three-leg VSI(n=2)
2
Vdc
3 2(N − 1)
(b) three-level PWM VSI(n=3)
2
Vdc
3 dqo space [14-19] as shown in Fig.4. Hence the three output
(c) 5-level PWM VSI(n=5)
Fig.2 Output voltage planes of a three-phase multi-level three-leg
VSIs, n is the number of the level
well-known fact in a case of a two-level VSI that the zero
switching vectors should be spilt equally and be placed at the
first and the last part of the sequence in a switching period. On
the other hand N. Celanovic et al [6] introduced a simple and
useful method for a multi-level VSI to find the switching
vectors and to calculate the duties of the respective vectors, but
did not propose how to achieve the optimal switching
sequence. Recently, Holmes [8] introduced analytically the
optimal switching sequence where redundant switching vector
was split into two so as to occupy the first and the last part of
the switching sequence with the same duration. It could give a
basic idea of optimal switching sequence for a three-phase
multi-level four-leg VSI.
In order to implement the carrier-based method for the three-
phase N-level three-leg VSI, N-1 triangular carriers and three
references to be compared with the carriers are necessary. The
addition of a proper offset voltage to the phase voltage
references (Vas*,Vbs*,Vcs*) generates the modified references
and the switching signals for each leg’s switches can be
IAS 2005
modified references and N-1 carriers. The optimal switching
sequence can be achieved using the proper offset voltage. Note
that the offset voltage for a two-level three-leg VSI given by
of a multi-level three-leg VSI [9].
*
Vsn = −
( * * *
)
max Vas ,Vbs ,Vcs + min Vas ,Vbs ,Vcs ( * * *
) (1)
2
The appropriate offset voltage for the multi-level three-leg
VSI can be expressed by (2) so that the carrier-based method
has the same optimal switching sequence with that of the space
vector PWM method [8].
Vdc max (Vas ' , Vbs ' , Vcs ') + min (Vas ' , Vbs ' , Vcs ')
Vsn ' = Vsn +
*
− (2)
2
where V xs ' = modV xs * + Vsn * + Vdc , Vdc  , x = a, b, and c.
 2 N −1
III. A CARRIER-BASED PWM METHODS FOR A MULTI-LEVEL
FOUR-LEG VSI
Four-leg VSIs are shown in Fig.3. An existence of the
fourth leg in the four-leg VSI makes it possible for the voltage
output range of the inverter to extend 2-D dq plane into 3-D
voltage references are given by Vaf*,Vbf*, and Vcf*, and they are
controlled independently. It is necessary to manipulate the
switches of the additional leg, which is quite different from the
three-leg VSI. Three-dimensional space vector PWM method
with an optimal switching sequence was proposed [14,15], and
we found out the appropriate offset voltage by which the
carrier-based method would be equivalent to the space vector
modulation with the optimal switching sequence [17]. The
offset voltage for the two-level four-leg VSI is given as (3),
which is different from (1) due to the zero sequence voltage
[17,18]. If this offset in (3) is used for a multi-level VSI, the
optimal switching sequence can not be achieved.
 − Vmax 2 , when Vmin > 0
*  (3)
V fn = − Vmin 2 , when Vmax < 0
− (V + V ) 2 , otherwise
 max min
( ) (
where, V max = max V af * , Vbf * , Vcf * , V min = min V af * , Vbf * , Vcf * )
There are 34 switching vectors in case of a three-level four-
leg VSI, and they can be displayed in dqo space as Fig.4. A
PWM method for a multi-level four-leg VSI was firstly
considered by M. M Prats [15,16]. Even though space vector
method could find the switching vectors and the duties of the
respective vectors with some complicated procedures [16],
how to decide the switching timing of switches for each leg in
order to arrange the respective vectors is a quite different
problem.
100 0-7803-9208-6/05/$20.00 © 2005 IEEE
 Vdc
2

Vdc
2

(a) two-level four-leg VSI

Vdc
2 Fig. 5 Carrier-based PWM method for a multi-level four-leg VSI
Fig. 5 shows the block diagram of a carrier-based PWM
Vdc method for three-phase n-level 4-leg VSI. Note that the
2 proposed offset voltage ‘Vfn’ is used for the control of the
gating signal for the additional leg. The more switches, to
(b) three-level four-leg VSI
Fig.3 Four-leg voltage source inverter increase the number of level, are used in a multi-level VSI, the
more effective the carrier-based PWM method becomes, when
1
it is compared with the space vector PWM method.

0.5 IV. SPECTRAL ANALYSIS OF OUTPUT WAVEFORM

The spectral analysis under various conditions has been
vo 0 carried out. Fig.6 shows some results under a condition where
the references are written using dqo components as (5), where
-0.5
(
Vomax equals to Vdc 1 2 − 1 4 3 [17]. )
1
-1 0
0.5 Vdq * = 0.7 ⋅ Vdc 3 e jωt , Vo * = 0.7 ⋅ Vo max sin ωt (5)
-1 -0.5 0 -0.5
0.5 1 -1 vq
where ω = 2π ⋅ 200 [rad/s] and V af ≈ 0.653 ⋅ V dc sin (ωt ) and
*
vd
Rectangle: switching vectors of a two-level four-leg VSI the magnitude of the voltage is normalized by Vdc.
Circle: switching vectors of a three-level four-leg VSI To reduce the simulation time, both fundamental frequency
Fig.4 Polyhedron: output voltage space of a three-phase 4-leg and carrier frequency are given higher than normal values by
n-level VSI (Normalized by Vdc)
200 Hz and 10 kHz respectively. Generally harmonic contents
There was no explanation about the way to arrange the are dominant around the carrier frequency, but the harmonics
switching vectors, neither was how to achieve the optimal above the carrier frequency can be easily filtered by the electric
switching sequence [15,16]. This paper proposes a carrier- components such as an inductance and capacitance, so that the
based PWM method where the switching sequence is harmonics higher than 15 kHz are excluded from
optimized for minimizing harmonic distortion by a proposed consideration. Under the same references condition as (5),
offset voltage for the multi-level 4-leg VSI. To achieve the THDs according to the number of level or PWM schemes are
optimal switching sequence of n-level 4-leg VSI, the switching summarized at Table I. One of DPWM schemes increases THD
timing of the additional leg should be taken into consideration of the voltage waveform but it should be noted that the
whenever the offset voltage is decided. Therefore it can be switching frequency decreased by DPWM scheme. THD of the
expressed by (4) to generalize N-level four-leg VSI system output voltage of three level VSI is dramatically decreased
including the two-level four-leg VSI. when it operates at the optimal switching sequence by the
V fn =
(4) proposed offset voltage.
V fno * +
Vdc
−
( ) (
max Van * , Vbn * , Vcn * , V fn * + min V an * , Vbn * , Vcn * , V fn * )
2(N − 1) 2 TABLE I. THDS OF OUTPUT VOLTAGES

( ( ) ( ))
,where V fno * = − max Vaf *,Vbf *,Vcf *,V ff * + min Vaf *,Vbf *,Vcf *,V ff * .
Topology Offset voltage THD
2 Two-level four-leg VSI Equation (3) 77.62%

 V V  Two-level four-leg VSI DPWM 82.77%

Vxn * = modVxf * +V fno * + dc , dc  , where x = a, b, c, f .
 2 N −1 Three-level four-leg VSI Equation (3) 22.11%
Three-level four-leg VSI Equation (4) 8.62%
N = 2,3,4,···n. (N is the number of the level, Vff* = 0)

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 (a)two-level four-leg VSI: by (3), Optimal switching sequence (b) two-level four-leg VSI, One of DPWM schemes [19]

(c) three-level four-leg VSI by (3) (d) three-level four-leg VSI: by (4), Optimal switching sequence
Fig.6 Spectral analysis: comparison the waveforms of multi-level four-leg VSI

The reason the offset voltage (3) was used in (c) of Fig. 6
and the Table I is to clarify the fact that compared to the Sine
PWM method, the offset voltage in (3) could be used for the
more utilization of the DC bus voltage by 15% in case of a
three-leg or even multi-level system, but it cannot guarantee
the optimal switching sequence in a multi-level case.

V. DISCONTINUOUS PWM
Discontinuous PWM (DPWM) for a two-level four-leg
VSI introduced in [19] can be extended to multi-level four-leg
VSI system. When the DPWM schemes are applied to the
multi-level VSI, the difference between DPWM schemes of the
two-level VSI and those of multi-level VSI is the fact that it is
possible to gain the non-switching due to the multi-carriers,
even if the pole voltage is not maximum or minimum value.
The additional offset voltages for the multi-level 4-leg VSI are
given by (6-7), where the van*, vbn*, vcn*, vfn* are the same
voltages in (4). DPWM can be achieved by adding one of the
offset voltages voffset_DPWM (6-7) to the offset voltage Vfn as
shown in Fig.7. voffset_DPWM1 allows one of the legs of which
voltage has the maximum value among van*, vbn*, vcn* and vfn*
to be unmodulated, and voffset_DPWM2 makes the leg, whose
voltage has minimum value among them, unmodulated.
Fig.7 Discontinuous PWM method for 4-leg multi-level VSI
VI. SIMULATION AND EXPERIMENTAL RESULTS
The simulation has been carried out to verify the
feasibility of the proposed PWM method. The switching states
of each leg are depicted with a virtual carrier in Fig.8, and it
can be seen that the optimal switching sequence is achieved
using the offset voltage. Fig.9 shows the output waveforms of
the three-level four-leg VSI according to corresponding
references. The performance can be easily verified by the
current waveforms under a three-phase balanced R-L (R=40Ω,
L= 10mH) load condition shown in Fig. 10. It can be seen that
the current flowing through a-phase load equals
0.653 ⋅Vdc sin(ωt − θ ) Z ≈ 4.67 sin (ωt − 0.3044) [A], where

(
voffset _ DPWM 1 = Vdc ( N − 1) − max van* , vbn * , vcn* , v fn * ) (6) θ = tan −1 (ωL R ) and Z = (ωL )2 + R 2 ≈ 42.93Ω . Fig.11 shows the

(
voffset _ DPWM 2 = − min van * , vbn* , vcn* , v fn* ) (7)
refined pole voltage references, while DPWM schemes for 4-
leg multi-level VSI are applied. It shows the variation of the

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pole voltages according to the DPWM schemes, when the same
voltage references are given by (5). Note that non-switching
could happen in the case of 3-level VSI when the refined pole
voltage maintains the value at the level of Vdc/2, -Vdc/2 or 0
during the switching period at least. Fig. 12 shows
experimental results, it is about the DPWM schemes for the
two-level four-leg VSI under the references condition given by
Vdq*=0.97 Vdc 3 e jωt and Vo*= Vo max , when the four-leg VSI
generates unbalanced three-phase voltages. For the
measurement of the PWM pole voltage in experiments, direct
voltage sensing circuit is used, which is specially designed for Fig.9 Output waveforms of the three-level four-leg VSI according to
its references
integrating the pole voltage during sampling period so that the
averaged output voltage (Vaf,Vbf, andVcf) can be measured
precisely as shown in Fig. 12 [20]. It is natural that the
measured voltages are almost identical with the references,
even though different DPWM schemes are applied.
VII. CONCLUSIONS
This paper suggests a multi-level four-leg PWM VSI as a
topology for the high power applications where a function is
required to produce the zero sequence components as well as
dq components. It proposed a carrier-based PWM method for a
multi-level four-leg PWM VSI using an offset voltage. The Fig. 10 Voltage and current waveforms under the references condition
proposed offset voltage makes it possible for the switching as (5)
sequence of all the legs to be optimized for minimizing the
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 (a) Max non-switching in equation (6) for a 4-leg 3-level PWM VSI (b) Min non-switching in equation (7) for 4-leg 3-level PWM
VSI (c) 4-leg 2-level PWM VSI (d) three output voltage references(Vaf*,Vbf*,Vcf*)
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(a) (b) (c)

(d) (e) (f) (g)

From top to bottom: Vaf* and Vaf (100V/div), Van*, Vfn* (38V/div) and Van+0.5Vdc(200V/div), Time scale: 2msec/div
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