Capell Valley Laptop Schematic Diagram 845 (Yonah-Calistoga Mobile Platform)

5 4 3 2 1
YONAH-CALISTOGA Fab 5
Capell
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CUSTOMER REFERENCE REV 1.502
Valley
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BOARD IPN: C75289-501
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D D
Calistoga
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Fan Clocking VCCP VR
Header IMVP-6 VR
Yonah 478 PG 30,31
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PG 5 PG 51, 52 PG 48
uFCPGA
XDP
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CPU
LVDS/ALS/BLI CRT PG 3,4
Thermal PG 37 DDR VR
(DVI-I)
PG 19 Sensor
SODIMM0
PG 18 PG 5 PG 46
FSB Dual Channel
SODIMM1
DDR2
VGA
a
TVOUT
Calistoga PG SYSTEM VR
PG 20 LVDS
21,22,23
1466 PG 49
FCBGA
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PEG/ SDVO PG
C SLEEP CONTROL C
SDVO 6,7,8,9,10,11,12 PG 25
e
PG 13 PCI SLOT3 PG 55
PG 25
h
PCI SLOT4 BATTERY CHARGER VR
X4 DMI 33 Mhz PCI
c
PG 26 PG 50
interface PCI
SATA EDGE-CONN
-s
CC SATA PORT 0
PG 43 PG 28
ICH7M PCIEx1 PG 28 MOBILE POWER
SATA PCIe SLOT0 PCIe SLOT2 ON SEQUENCE
SATA PORT 2
DC 652 PCIEx1 PG 28
p
PG 44 BGA PCIe SLOT1
PATA PCIEx1
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PG
B PG 39 B
t
14-17 PCIEx1
BACK PANEL FPIO/DB BACK PANEL FPIO/DB
USB 2.0 PCIEx1
2.0 2.0 2.0 2.0
PCIE
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PCIEx1
8 USB ports total
USB6
USB5
USB7
USB4
SPI DOCKING
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HD AUDIO/ AC97
DOCKING BACK PANEL FPIO/DB BACK PANEL LPC, 33MHz
.
RJ45
2.0 2.0 2.0 2.0 Tekoa/EkronR LAN
HD AUDIO / PORT PG 33, 34
USB0
USB1
USB2
TPM SIO
USB3
MDC 1.5 80-83
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HEADER PG 41 PG 35 PG 42
SPI
PG 27 IR/ SERIAL Flash
BACK PANEL USB FPIO/DB USB
PG 45 PG 33
PG 40 PG 29
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A LPC A
SMC/KSC SLOT LPC Capell Valley Intel Confidential
FWH PG 35 DOCK Title
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8 Mbit PG 32 PG 57 TITLE PAGE
PG 24
Size Document Number Rev
A D15378
EMA 1.501
SCN KB/ PS2
PG 36 PG 38 Date: Wednesday, July 20, 2005 Sheet 1 of 60
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5 4 3 2 1
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CALISTOGA CUSTOMER REFERENCE
PLATFORM
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SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
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D D
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Default Jumper Settings For Stuffed Jumpers
2
I C / SMB Addresses Jumper Default Description Page
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J3B1 1-2 H_THERMDA 5
Voltage Rails Device Address Hex Bus J3B1 3-4 H_THERMDC 5
Clock Generator 1101 001x D2/D3* SMB_ICH_S3 J6H1 1-X CMOS CLEAR 14
POWER PLANE VOLTAGE S3COLD ACTIVE DESCRIPTION Spread Spectrum Clock 1101 010x D4/D5* SMB_ICH_S3 J8H1 1-X BIOS RECOVERY 16
+VBATA 9V-12.5V S0, S3, S4, S5 Battery Rail in Mobile Power Mode PCI Express Clock 1101 110x DC/DD* SMB_ICH_S3 J2J10 2-3 CRB/SV DETECT 16
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+VBAT 9V-12.5V S0, S3, S4, S5 Battery Rail in Mobile Power Mode SO-DIMM0 1010 010x A4 SMB_ICH_S2 J9J8 MFG/TEST 16
SO-DIMM1 1010 000x A0 SMB_ICH_S2 J1F4 1-2 BSEL2 30
+VBATS 9V-12.5V S0 Battery Rail in Mobile Power Mode DDR Thermal Sensor 0100 1100 4C SMB_ICH_S2 J1G1 1-2 BSEL1 30
+V12S 12V S0 Only on in DT Power Mode IC2 Buss Expander 0011 xxxx 3x J1G2 1-2 BSEL0 30
-V12A -12V S0, S3,S4,S5 Only on in DT Power Mode Ambient Light Sensor 0111 0010 72 AON_ALS J9J2 1-2 MDO 32
-V12S -12V S0 Only on in DT Power Mode Always ON Display 011 110x 3C SMB_ICH J9J6 1-2 MD1 32
+V5A 5V S0, S3,S4,S5 Thermal Diode 1001 100B 4C SMB_THRM J9J4 1-X MD2 32
Battery A 0001 0110 16 SMB_BS J9J1 1-X KSC DISABLE 32
+V5 5V S0, S3 Battery B 11110 1E SMB_BS J9J7 1-X VB JMPR 32
+V5S 5V S0 LAN 1100 1000 1E SMB_BS J9J5 1-X LID JMPR 32
a
+V3.3A 3.3V S0, S3,S4,S5 PCI Express Docking TBD TBD SMB_ICH_A1 J8G1 1-2 SMC RST# 32
+V3.3 3.3V S0, S3 Trusted Platform Module TBD TBD J8A1 1-X LAN PROTECT 33
+V3.3S 3.3V S0 J9G3 1-2 BOOT BLOCK PROG 38
+V1.5S 1.5V S0 J9H1 1-X NMI JMPR 38
1.8V
J7J3 1-2 PATA HotSwap 39
+V1.8 S0, S3 DDR core J7E1 1-X PORT80 SEL 41
+V0.9 0.9V S0, S3 DDR command & control pull up. * First address is for a write command and second is for a read command. J7E3 1-2 SIO RST# 42
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+V2.5S 2.5V S0 J9J3 1-2 SATA DET 44
+V2.5_LAN 2.5V S0, S3 LAN Rail Buses labeled SMB_ICH_xx come out of ICH, via an I2C expander. The J5H2 1-2 SATA HotSwap 44
+V1.2 1.2V S0, S3 LAN Rail rest come out of EC.
J7A3 1-2 H8 PROG# 45
+1.05S 1.05V S0 GMCH, ICH core, and FSB rail
J7A4 1-2 H8 PROG# 45
C J3H1 1-X SHUTDOWN 54 C
+VCC_CORE 0.700V-1.77V S0 CPU core rail
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LEDs and Switches
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LED Page Reference
ATA Activity LED 14 CR7J1
SMC/KBC Num Lock 32 CR9G1
SMC/KBC Scroll Lock 32 CR9G2
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SMC/KBC Caps Lock 32 CR9G3
VID0 45 CR1B1
VID1 45 CR1B2
VID2 45 CR1B3
VID3 45 CR1B4
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VID4 45 CR1B5
VID5 45 CR1B5
VID6 45 CR1C1
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S0 State 55 CR3G1
S3 State 55 CR3G2
S4 State 55 CR3G3
S5 State 55 CR2G1
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Switch Page Reference
Power On/Off 54 SW1C1
Reset 54 SW1C2
LID 32 SW9J2
Virtual battery 32 SW9J1
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PCI Devices
B B
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Device IDSEL # REQ/GNT # Interrupts
Slot 3 AD18 2 2 C, D, B, A
Slot 4 AD19 3 3 D, C, F, G
Wake Events
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LAN (AD24 internal)
Wake Events State Supported

RI# from serial port S3
PME# from PCI, mini PCI slot/device, LPC S3
Net Naming Conventions PCB Footprints
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slot/device S3
PCI Express, mini PCI Express, Newcard wake event S3
Suffix Wake on LAN S3
# = Active Low Signal SOT-23 SOT23-5 LID switch attached to SMC S3
.
1 1 5 USB S3
Prefix
AC97/Azalia wake on ring S3
H = Host
3 As seen from top 2 SmLink for AOLII S3
M = DDR Memory
TP = Test Point (does not connect anywhere else) Hot Key from Scan matrix keyboard S3
PS/2 Keyboard/mouse S3
2 3 4 PWRBTN# S3, S4, S5
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Power States
SIGNAL SLP SLP +V*A +V* +V*S Clocks
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S4# S5#
STATE
A A
HIGH HIGH ON ON ON ON Capell Valley Intel Confidential
Full ON
Title
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HIGH HIGH ON ON OFF OFF
S3 (Suspend to RAM) NOTES
LOW HIGH ON OFF OFF OFF
S4 (Suspend To Disk)
S5 / Soft OFF
LOW LOW ON OFF OFF OFF A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 2 of 60
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4,6,9,10,14,17,30,37,45,48,53,56,58 +V1.05S
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6 H_A#[31:3]
U2E1A
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H_A#3 J4 H1 R3T5
A[3]# ADS# H_ADS# 6 56
H_A#4 L4 E2
A[4]# BNR# H_BNR# 6
H_A#5 M3 G5
A[5]# BPRI# H_BPRI# 6
H_A#6 K5 A[6]#
ADDR GROUP 0
H_A#7 M1 H5
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A[7]# DEFER# H_DEFER# 6
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# 6
D H_A#9 J1 A[9]# DBSY# E1 H_DBSY# 6 Place testpoint on D
.
H_A#10 N3
H_A#11 P5
A[10]#
F1
H_IERR# with a GND
A[11]# BR0# H_BREQ#0 6
H_A#12 P2 A[12]#
0.1" away
CONTROL
H_A#13 L1 D20 H_IERR#
H_A#14 A[13]# IERR#
P4 INIT# B3 H_INIT# 14
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H_A#15 A[14]#
P1 A[15]#
H_A#16 R1 H4
A[16]# LOCK# H_LOCK# 6
6 H_ADSTB#0 L2 ADSTB[0]# H_CPURST# 6,37
6 H_REQ#[4:0] RESET# B1 H_RS#[2:0] 6
H_REQ#0 K3 F3 H_RS#0
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H_REQ#1 REQ[0]# RS[0]# H_RS#1
H2 REQ[1]# RS[1]# F4
H_REQ#2 K2 G3 H_RS#2
H_REQ#3 REQ[2]# RS[2]#
J3 REQ[3]# TRDY# G2 H_TRDY# 6
H_REQ#4 L5 REQ[4]#
6 H_A#[31:3] HIT# G6 H_HIT# 6
H_A#17 Y2 E4
A[17]# HITM# H_HITM# 6
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4 XDP_BPM#0 37
ADDR GROUP 1
H_A#20 W6 AD3
A[20]# BPM[1]# XDP_BPM#1 30
H_A#21
a
U4 A[21]# BPM[2]# AD1 XDP_BPM#2 30
XDP/ITP SIGNALS
H_A#22 Y5 AC4
A[22]# BPM[3]# XDP_BPM#3 30,58
H_A#23 U2 AC2
A[23]# PRDY# XDP_BPM#4 37
H_A#24 R4 AC1 +V1.05S 4,6,9,10,14,17,30,37,45,48,53,56,58
A[24]# PREQ# XDP_BPM#5 37
H_A#25 T5 AC5
A[25]# TCK XDP_TCK 37
H_A#26 T3 AA6
A[26]# TDI XDP_TDI 37
H_A#27 W3 AB3
A[27]# TDO XDP_TDO 37 6 H_D#[63:0] H_D#[63:0] 6
H_A#28 W5 AB5 R3R1 U2E1B
A[28]# TMS XDP_TMS 37
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H_A#29 Y4 AB6 75 H_D#0 E22 AA23 H_D#32
A[29]# TRST# XDP_TRST# 37 D[0]# D[32]#
Layout note: no stub H_A#30 W2 C20 H_D#1 F24 AB24 H_D#33
A[30]# DBR# XDP_DBRESET# 37,54,58 D[1]# D[33]#
H_A#31 Y1 H_D#2 E26 V24 H_D#34
on H_STPCLK TP A[31]# H_D#3 D[2]# D[34]# H_D#35
6 H_ADSTB#1 V4 D21 H_PROCHOT# 51 H22 V26
THERM
ADSTB[1]# PROCHOT# D[3]# D[35]#

C THERMDA A24 H_THERMDA 5
H_D#4 F23 D[4]# D[36]# W25 H_D#36 C
DATA GRP 0
DATA GRP 2
H_D#5 H_D#37
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H_STPCLK#_R 14 H_A20M# A6 A20M# THERMDC A25 H_THERMDC 5 G25 D[5]# D[37]# U23
A5 PM_THRMTRIP# should connect H_D#6 E25 U25 H_D#38
14 H_FERR# FERR# PM_THRMTRIP# 7,14 D[6]# D[38]#
NO_STUFF C4 C7 H_D#7 E23 U22 H_D#39
TP2F1
14 H_IGNNE# IGNNE# THERMTRIP# to ICH7 and GMCH without H_D#8 D[7]# D[39]# H_D#40
PM_THRMTRIP# 7,14 K24 D[8]# D[40]# AB25
R2F2 D5 T-ing (No stub) H_D#9 G24 W22 H_D#41
14 H_STPCLK# STPCLK# D[9]# D[41]#
0 C6 H_D#10 J24 Y23 H_D#42
H CLK
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14 H_INTR LINT0 D[10]# D[42]#
B4 A22 H_D#11 J23 AA26 H_D#43
14,35 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 30 D[11]# D[43]#
A3 A21 H_D#12 H26 Y26 H_D#44
14,35,58 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 30 D[12]# D[44]#
H_D#13 F26 Y22 H_D#45
TP_A32# H_D#14 D[13]# D[45]# H_D#46
AA1 RSVD[01] K22 D[14]# D[46]# AC26
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TP_A33# AA4 T22 TP_EXTBREF H_D#15 H25 AA24 H_D#47
TP_A34# RSVD[02] RSVD[12] D[15]# D[47]#
AB2 RSVD[03] 6 H_DSTBN#0 H23 DSTBN[0]# DSTBN[2]# W24 H_DSTBN#2 6
A#[32-39], APM#[0-1]: TP_A35# AA3 G22 Y25
RSVD[04] 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 6
TP_A36# M4 D2 TP_SPARE0 J26 V23
RESERVED
Leave escape routing on TP_A37# RSVD[05] RSVD[13] TP_SPARE1

6 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 6
N5 RSVD[06] RSVD[14] F6 6 H_D#[63:0] H_D#[63:0] 6
-s
for future functionality TP_A38# T2 D3 TP_SPARE2
TP_A39# RSVD[07] RSVD[15] TP_SPARE3 H_D#16 H_D#48
V3 RSVD[08] RSVD[16] C1 N22 D[16]# D[48]# AC22
TP_APM0# B2 AF1 TP_SPARE4 H_D#17 K25 AC23 H_D#49
TP_APM1# RSVD[09] RSVD[17] TP_SPARE5 H_D#18 D[17]# D[49]# H_D#50
C3 RSVD[10] RSVD[18] D22 P26 D[18]# D[50]# AB22
C23 TP_SPARE6 H_D#19 R23 AA21 H_D#51
TP_HFPLL RSVD[19] TP_SPARE7 H_D#20 D[19]# D[51]# H_D#52
B25 RSVD[11] RSVD[20] C24 L25 D[20]# D[52]# AB21
H_D#21 L22 AC25 H_D#53
DATA GRP 1
D[21]# D[53]#
DATA GRP 3
Yonah Ball-out Rev 1.0 H_D#22 L23 AD20 H_D#54
D[22]# D[54]#
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H_D#23 M23 AE22 H_D#55
H_D#24 D[23]# D[55]# H_D#56
P25 D[24]# D[56]# AF23
H_D#25 P22 AD24 H_D#57
H_D#26 D[25]# D[57]# H_D#58 Layout note:
P23 D[26]# D[58]# AE21
H_D#27 T24 AD21 H_D#59 Comp0,2 connect with Zo=27.4ohm, make
4,6,9,10,14,17,30,37,45,48,53,56,58 +V1.05S H_D#28 D[27]# D[59]# H_D#60
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R24 D[28]# D[60]# AE25 trace length shorter than 0.5".
H_D#29 L26 AF25 H_D#61
H_D#30 D[29]# D[61]# H_D#62 Comp1,3 connect with Zo=55ohm, make
T25 D[30]# D[62]# AF22
B B
t
4,6,9,10,14,17,30,37,45,48,53,56,58 +V1.05S H_D#31 N24 AF26 H_D#63 trace length shorter than 0.5".
R3T1 D[31]# D[63]#
6 H_DSTBN#1 M24 DSTBN[1]# DSTBN[3]# AD23 H_DSTBN#3 6
1K N25 AE24
6 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 6
XDP_TMS R1R4 54.9 1% 1% M26 AC20
6 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 6
p
AD26 R26 COMP0 R3T3 27.4 1%
58 H_GTLREF GTLREF COMP[0]
XDP_TDI R2R3 54.9 1% MISC U26 COMP1 R3T2 54.9 1%
COMP[1] COMP2 R2T2 27.4 1%
COMP[2] U1
Layout note: Zo=55 ohm, R3R3 NO_STUFF R3U2 1K ACLKPH C26 V1 COMP3 R2T1 54.9 1%
XDP_BPM#5 R1R3 54.9 1% 2K TEST1 COMP[3]
0.5" max for GTLREF. 1% R3U1 51DCLKPH
la
D25 TEST2 DPRSTP# E5 H_DPRSTP# 14,35
J2G1 B5
DPSLP# H_DPSLP# 14,35
DPWR# D24 H_DPWR# 6
XDP_TCK R2R4 54.9 1% B22 D6
30 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD 14,35
B23 BSEL[1] SLP# D7 H_CPUSLP# 6,35
30 CPU_BSEL1
.
C21 AE6 R2U4 1K
30 CPU_BSEL2 BSEL[2] PSI# PSI# H_PWRGD_XDP 37
Yonah Ball-out Rev 1.0
Layout: Connect Place Series
test point TP3F1 TP3F1 Resistor on
with no stub
NO_STUFF H_PWRGD_XDP
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Without Stub
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NO_STUFF TP3D1 TP_CPN_L1 NO_STUFF TP3D2
A A
NO_STUFF TP3D3 TP_CPN_L3 NO_STUFF TP3D4 Capell Valley Intel Confidential
NO_STUFF TP3D5 TP_CPN_L6 NO_STUFF TP3D6 Title
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NO_STUFF TP3D7 TP_CPN_L8 NO_STUFF TP3D8 CPU (1 of 2)

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
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U2E1D
A4 VSS[001] VSS[082] P6
53,56,58 +VCC_CORE 53,56,58 +VCC_CORE A8 P21
U2E1C VSS[002] VSS[083]
A11 P24
c
VSS[003] VSS[084]
A7 VCC[001] VCC[068] AB20 A14 VSS[004] VSS[085] R2
D A9 VCC[002] VCC[069] AB7 A16 VSS[005] VSS[086] R5 D
.
A10 VCC[003] VCC[070] AC7 A19 VSS[006] VSS[087] R22
A12 VCC[004] VCC[071] AC9 A23 VSS[007] VSS[088] R25
A13 VCC[005] VCC[072] AC12 A26 VSS[008] VSS[089] T1
A15 VCC[006] VCC[073] AC13 B6 VSS[009] VSS[090] T4
A17 VCC[074] AC15 B8 VSS[091] T23
s
VCC[007] VSS[010]
A18 VCC[008] VCC[075] AC17 B11 VSS[011] VSS[092] T26
A20 VCC[009] VCC[076] AC18 B13 VSS[012] VSS[093] U3
B7 VCC[010] VCC[077] AD7 B16 VSS[013] VSS[094] U6
B9 VCC[011] VCC[078] AD9 B19 VSS[014] VSS[095] U21
B10 AD10 B21 U24
it c
VCC[012] VCC[079] VSS[015] VSS[096]
B12 VCC[013] VCC[080] AD12 B24 VSS[016] VSS[097] V2
B14 VCC[014] VCC[081] AD14 C5 VSS[017] VSS[098] V5
B18 VCC[017] VCC[084] AD18 C14 VSS[020] VSS[101] W1
B20 VCC[018] VCC[085] AE9 C16 VSS[021] VSS[102] W4
C9 VCC[019] VCC[086] AE10 C19 VSS[022] VSS[103] W23
C10 VCC[020] VCC[087] AE12 C2 VSS[023] VSS[104] W26
C12 VCC[021] VCC[088] AE13 C22 VSS[024] VSS[105] Y3
a
C13 VCC[022] VCC[089] AE15 C25 VSS[025] VSS[106] Y6
C15 VCC[023] VCC[090] AE17 D1 VSS[026] VSS[107] Y21
C17 VCC[024] VCC[091] AE18 D4 VSS[027] VSS[108] Y24
C18 VCC[025] VCC[092] AE20 D8 VSS[028] VSS[109] AA2
D9 VCC[026] VCC[093] AF9 D11 VSS[029] VSS[110] AA5
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D18 VCC[032] VCC[099] AF18 E3 VSS[035] VSS[116] AA22
E7 AF20 +V1.05S 3,6,9,10,14,17,30,37,45,48,53,56,58 E6 AA25
VCC[033] VCC[100] VSS[036] VSS[117]
C E9 VCC[034] E8 VSS[037] VSS[118] AB1 C
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E10 VCC[035] VCCP[01] V6 E11 VSS[038] VSS[119] AB4
E12 VCC[036] VCCP[02] G21 E14 VSS[039] VSS[120] AB8
E13 J6 C3T1 E16 AB11
VCC[037] VCCP[03] 270uF VSS[040] VSS[121]
E15 VCC[038] VCCP[04] K6 20% E19 VSS[041] VSS[122] AB13
E17 VCC[039] VCCP[05] M6 E21 VSS[042] VSS[123] AB16
E18 J21 E24 AB19
h
VCC[040] VCCP[06] VSS[043] VSS[124]
E20 VCC[041] VCCP[07] K21 F5 VSS[044] VSS[125] AB23
F7 VCC[042] VCCP[08] M21 F8 VSS[045] VSS[126] AB26
F9 VCC[043] VCCP[09] N21 F11 VSS[046] VSS[127] AC3
F10 N6 10,17,27,48,56,58 +V1.5S F13 AC6
VCC[044] VCCP[10] VSS[047] VSS[128]
c
F12 VCC[045] VCCP[11] R21 F16 VSS[048] VSS[129] AC8
F14 R6 +V1.5S 10,17,27,48,56,58 F19 AC11
VCC[046] VCCP[12] VSS[049] VSS[130]
F15 VCC[047] VCCP[13] T21 F2 VSS[050] VSS[131] AC14
F17 T6 C3T4 C3T3 LAYOUT NOTE: PLACE C3T4 F22 AC16
VCC[048] VCCP[14] VSS[051] VSS[132]
F18 VCCP[15] V21 F25 VSS[133] AC19
VCC[049] NEAR PIN B26 VSS[052]
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F20 W21 0.01uF 10uF G4 AC21
VCC[050] VCCP[16] VSS[053] VSS[134]
AA7 VCC[051] G1 VSS[054] VSS[135] AC24
AA9 VCC[052] VCCA B26 G23 VSS[055] VSS[136] AD2
-
AA10 VCC[053] G26 VSS[056] VSS[137] AD5
AA12 53,56,58 +VCC_CORE H3 AD8
VCC[054] VSS[057] VSS[138]
AA13 VCC[055] VID[0] AD6 H_VID0 51 H6 VSS[058] VSS[139] AD11
AA15 VCC[056] VID[1] AF5 H_VID1 51 H21 VSS[059] VSS[140] AD13
AA17 VCC[057] VID[2] AE5 H_VID2 51 H24 VSS[060] VSS[141] AD16
p
AA18 VCC[058] VID[3] AF4 H_VID3 51 J2 VSS[061] VSS[142] AD19
AA20 VCC[059] VID[4] AE3 H_VID4 51 J5 VSS[062] VSS[143] AD22
AB9 VCC[060] VID[5] AF2 H_VID5 51 J22 VSS[063] VSS[144] AD25
AC10 AE2 R2R1 J25 AE1
VCC[061] VID[6] H_VID6 51 100 VSS[064] VSS[145]
AB10 VCC[062] 1% K1 VSS[065] VSS[146] AE4
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AB12 VCC[063] K4 VSS[066] VSS[147] AE8
AB14 AF7 Layout Note: K23 AE11
VCC[064] VCCSENSE VCCSENSE VSS[067] VSS[148]
AB15 VCC[065] Route VCCSENSE and VSSSENSE traces at K26 VSS[068] VSS[149] AE14
B B
t
AB17 VCC[066] 27.4 Ohms with 50 mil spacing. L3 VSS[069] VSS[150] AE16
AB18 VCC[067] VSSSENSE AE7 VSSSENSE Place PU and PD within 1 inch of CPU. L6 VSS[070] VSS[151] AE19
L21 VSS[071] VSS[152] AE23
Yonah Ball-out Rev 1.0 R2R2 L24 AE26
100 VSS[072] VSS[153]
1% M2 VSS[073] VSS[154] AF3
p
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
la
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] AF24
Yonah Ball-out Rev 1.0
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A A
Capell Valley Intel Confidential
Title
w
CPU (2 of 2)

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
o m
7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
CPU Thermal Sensor
7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
c
D Layout Note: R3N4
10K
R3N6
10K
D
.
Route H_THERMDA and C3N2
H_THERMDC on same layer 0.1uF
J3B1
w/ 10 mil trace & 10 mil R3N7
Default Stuffing: 1-2 3-4
spacing. Route away from 10K U3B2
Option Stuffing: 1-X 3-X SMB_THRM_CLK 32,35
s
noise sources with ground 1 VDD 8
SCLK
guard tracks on each side.
J3B1 THERM_DXP R3N3 499 1% ADT_THERM_DXP
2 D+ 7
C3N3 SDATA
3 H_THERMDA 1 2 SMB_THRM_DATA 32,35
3 4 ADT_THERM_DXN
3 D- 6 THRM_ALERT#
it c
3 H_THERMDC THERM_DXN R3N8 499 1% 1000pF ALRT#/THM2#
2X2HDR ADT_THM# 4 5
THM# GND PM_THRM# 16,32,35
R3N5 0
ADT7461A-TEMP MON NO_STUFF
Note: No-Stuff R3N5 for normal

operation. No Stuff R9G18 if
R3N5 is stuffed
3Pin_Recepticle
J4A1
a
2 1
THERMDP THERMDN
GND0 GND2
GND1 3 4 5 6 GND3
m
NO_STUFF
C Thermal Diode Conn C
h e
s c
p -
o
B Fan Power Control B
t
Place fan connector near CPU
p
Q2B3
SI7458DP J3C1
10,17,18,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S 3
V5S_FAN
la
2 5 1
1 2
3
C3D1 C3B2
R2B4 C2B4 CR3D1 CONN2_HDR
.
1M 0.1uF 22uF 1N4148
4
1000pF
1
3 FAN_ON_Q
FAN_ON_D#
R2B3
w
100K
Q2B2
1 BSS138
32,35 FAN_ON
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2
A A
Title
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CPU THERMAL SENSOR AND FAN

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
H_XRCOMP
m
R4T3
24.9
1%
o
U5E1A
3 H_D#[63:0] H_D#0 H_A#[31:3] 3
3,4,9,10,14,17,30,37,45,48,53,56,58 +V1.05S F1 H9 H_A#3
H_D#1 H_D#_0 H_A#_3 H_A#4
J1 C9
c
H_D#2 H_D#_1 H_A#_4 H_A#5
H1 H_D#_2 H_A#_5 E11
D H_D#3 J6 G11 H_A#6 D
H_D#4 H_D#_3 H_A#_6
.
R4E3 H3 F11 H_A#7
54.9 H_D#5 H_D#_4 H_A#_7 H_A#8
K2 H_D#_5 H_A#_8 G12
1% H_D#6 G1 F9 H_A#9
H_D#7 H_D#_6 H_A#_9 H_A#10
G2 H_D#_7 H_A#_10 H11
H_XSCOMP H_D#8 K9 J12 H_A#11
H_D#_8
s
H_D#9 H_A#_11 H_A#12
K1 H_D#_9 H_A#_12 G14
H_D#10 K7 D9 H_A#13
H_D#11 H_D#_10 H_A#_13 H_A#14
J8 H_D#_11 H_A#_14 J14
H_D#12 H4 H13 H_A#15
3,4,9,10,14,17,30,37,45,48,53,56,58 +V1.05S H_D#13 H_D#_12 H_A#_15 H_A#16
J3 J15
it c
H_D#14 H_D#_13 H_A#_16 H_A#17
K11 H_D#_14 H_A#_17 F14
H_D#15 G4 D12 H_A#18
H_D#16 H_D#_15 H_A#_18 H_A#19
T10 H_D#_16 H_A#_19 A11
R4E8 H_D#17 W11 C11 H_A#20
221 H_D#18 H_D#_17 H_A#_20 H_A#21
1% T3 H_D#_18 H_A#_21 A12
H_D#19 U7 A13 H_A#22
H_D#20 H_D#_19 H_A#_22 H_A#23
U9 H_D#_20 H_A#_23 E13
H_D#21 U11 G13 H_A#24
H_XSWING 58 H_D#22 H_D#_21 H_A#_24 H_A#25
T11 H_D#_22 H_A#_25 F12 Note: H_CPURST#
H_D#23 H_A#26
a
W9 B12
H_D#24 T1
H_D#_23 H_A#_26
B14 H_A#27 has T topology
H_D#25 H_D#_24 H_A#_27 H_A#28
T8 H_D#_25 H_A#_28 C12
R4T4 C4T8 H_D#26 T4 A14 H_A#29 3,4,9,10,14,17,30,37,45,48,53,56,58 +V1.05S
100 H_D#27 H_D#_26 H_A#_29 H_A#30
1% W7 H_D#_27 H_A#_30 C14
0.1uF H_D#28 U5 D14 H_A#31
H_D#29 H_D#_28 H_A#_31 R4E5
T9 H_D#_29
H_D#30 100
W6 H_D#_30 H_ADS# E8 H_ADS# 3 1%
H_D#31
m
T5 H_D#_31 H_ADSTB#_0 B9 H_ADSTB#0 3
H_D#32 AB7 C13
H_D#33 H_D#_32 H_ADSTB#_1 H_ADSTB#1 3
AA9 H_D#_33 H_VREF J13 H_VREF
HOST
H_D#34 W4 C6
H_D#_34 H_BNR# H_BNR# 3
C H_D#35 W3 H_D#_35 H_BPRI# F6 H_BPRI# 3
C5T10 C
3,4,9,10,14,17,30,37,45,48,53,56,58 +V1.05S H_D#36 0.1uF R4E4
e
Y3 H_D#_36 H_BREQ#0 C7 H_BREQ#0 3
H_D#37 Y7 B7 200
H_D#38 H_D#_37 H_CPURST# H_CPURST# 3,37 1%
W5 H_D#_38 H_DBSY# A7 H_DBSY# 3
H_D#39 Y10 C3
H_D#_39 H_DEFER# H_DEFER# 3
R4T2 H_D#40 AB8 J9
H_D#41 H_D#_40 H_DPWR# H_DPWR# 3
54.9 W2 H8
h
H_D#42 H_D#_41 H_DRDY# H_DRDY# 3
1% AA4 K13
H_D#43 H_D#_42 H_VREF
AA7 H_D#_43 H_DINV#[3:0] 3
H_D#44 AA2 J7 H_DINV#0
H_YSCOMP H_D#45 H_D#_44 H_DINV#_0 H_DINV#1
AA6 H_D#_45 H_DINV#_1 W8
H_D#46 H_DINV#2
c
AA10 H_D#_46 H_DINV#_2 U3
H_D#47 Y8 AB10 H_DINV#3
H_D#48 H_D#_47 H_DINV#_3
AA1 H_D#_48 H_DSTBN#[3:0] 3
H_D#49 AB4 K4 H_DSTBN#0
H_D#50 H_D#_49 H_DSTBN#_0 H_DSTBN#1
AC9 H_D#_50 H_DSTBN#_1 T7
s
3,4,9,10,14,17,30,37,45,48,53,56,58 +V1.05S H_D#51 AB11 Y5 H_DSTBN#2
H_D#52 H_D#_51 H_DSTBN#_2 H_DSTBN#3
AC11 H_D#_52 H_DSTBN#_3 AC4
H_D#53 AB3 H_D#_53 H_DSTBP#[3:0] 3
-
H_D#54 AC2 K3 H_DSTBP#0
R4E2 H_D#55 H_D#_54 H_DSTBP#_0
AD1 T6 H_DSTBP#1
221 H_D#56 H_D#_55 H_DSTBP#_1
AD9 AA5 H_DSTBP#2
1% H_D#57 H_D#_56 H_DSTBP#_2
AC1 AC5 H_DSTBP#3
H_D#58 H_D#_57 H_DSTBP#_3
AD7 H_D#_58
H_D#59
p
H_YSWING 58 AC6 H_D#_59
H_D#60 AB5 D3
H_D#61 H_D#_60 H_HIT# H_HIT# 3
AD10 H_D#_61 H_HITM# D4 H_HITM# 3
H_D#62 AD4 B3
H_D#63 H_D#_62 H_LOCK# H_LOCK# 3
AC8 H_D#_63
R4E1 C4T5
o
100 H_XRCOMP
1% E1 H_XRCOMP H_REQ#[4:0] 3
0.1uF H_XSCOMP E2 D8 H_REQ#0
B H_XSCOMP H_REQ#_0 B
t
H_XSWING E4 G8 H_REQ#1
H_XSWING H_REQ#_1
B8 H_REQ#2
H_YRCOMP H_REQ#_2
Y1 F8 H_REQ#3
H_YSCOMP H_YRCOMP H_REQ#_3
U1 A8 H_REQ#4
H_YSWING H_YSCOMP H_REQ#_4
W1 H_YSWING H_RS#[2:0] 3
p
B4 H_RS#0
H_RS#_0
AG2 E6 H_RS#1
30 CLK_MCH_BCLK H_CLKIN H_RS#_1
H_YRCOMP AG1 D6 H_RS#2
30 CLK_MCH_BCLK# H_CLKIN# H_RS#_2
H_SLPCPU# E3 H_CPUSLP# 3,35

R4T1
la
H_TRDY# E7 H_TRDY# 3
24.9
1% CALISTOGA_1p0
w .
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A A
Title
w
CALISTOGA (1 OF 6)

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
m
10,58 +V1.5S_PCIE
U5E1C R5E1 24.9 1%

D32 L_BKLTCTL EXP_A_COMPI D40 PEG_COMP
U5E1B 19 L_BKLTCTL
J30 L_BKLTEN EXP_A_COMPO D38
o
MCH_RSVD_[2:1] MCH_RSVD_0 19 L_BKLTEN
H32 RSVD_0 H30 L_CLKCTLA PEG_RXN[15:0] 13
MCH_RSVD_1 19,37 L_CLKCTLA PEG_RXN0
T32 RSVD_1 SM_CK_0 AY35 M_CLK_DDR0 21 H29 L_CLKCTLB EXP_A_RXN_0 F34
MCH_RSVD_2 19,37 L_CLKCTLB PEG_RXN1
R32 RSVD_2 SM_CK_1 AR1 M_CLK_DDR1 21 19 L_DDC_CLK G26 L_DDC_CLK EXP_A_RXN_1 G38
TP_MCH_RSVD_3 F3 RSVD_3 AW7 G25 H34 PEG_RXN2
TP_MCH_RSVD_4 SM_CK_2 M_CLK_DDR2 22 19 L_DDC_DATA L_IBG L_DDC_DATA EXP_A_RXN_2
F7 RSVD_4 AW40 B38 J38 PEG_RXN3
c
SM_CK_3 M_CLK_DDR3 22 L_IBG EXP_A_RXN_3
RSVD
MCH_RSVD_5 AG11 RSVD_5 TP5E1 NO_STUFF L_LVBG C35 L34 PEG_RXN4
MCH_RSVD_6 L_VBG EXP_A_RXN_4
D AF11 RSVD_6 SM_CK#_0 AW35 M_CLK_DDR#0 21 19 L_VDDEN F32 L_VDDEN EXP_A_RXN_5 M38 PEG_RXN5 D
MCH_RSVD_7
.
H7 RSVD_7 AT1 C33 N34 PEG_RXN6
MCH_RSVD_8 SM_CK#_1 M_CLK_DDR#1 21 L_VREFH EXP_A_RXN_6
J19 RSVD_8 AY7 C32 P38 PEG_RXN7
MCH_RSVD_9 SM_CK#_2 M_CLK_DDR#2 22 L_VREFL EXP_A_RXN_7
A41 RSVD_9 AY40 R34 PEG_RXN8
MCH_RSVD_10 SM_CK#_3 M_CLK_DDR#3 22 EXP_A_RXN_8
A35 RSVD_10 A33 T38 PEG_RXN9
MCH_RSVD_11 19 LA_CLKN LA_CLK# EXP_A_RXN_9
A34 RSVD_11 AU20 A32 V34 PEG_RXN10
SM_CKE_0 M_CKE0 21,23 19 LA_CLKP LA_CLK
s
MCH_RSVD_12 EXP_A_RXN_10 PEG_RXN11
D28 RSVD_12 SM_CKE_1 AT20 M_CKE1 21,23 19 LB_CLKN E27 LB_CLK# EXP_A_RXN_11 W38
MCH_RSVD_13 D27 RSVD_13 BA29 E26 Y34 PEG_RXN12
SM_CKE_2 M_CKE2 22,23 19 LB_CLKP LB_CLK EXP_A_RXN_12
AY29 AA38 PEG_RXN13
SM_CKE_3 M_CKE3 22,23 EXP_A_RXN_13
LVDS
C37 AB34 PEG_RXN14
19 LA_DATAN0 LA_DATA#_0 EXP_A_RXN_14
AW13 B35 AC38 PEG_RXN15
it c
SM_CS#_0 M_CS#0 21,23 19 LA_DATAN1 LA_DATA#_1 EXP_A_RXN_15
30 MCH_BSEL0 SM_CS#_1 AW12 M_CS#1 21,23 19 LA_DATAN2 A37 LA_DATA#_2 PEG_RXP[15:0] 13
MUXING
K16 AY21 D34 PEG_RXP0
30 MCH_BSEL1 CFG_0 SM_CS#_2 M_CS#2 22,23 EXP_A_RXP_0
GRAPHICS
K18 AW21 F38 PEG_RXP1
30 MCH_BSEL2 CFG_1 SM_CS#_3 M_CS#3 22,23 EXP_A_RXP_1
J18 G34 PEG_RXP2
12,13 MCH_CFG_[20:3] MCH_CFG_3 CFG_2 TP_M_OCDCOMP_0 EXP_A_RXP_2 PEG_RXP3
F18 CFG_3 SM_OCDCOMP_0 AL20 19 LA_DATAP0 B37 LA_DATA_0 EXP_A_RXP_3 H38
MCH_CFG_4 E15 AF10 TP_M_OCDCOMP_1 B34 J34 PEG_RXP4
MCH_CFG_5 CFG_4 SM_OCDCOMP_1 19 LA_DATAP1 LA_DATA_1 EXP_A_RXP_4
F15 A36 L38 PEG_RXP5
MCH_CFG_6 CFG_5 19 LA_DATAP2 LA_DATA_2 EXP_A_RXP_5
E18 BA13 M34 PEG_RXP6
MCH_CFG_7 CFG_6 SM_ODT_0 M_ODT0 21,23 EXP_A_RXP_6
D19 BA12 N38 PEG_RXP7
MCH_CFG_8 CFG_7 SM_ODT_1 M_ODT1 21,23 EXP_A_RXP_7 PEG_RXP8
a
D16 CFG_8 SM_ODT_2 AY20 M_ODT2 22,23 19 LB_DATAN0 G30 LB_DATA#_0 EXP_A_RXP_8 P34
CFG
MCH_CFG_9 G16 AU21 D30 R38 PEG_RXP9
MCH_CFG_10 CFG_9 SM_ODT_3 M_ODT3 22,23 19 LB_DATAN1 LB_DATA#_1 EXP_A_RXP_9
DDR
E16 F29 T34 PEG_RXP10
MCH_CFG_11 CFG_10 M_RCOMP# 19 LB_DATAN2 LB_DATA#_2 EXP_A_RXP_10
D15 AV9 V38 PEG_RXP11
MCH_CFG_12 CFG_11 SM_RCOMP# M_RCOMP EXP_A_RXP_11 PEG_RXP12
G15 CFG_12 SM_RCOMP AT9 EXP_A_RXP_12 W34
MCH_CFG_13 K15 Y38 PEG_RXP13
MCH_CFG_14 CFG_13 EXP_A_RXP_13 PEG_RXP14
C15 CFG_14 SM_VREF_0 AK1 M_VREF_MCH 47,58 19 LB_DATAP0 F30 LB_DATA_0 EXP_A_RXP_14 AA34
PCI-EXPRESS
MCH_CFG_15 H16 AK41 D29 AB38 PEG_RXP15
MCH_CFG_16 CFG_15 SM_VREF_1 19 LB_DATAP1 LB_DATA_1 EXP_A_RXP_15
m
G18 CFG_16 19 LB_DATAP2 F28 LB_DATA_2 PEG_TXN[15:0] 13
MCH_CFG_17 H15 Layout Note: F36 PEG_TXN0
MCH_CFG_18 CFG_17 EXP_A_TXN_0 PEG_TXN1
J25 CFG_18 G_CLKIN# AF33 CLK_PCIE_3GPLL# 31 Place 150 Ohm termination
EXP_A_TXN_1 G40
MCH_CFG_19 K27 AG33 resistors close to GMCH H36 PEG_TXN2
CFG_19 G_CLKIN CLK_PCIE_3GPLL 31 EXP_A_TXN_2
C MCH_CFG_20 PEG_TXN3 C
CLK
J26 CFG_20 D_REFCLKIN# A27 DREFCLK# 30 EXP_A_TXN_3 J40
PEG_TXN4
e
D_REFCLKIN A26 DREFCLK 30 18,20 TV_DACA_OUT A16 TV_DACA_OUT EXP_A_TXN_4 L36
G28 C40 C18 M40 PEG_TXN5
16 PM_BMBUSY# PM_BMBUSY# D_REFSSCLKIN# DREFSSCLK# 30 18,20 TV_DACB_OUT TV_DACB_OUT EXP_A_TXN_5
F25 D41 A19 N36 PEG_TXN6
21,23 PM_EXTTS#0 PM_EXTTS#_0 D_REFSSCLKIN DREFSSCLK 30 18,20 TV_DACC_OUT TV_DACC_OUT EXP_A_TXN_6
PM
TV
PM_EXTTS#1_R
H26 P40 PEG_TXN7
R6E4 0 PM_EXTTS#_1 R5T3 150 1% R4T5 TVIREF J20 EXP_A_TXN_7 PEG_TXN8
22,23 PM_EXTTS#1 G6 PM_THRMTRIP# DMI_TXN[3:0] 15 TV_IREF EXP_A_TXN_8 R36
AH33 AE35 DMI_TXN0 R4T7 150 1% 4.99k B16 T40 PEG_TXN9
h
3,14 PM_THRMTRIP# PWROK DMI_RXN_0 DMI_TXN1 R4T6 150 1% 1% TV_IRTNA EXP_A_TXN_9 PEG_TXN10
16 DELAY_VR_PWRGOOD AH34 RSTIN# DMI_RXN_1 AF39 B18 TV_IRTNB EXP_A_TXN_10 V36
AG35 DMI_TXN2 B19 W40 PEG_TXN11
13,15,24,28,32,41,42,57 DMI_RXN_2 DMI_TXN3 TV_IRTNC EXP_A_TXN_11
R5R1 100 RST_IN#_MCH AH39 Y36 PEG_TXN12
PLT_RST# DMI_RXN_3 EXP_A_TXN_12
MISC
H28 K30 AA40 PEG_TXN13

13 SDVO_CTRLCLK SDVO_CTRLCLK 20 TV_DCONSEL0 TV_DCONSEL0 EXP_A_TXN_13
c
H27 J29 AB36 PEG_TXN14
13 SDVO_CTRLDATA SDVO_CTRLDATA DMI_TXP0 DMI_TXP[3:0] 15 20 TV_DCONSEL1 TV_DCONSEL1 EXP_A_TXN_14
K28 AC35 AC40 PEG_TXN15
15 MCH_ICH_SYNC# LT_RESET# DMI_RXP_0 DMI_TXP1 EXP_A_TXN_15
DMI_RXP_1 AE39 PEG_TXP[15:0] 13
31 CLK_MCH_OE# DMI_TXP2 PEG_TXP0
DMI_RXP_2 AF35 18 CRT_BLUE E23 CRT_BLUE EXP_A_TXP_0 D36
TP_MCH_NC0 D1 AG39 DMI_TXP3 Layout Note: D23 F40 PEG_TXP1
NC0 DMI_RXP_3 CRT_BLUE# EXP_A_TXP_1
-s
TP_MCH_NC1 C41 Place 150 Ohm termination C22 G36 PEG_TXP2
NC1 18 CRT_GREEN CRT_GREEN EXP_A_TXP_2
VGA
TP_MCH_NC2 C1 resistors close to GMCH B22 H40 PEG_TXP3
TP_MCH_NC3 NC2 DMI_RXN[3:0] 15 CRT_GREEN# EXP_A_TXP_3
BA41 NC3 DMI_TXN_0 AE37 DMI_RXN0 18 CRT_RED A21 CRT_RED EXP_A_TXP_4 J36 PEG_TXP4
TP_MCH_NC4 BA40 AF41 DMI_RXN1 R5T4 150 1% B21 L40 PEG_TXP5
NC4 DMI_TXN_1 CRT_RED# EXP_A_TXP_5
NC
TP_MCH_NC5 BA39 NC5 DMI_TXN_2 AG37DMI_RXN2 R5T5 150 1%

EXP_A_TXP_6 M36 PEG_TXP6
TP_MCH_NC6 BA3 AH41DMI_RXN3 R5T6 150 1% N40 PEG_TXP7
TP_MCH_NC7 NC6 DMI_TXN_3 EXP_A_TXP_7
DMI
BA2 C26 P36 PEG_TXP8

TP_MCH_NC8 NC7 18 CRT_DDC_CLK CRT_DDC_CLK EXP_A_TXP_8
BA1 C25 R40 PEG_TXP9
TP_MCH_NC9 NC8 DMI_RXP0 DMI_RXP[3:0] 15 18 CRT_DDC_DATA CRT_DDC_DATA EXP_A_TXP_9
p
B41 AC37 G23 T36 PEG_TXP10
TP_MCH_NC10 NC9 DMI_TXP_0 CRT_HSYNC EXP_A_TXP_10
B2 NC10 DMI_TXP_1 AE41 DMI_RXP1 J22 CRT_IREF EXP_A_TXP_11 V40 PEG_TXP11
TP_MCH_NC11 AY41 AF37 DMI_RXP2 H23 W36 PEG_TXP12
TP_MCH_NC12 NC11 DMI_TXP_2 CRT_VSYNC EXP_A_TXP_12
AY1 NC12 DMI_TXP_3 AG41DMI_RXP3 18 CRT_HSYNC
R5E7 39 HSYNC
EXP_A_TXP_13 Y40 PEG_TXP13
TP_MCH_NC13 AW41 AA36 PEG_TXP14
NC13 EXP_A_TXP_14
VSYNC
TP_MCH_NC14 R5E5 255 1% CRTIREF PEG_TXP15
o
AW1 NC14 EXP_A_TXP_15 AB40
TP_MCH_NC15 A40
TP_MCH_NC16 NC15 CALISTOGA_1p0
A4 NC16
B B
t
TP_MCH_NC17 A39 R5E6 39
TP_MCH_NC18 NC17 18 CRT_VSYNC
A3 NC18
CALISTOGA_1p0
p
PM_EXTTS#1_R R6E5 0 R7N3 0
NO_STUFF PM_DPRSLPVR 16,35,51 L_IBG
la
58 EPOT_WIPER
NO_STUFF
R7N4
1.5K
.
1%
+V3.3S 5,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
R5P2 10K PM_EXTTS#0
w
R5P3 10K PM_EXTTS#1
+V1.8 9,21,22,34,46,47,56,58
w
R4R1
80.6
1%
A M_RCOMP# A
M_RCOMP
Title
w
R4R2
80.6 CALISTOGA (2 OF 6)
1%

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
o m
c
21 M_A_DQ[63:0] 22 M_B_DQ[63:0]
U5E1D U5E1E
D M_A_DQ0 AJ35 AU12 M_B_DQ0 AK39 D
M_A_DQ1 SA_DQ0 SA_BS_0 M_A_BS0 21,23 M_B_DQ1 SB_DQ0
.
AJ34 SA_DQ1 SA_BS_1 AV14 M_A_BS1 21,23 AJ37 SB_DQ1 SB_BS_0 AT24 M_B_BS0 22,23
M_A_DQ2 AM31 BA20 M_B_DQ2 AP39 AV23
M_A_DQ3 SA_DQ2 SA_BS_2 M_A_BS2 21,23 M_B_DQ3 SB_DQ2 SB_BS_1 M_B_BS1 22,23
AM33 SA_DQ3 M_A_CAS# 21,23 AR41 SB_DQ3 SB_BS_2 AY28 M_B_BS2 22,23
M_A_DQ4 AJ36 AY13 M_B_DQ4 AJ38
M_A_DQ5 SA_DQ4 SA_CAS# M_A_DM0 M_A_DM[7:0] 21 M_B_DQ5 SB_DQ4 M_B_CAS# 22,23
AK35 SA_DM_0 AJ33 AK38 SB_CAS# AR24 M_B_DM[7:0] 22
s
M_A_DQ6 SA_DQ5 M_A_DM1 M_B_DQ6 SB_DQ5 M_B_DM0
AJ32 SA_DQ6 SA_DM_1 AM35 AN41 SB_DQ6 SB_DM_0 AK36
M_A_DQ7 AH31 AL26 M_A_DM2 M_B_DQ7 AP41 AR38 M_B_DM1
M_A_DQ8 SA_DQ7 SA_DM_2 M_A_DM3 M_B_DQ8 SB_DQ7 SB_DM_1 M_B_DM2
AN35 SA_DQ8 SA_DM_3 AN22 AT40 SB_DQ8 SB_DM_2 AT36
M_A_DQ9 AP33 AM14 M_A_DM4 M_B_DQ9 AV41 BA31 M_B_DM3
AR31 AL9 AU38 AL17
it c
AP31 SA_DQ11 SA_DM_6 AR3 AV38 SB_DQ11 SB_DM_5 AH8
M_A_DQ12 AN38 AH4 M_A_DM7 M_B_DQ12 AP38 BA5 M_B_DM6
M_A_DQ13 SA_DQ12 SA_DM_7 M_B_DQ13 SB_DQ12 SB_DM_6 M_B_DM7
AM36 SA_DQ13 M_A_DQS[7:0] 21 AR40 SB_DQ13 SB_DM_7 AN4
A
M_A_DQ14 AM34 AK33 M_A_DQS0 M_B_DQ14 AW38
SA_DQ14 SA_DQS_0 SB_DQ14 M_B_DQS[7:0] 22
B
M_A_DQ15 AN33 AT33 M_A_DQS1 M_B_DQ15 AY38 AM39 M_B_DQS0
M_A_DQ16 SA_DQ15 SA_DQS_1 M_A_DQS2 M_B_DQ16 SB_DQ15 SB_DQS_0 M_B_DQS1
AK26 SA_DQ16 SA_DQS_2 AN28 BA38 SB_DQ16 SB_DQS_1 AT39
M_A_DQ17 AL27 AM22 M_A_DQS3 M_B_DQ17 AV36 AU35 M_B_DQS2
AM26 AN12 AR36 AR29
MEMORY
AN24 AN8 AP36 AR16
MEMORY
a
AK28 SA_DQ20 SA_DQS_6 AP3 BA36 SB_DQ20 SB_DQS_5 AR10
M_A_DQ21 AL28 AG5 M_A_DQS7 M_B_DQ21 AU36 AR7 M_B_DQS6
M_A_DQ22 SA_DQ21 SA_DQS_7 M_A_DQS#0 M_A_DQS#[7:0] 21 M_B_DQ22 SB_DQ21 SB_DQS_6 M_B_DQS7
AM24 SA_DQ22 SA_DQS#_0 AK32 AP35 SB_DQ22 SB_DQS_7 AN5 M_B_DQS#[7:0] 22
M_A_DQ23 AP26 AU33 M_A_DQS#1 M_B_DQ23 AP34 AM40 M_B_DQS#0
M_A_DQ24 SA_DQ23 SA_DQS#_1 M_A_DQS#2 M_B_DQ24 SB_DQ23 SB_DQS#_0 M_B_DQS#1
AP23 SA_DQ24 SA_DQS#_2 AN27 AY33 SB_DQ24 SB_DQS#_1 AU39
M_A_DQ25 AL22 AM21 M_A_DQS#3 M_B_DQ25 BA33 AT35 M_B_DQS#2
AP21 SA_DQ26 SA_DQS#_4 AM12 AT31 SB_DQ26 SB_DQS#_3 AP29
M_A_DQ27 AN20 AL8 M_A_DQS#5 M_B_DQ27 AU29 AP16 M_B_DQS#4
m
AL23 SA_DQ28 SA_DQS#_6 AN3 AU31 SB_DQ28 SB_DQS#_5 AT10
M_A_DQ29 AP24 AH5 M_A_DQS#7 M_B_DQ29 AW31 AT7 M_B_DQS#6
M_A_DQ30 SA_DQ29 SA_DQS#_7 M_B_DQ30 SB_DQ29 SB_DQS#_6 M_B_DQS#7
AP20 SA_DQ30 M_A_A[13:0] 21,23 AV29 SB_DQ30 SB_DQS#_7 AP5
M_A_DQ31 AT21 AY16 M_A_A0 M_B_DQ31 AW29
SYSTEM
SA_DQ31 SA_MA_0 SB_DQ31 M_B_A[13:0] 22,23

C M_A_DQ32 AR12 AU14 M_A_A1 M_B_DQ32 AM19 AY23 M_B_A0 C
SYSTEM
M_A_DQ33 SA_DQ32 SA_MA_1 M_A_A2 M_B_DQ33 SB_DQ32 SB_MA_0 M_B_A1
e
AR14 SA_DQ33 SA_MA_2 AW16 AL19 SB_DQ33 SB_MA_1 AW24
M_A_DQ34 AP13 BA16 M_A_A3 M_B_DQ34 AP14 AY24 M_B_A2
AP12 SA_DQ35 SA_MA_4 BA17 AN14 SB_DQ35 SB_MA_3 AR28
M_A_DQ36 AT13 AU16 M_A_A5 M_B_DQ36 AN17 AT27 M_B_A4
AT12 SA_DQ37 SA_MA_6 AV17 AM16 SB_DQ37 SB_MA_5 AT28
M_A_DQ38 AL14 AU17 M_A_A7 M_B_DQ38 AP15 AU27 M_B_A6
h
AL12 SA_DQ39 SA_MA_8 AW17 AL15 SB_DQ39 SB_MA_7 AV28
M_A_DQ40 AK9 AT16 M_A_A9 M_B_DQ40 AJ11 AV27 M_B_A8
AN7 SA_DQ41 SA_MA_10 AU13 AH10 SB_DQ41 SB_MA_9 AW27
M_A_DQ42 AK8 AT17 M_A_A11 M_B_DQ42 AJ9 AV24 M_B_A10
c
AK7 SA_DQ43 SA_MA_12 AV20 AN10 SB_DQ43 SB_MA_11 BA27
M_A_DQ44 M_A_A13 M_B_DQ44 M_B_A12
DDR
AP9 SA_DQ44 SA_MA_13 AV12 AK13 SB_DQ44 SB_MA_12 AY27

M_A_DQ45 M_B_DQ45 M_B_A13
DDR
AN9 SA_DQ45 AH11 SB_DQ45 SB_MA_13 AR23
M_A_DQ46 AT5 AW14 M_B_DQ46 AK10
M_A_DQ47 SA_DQ46 SA_RAS# M_A_RAS# 21,23 M_B_DQ47 SB_DQ46
AL5 SA_DQ47 SA_RCVENIN# AK23 TP_MA_RCVENIN# AJ8 SB_DQ47 SB_RAS# AU23 M_B_RAS# 22,23
s
M_A_DQ48 AY2 AK24 TP_MA_RCVENOUT# M_B_DQ48 BA10 AK16 TP_MB_RCVENIN#
M_A_DQ49 SA_DQ48 SA_RCVENOUT# M_B_DQ49 SB_DQ48 SB_RCVENIN#
AW2 SA_DQ49 SA_WE# AY14 M_A_WE# 21,23 AW10 SB_DQ49 SB_RCVENOUT# AK18 TP_MB_RCVENOUT#
M_A_DQ50 AP1 M_B_DQ50 BA4 AR27
SA_DQ50 SB_DQ50 SB_WE# M_B_WE# 22,23
-
M_A_DQ51 AN2 M_B_DQ51 AW4
M_A_DQ52 SA_DQ51 M_B_DQ52 SB_DQ51
AV2 SA_DQ52 AY10 SB_DQ52
M_A_DQ53 AT3 M_B_DQ53 AY9
AN1 SA_DQ54 AW5 SB_DQ54
M_A_DQ55 AL2 M_B_DQ55 AY5
p
AG7 SA_DQ56 AV4 SB_DQ56
M_A_DQ57 AF9 M_B_DQ57 AR5
AG4 SA_DQ58 AK4 SB_DQ58
M_A_DQ59 AF6 M_B_DQ59 AK3
AG9 SA_DQ60 AT4 SB_DQ60
M_A_DQ61 M_B_DQ61
o
AH6 SA_DQ61 AK5 SB_DQ61
M_A_DQ62 AF4 M_B_DQ62 AJ5
AF8 SA_DQ63 AJ3 SB_DQ63
B B
t
CALISTOGA_1p0 CALISTOGA_1p0
la p
w .
w
A A
Title
w
CALISTOGA (3 OF 6)

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
+V1.05S 3,4,6,10,14,17,30,37,45,48,53,56,58
U5E1G
AA33 VCC_0
W33 VCC_1
m
P33 VCC_2
N33 VCC_3
L33 VCC_4 VCC_SM_0 AU41
J33 VCC_5 VCC_SM_1 AT41 VCCSM_LF4
AA32 VCC_6 VCC_SM_2 AM41 VCCSM_LF5 C5D2 +V1.05S 3,4,6,10,14,17,30,37,45,48,53,56,58
o
Y32 VCC_7 AU40 C5D4
VCC_SM_3 0.47uF
W32 VCC_8 VCC_SM_4 BA34
V32 VCC_9 AY34 0.47uF
VCC_SM_5
P32 VCC_10 VCC_SM_6 AW34
N32 VCC_11 AV34 U5E1F
c
VCC_SM_7 C4T7 C4T6 C5T6 C5T2 C5T7 C5T4 C5T5 C5T3
M32 VCC_12 VCC_SM_8 AU34 AD27 VCC_NCTF0
D L32 VCC_13 AT34 270uF 270uF 10uF 1uF 10uF 0.22uF 0.22uF 0.22uF AC27 AE27 D
VCC_SM_9 20% VCC_NCTF1 VSS_NCTF0
.
J32 VCC_14 AR34 2.0V, 3.3Arms 20% AB27 AE26
VCC_SM_10 VCC_NCTF2 VSS_NCTF1
AA31 VCC_15 VCC_SM_11 BA30 AA27 VCC_NCTF3 VSS_NCTF2 AE25
W31 VCC_16 VCC_SM_12 AY30 Y27 VCC_NCTF4 VSS_NCTF3 AE24
V31 VCC_17 VCC_SM_13 AW30 W27 VCC_NCTF5 VSS_NCTF4 AE23
T31 VCC_18 VCC_SM_14 AV30 V27 VSS_NCTF5 AE22
s
VCC_NCTF6
R31 VCC_19 VCC_SM_15 AU30 U27 VCC_NCTF7 VSS_NCTF6 AE21
P31 VCC_20 VCC_SM_16 AT30 T27 VCC_NCTF8 VSS_NCTF7 AE20
N31 VCC_21 VCC_SM_17 AR30 R27 VCC_NCTF9 VSS_NCTF8 AE19
M31 VCC_22 VCC_SM_18 AP30 AD26 VCC_NCTF10 VSS_NCTF9 AE18
AA30 VCC_23 AN30 AC26 AC17
it c
Y30 VCC_24 VCC_SM_20 AM30 AB26 VCC_NCTF12 VSS_NCTF11 Y17
W30 VCC_25 VCC_SM_21 AM29 AA26 VCC_NCTF13 VSS_NCTF12 U17
V30 VCC_26 VCC_SM_22 AL29 Y26 VCC_NCTF14
U30 VCC_27 VCC_SM_23 AK29 W26 VCC_NCTF15
T30 VCC_28 VCC_SM_24 AJ29 V26 VCC_NCTF16
R30 VCC_29 AH29 U26 10,58 +V1.5S_AUX
VCC_SM_25 VCC_NCTF17
P30 VCC_30 VCC_SM_26 AJ28 T26 VCC_NCTF18
N30 VCC_31 VCC_SM_27 AH28 R26 VCC_NCTF19 VCCAUX_NCTF0 AG27
M30 VCC_32 VCC_SM_28 AJ27 AD25 VCC_NCTF20 VCCAUX_NCTF1 AF27
a
L30 VCC_33 VCC_SM_29 AH27 AC25 VCC_NCTF21 VCCAUX_NCTF2 AG26
AA29 VCC_34 VCC_SM_30 BA26 AB25 VCC_NCTF22 VCCAUX_NCTF3 AF26
Y29 VCC_35 VCC_SM_31 AY26 AA25 VCC_NCTF23 VCCAUX_NCTF4 AG25
W29 VCC_36 VCC_SM_32 AW26 Y25 VCC_NCTF24 VCCAUX_NCTF5 AF25
V29 VCC_37 VCC_SM_33 AV26 W25 VCC_NCTF25 VCCAUX_NCTF6 AG24
U29 VCC_38 VCC_SM_34 AU26 V25 VCC_NCTF26 VCCAUX_NCTF7 AF24
R29 VCC_39 VCC_SM_35 AT26 U25 VCC_NCTF27 VCCAUX_NCTF8 AG23
P29 VCC_40 VCC_SM_36 AR26 T25 VCC_NCTF28 VCCAUX_NCTF9 AF23
m
M29 VCC_41 VCC_SM_37 AJ26 R25 VCC_NCTF29 VCCAUX_NCTF10 AG22
L29 VCC_42 VCC_SM_38 AH26 AD24 VCC_NCTF30 VCCAUX_NCTF11 AF22
AB28 VCC_43 VCC_SM_39 AJ25 AC24 VCC_NCTF31 VCCAUX_NCTF12 AG21
AA28 VCC_44 VCC_SM_40 AH25 AB24 VCC_NCTF32 VCCAUX_NCTF13 AF21
C Y28 VCC_45 VCC_SM_41 AJ24 AA24 VCC_NCTF33 VCCAUX_NCTF14 AG20 C
e
V28 VCC_46 VCC_SM_42 AH24 Y24 VCC_NCTF34 VCCAUX_NCTF15 AF20
U28 VCC_47 VCC_SM_43 BA23 W24 VCC_NCTF35 VCCAUX_NCTF16 AG19
T28 VCC_48 AJ23 C5D3 V24 AF19
VCC_SM_44 VCC_NCTF36 VCCAUX_NCTF17
R28 VCC_49 VCC_SM_45 BA22 U24 VCC_NCTF37 VCCAUX_NCTF18 R19
P28 VCC_50 AY22 0.47uF T24 AG18
N28 VCC_51 AW22 R24 AF18
h
M28 VCC_52 VCC_SM_48 AV22 AD23 VCC_NCTF40 VCCAUX_NCTF21 R18
L28 VCC_53 VCC_SM_49 AU22 V23 VCC_NCTF41 VCCAUX_NCTF22 AG17
P27 VCC_54 VCC_SM_50 AT22 U23 VCC_NCTF42 VCCAUX_NCTF23 AF17
N27 VCC_55 VCC_SM_51 AR22 T23 VCC_NCTF43 VCCAUX_NCTF24 AE17
c
M27 VCC_56 VCC_SM_52 AP22 R23 VCC_NCTF44 VCCAUX_NCTF25 AD17
L27 VCC_57 VCC_SM_53 AK22 AD22 VCC_NCTF45 VCCAUX_NCTF26 AB17
P26 VCC_58 VCC_SM_54 AJ22 V22 VCC_NCTF46 VCCAUX_NCTF27 AA17
N26 VCC_59 VCC_SM_55 AK21 U22 VCC_NCTF47 VCCAUX_NCTF28 W17
L26 VCC_60 VCC_SM_56 AK20 T22 VCC_NCTF48 VCCAUX_NCTF29 V17
s
N25 VCC_61 VCC_SM_57 BA19 R22 VCC_NCTF49 VCCAUX_NCTF30 T17
M25 VCC_62 AY19 AD21 R17
L25 VCC_63
VCC_SM_58
VCC_SM_59 AW19 V21
VCC_NCTF50
VCC_NCTF51 NCTF VCCAUX_NCTF31
VCCAUX_NCTF32 AG16
-
P24 VCC_64 VCC_SM_60 AV19 U21 VCC_NCTF52 VCCAUX_NCTF33 AF16
N24 VCC_65 VCC_SM_61 AU19 T21 VCC_NCTF53 VCCAUX_NCTF34 AE16
M24 VCC_66 VCC_SM_62 AT19 R21 VCC_NCTF54 VCCAUX_NCTF35 AD16
AB23 VCC_67 VCC_SM_63 AR19 AD20 VCC_NCTF55 VCCAUX_NCTF36 AC16
AA23 VCC_68 AP19 V20 AB16
VCC VCC_SM_64 VCC_NCTF56 VCCAUX_NCTF37
p
Y23 VCC_69 VCC_SM_65 AK19 U20 VCC_NCTF57 VCCAUX_NCTF38 AA16
P23 VCC_70 VCC_SM_66 AJ19 T20 VCC_NCTF58 VCCAUX_NCTF39 Y16
N23 VCC_71 VCC_SM_67 AJ18 R20 VCC_NCTF59 VCCAUX_NCTF40 W16
M23 VCC_72 VCC_SM_68 AJ17 AD19 VCC_NCTF60 VCCAUX_NCTF41 V16
L23 VCC_73 VCC_SM_69 AH17 V19 VCC_NCTF61 VCCAUX_NCTF42 U16
o
AC22 VCC_74 VCC_SM_70 AJ16 U19 VCC_NCTF62 VCCAUX_NCTF43 T16
AB22 VCC_75 VCC_SM_71 AH16 T19 VCC_NCTF63 VCCAUX_NCTF44 R16
Y22 VCC_76 VCC_SM_72 BA15 AD18 VCC_NCTF64 VCCAUX_NCTF45 AG15
B B
t
W22 VCC_77 VCC_SM_73 AY15 AC18 VCC_NCTF65 VCCAUX_NCTF46 AF15
P22 VCC_78 VCC_SM_74 AW15 AB18 VCC_NCTF66 VCCAUX_NCTF47 AE15
N22 VCC_79 VCC_SM_75 AV15 AA18 VCC_NCTF67 VCCAUX_NCTF48 AD15
M22 VCC_80 VCC_SM_76 AU15 Y18 VCC_NCTF68 VCCAUX_NCTF49 AC15
L22 VCC_81 VCC_SM_77 AT15 W18 VCC_NCTF69 VCCAUX_NCTF50 AB15
p
AC21 VCC_82 VCC_SM_78 AR15 V18 VCC_NCTF70 VCCAUX_NCTF51 AA15
AA21 VCC_83 VCC_SM_79 AJ15 U18 VCC_NCTF71 VCCAUX_NCTF52 Y15
W21 VCC_84 VCC_SM_80 AJ14 T18 VCC_NCTF72 VCCAUX_NCTF53 W15
N21 VCC_85 VCC_SM_81 AJ13 VCCAUX_NCTF54 V15
M21 VCC_86 VCC_SM_82 AH13 VCCAUX_NCTF55 U15
la
L21 VCC_87 VCC_SM_83 AK12 VCCAUX_NCTF56 T15
AC20 VCC_88 VCC_SM_84 AJ12 VCCAUX_NCTF57 R15
AB20 VCC_89 VCC_SM_85 AH12
Y20 VCC_90 VCC_SM_86 AG12 CALISTOGA_1p0
W20 VCC_91 VCC_SM_87 AK11
.
P20 VCC_92 VCC_SM_88 BA8
N20 VCC_93 VCC_SM_89 AY8
M20 VCC_94 VCC_SM_90 AW8
L20 VCC_95 VCC_SM_91 AV8
AB19 VCC_96 VCC_SM_92 AT8
AA19 VCC_97 VCC_SM_93 AR8
Y19 VCC_98 AP8 +V1.8 7,21,22,34,46,47,56,58
VCC_SM_94
w
N19 VCC_99 VCC_SM_95 BA6
M19 VCC_100 VCC_SM_96 AY6
L19 VCC_101 VCC_SM_97 AW6
N18 VCC_102 VCC_SM_98 AV6
M18 VCC_103 VCC_SM_99 AT6
L18 VCC_104 AR6 C5R4 C5R3 C5D1
VCC_SM_100
P17 VCC_105 AP6
w
VCC_SM_101
N17 VCC_106 AN6 10uF 10uF 0.47uF
VCC_SM_102
M17 VCC_107 VCC_SM_103 AL6
N16 VCC_108 AK6 Place C5D1 near
A VCC_SM_104
PLACE IN CAVITY A
M16 VCC_109
L16 VCC_110
VCC_SM_105 AJ6
AV1 VCCSM_LF2
pin BA15 on Capell Valley Intel Confidential
VCC_SM_106 Layer1
VCC_SM_107 AJ1 VCCSM_LF1
C4D1 C4D2 Title
w
CALISTOGA_1p0
0.47uF 0.47uF CALISTOGA (4 OF 6)

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
18,20,49,56,58 +V2.5S 4,17,27,48,56,58 +V1.5S
+V1.5S 4,17,27,48,56,58 NOTE: CAPS USED IN
NOTE: 0.1uF caps +V3.3_TVDAC should be
m
within 250mils of C5T14 C5T17
in 1.5SxPLL need C5T8 0.1uF
to be located as edge of MCH 3,4,6,9,14,17,30,37,45,48,53,56,58 +V1.05S 0.1uF 10uF
U5E1H
edge caps within H22 VCCSYNC
o
47,56 +V3.3S_TVDAC +VCCA_TVDAC C4E5 +V3.3S_TVDACA 18,20,49,56,58 +V2.5S AC14
200mils FB4F1 VTT_0
22nF C30 VCC_TXLVDS0 VTT_1 AB14
+V1.5S_DPLLA 3 1 B30 W14
L5F1 C4F6 VCC_TXLVDS1 VTT_2
A30 VCC_TXLVDS2 VTT_3 V14
1 2 180ohm@100MHz 10uF C4F3 7,58 +V1.5S_PCIE T14
c
10uH 10% +80-20% VTT_4
2
0.1uF AJ41 VCC3G0 VTT_5 R14
C5U1
D C5U2
+V3.3S_TVDACB
AB41 VCC3G1 VTT_6 P14 D
.
470uF C4E4 Y41 N14
20% +V1.5S_3GPLL VCC3G2 VTT_7
0.1uF V41 M14
18,20,49,56,58 +V2.5S VCC3G3 VTT_8
22nF R41 VCC3G4 VTT_9 L14
3 1 N41 VCC3G5 VTT_10 AD13
C5R6 C5T1 L41 AC13
VCC3G6 VTT_11
s
+V1.5S_DPLLB C4F2 AC33 AB13
L6F1 0.1uF 10uF VCCA_3GPLL VTT_12
2
0.1uF G41 VCCA_3GBG VTT_13 AA13
1 2 H41 VSSA_3GBG VTT_14 Y13
10uH 10% C4E3 W13
C6F1 C5T13 +V3.3S_TVDACC 58 +V2.5S_CRTDAC VTT_15 18,20,49,56,58 +V2.5S
F21 V13
it c
22nF VCCA_CRTDAC0 VTT_16
470uF 3 1 1 3 VCCA_CRTDAC E21 U13
20% VCCA_CRTDAC1 VTT_17
0.1uF G21 VSSA_CRTDAC T13
C4F1 C5F2 C5F1 +V1.5S_DPLLA VTT_18
VTT_19 R13
22nF +V1.5S_DPLLB C5T15 C5F6
2
0.1uF B26 VCCA_DPLLA VTT_20 N13
0.1uF +V1.5S_HPLL C39 M13 4.7uF
+V1.5S_HPLL VCCA_DPLLB VTT_21 0.1uF
AF1 VCCA_HPLL VTT_22 L13
18,20,49,56,58 +V2.5S AB12
FB4D2 VTT_23
1 2 A38 VCCA_LVDS VTT_24 AA12
B39 VSSA_LVDS VTT_25 Y12
120ohm@100MHz C4T1 C4R5 C5T11 C5T12 +V1.5S_MPLL
a
VTT_26 W12
22uF AF2 V12
20% C5E6 0.01uF 0.1uF VCCA_MPLL VTT_27
0.1uF U12
+V3.3S_ATVBG VTT_28 18,20,49,56,58 +V2.5S
22nF H20 VCCA_TVBG VTT_29 T12
3 1 G20 VSSA_TVBG VTT_30 R12
+V1.5S_MPLL P12
VTT_31
VTT_32 N12
C5F5
2
VTT_33 M12
+V3.3S_TVDACA
m
FB4D1
1 2 E19 L12 C5E3
0.1uF +V3.3S_TVDACB VCCA_TVDACA0 VTT_34
F19 VCCA_TVDACA1 VTT_35 R11 0.1uF
120ohm@100MHz C4R3 C4R4
C20 VCCA_TVDACB0 VTT_36 P11
22uF D20 N11
+V3.3S_TVDACC VCCA_TVDACB1 VTT_37
C 20% 0.1uF E20 M11 C
VCCA_TVDACC0
POWER VTT_38
e
F20 VCCA_TVDACC1 VTT_39 R10
4,17,27,48,56,58 +V1.5S P10
VTT_40
AH1 VCCD_HMPLL0 VTT_41 N10
AH2 VCCD_HMPLL1 VTT_42 M10
3,4,6,9,14,17,30,37,45,48,53,56,58 +V1.05S 4,17,27,48,56,58 +V1.5S P9
VTT_43
A28 N9 NOTE: .1uF CAPS USED IN
h
+V2.5S 18,20,49,56,58 VCCD_LVDS0 VTT_44
NOTE: CAPS USED IN B28 VCCD_LVDS1 VTT_45 M9
+V1.5S_DLVDS, +V2.5S_ALVDS,
C28 VCCD_LVDS2 VTT_46 R8
+V2.5_CRTDAC should 58 +V1.5S_TVDAC P8 +V2.5S_TXLVDS, +V2.5S_3GBG
R5U5 CR5F1 BAT54 VTT_47
be5,7,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
within 250mils of +V3.3S
D21 VCCD_TVDAC VTT_48 N8
should be placed within
2 VCCGFOLLOW 3
c
1 1 VTT_49 M8
10 edge of MCH A23 P7 200mils of edge
58 +V2.5S_CRTDAC VCC_HV0 VTT_50
B23 VCC_HV1 VTT_51 N7
FB5E1 B25 M7
+V1.5S_QTVDAC VCC_HV2 VTT_52
VTT_53 R6
s
180ohm@100MHz H19 P6
+V1.5S_AUX 9,58 VCCD_QTVDAC VTT_54
VTT_55 M6
AK31 A6 VTTLF_CAP3
VCCAUX0 VTT_56
-
AF31 R5 C4T10
VCCAUX1 VTT_57
NOTE: CAPS AE31 VCCAUX2 VTT_58 P5
AC31 N5 0.47uF
USED IN VCCAUX3 VTT_59
AL30 VCCAUX4 VTT_60 M5
4,17,27,48,56,58 +V1.5S +V1.5_PCIE AK30 P4
VCCAUX5 VTT_61
p
7,58 +V1.5S_PCIE AJ30 N4
L5E1 should be on VCCAUX6 VTT_62
AH30 VCCAUX7 VTT_63 M4
PCIE_LR5E2 AG30 R3
0.002 1%
top layer VCCAUX8 VTT_64
AF30 VCCAUX9 VTT_65 P3
C5E2 C5D5 C5E1 91nH 20% AE30 N3
220uF VCCAUX10 VTT_66
o
AD30 VCCAUX11 VTT_67 M3
10uF 10uF AC30 R2
VCCAUX12 VTT_68
AG29 VCCAUX13 VTT_69 P2
B B
t
NOTE: 10uF CAPS AF29 VCCAUX14 VTT_70 M2
4,17,27,48,56,58 +V1.5S AE29 D2 VTTLF_CAP2
+V1.5S_3GPLL USED IN VCCAUX15 VTT_71 VTTLF_CAP1
AD29 VCCAUX16 VTT_72 AB1
L5D1 R6D8
+V1.5_3GPLL AC29 VCCAUX17 VTT_73 R1
R5D1 0.5 1% 3GPLL_R_L1 23GPLL_FB_L AG28 P1 C4T3 C4T9
should be placed VCCAUX18 VTT_74
p
1uH 20% 0.002 1% AF28 N1 NOTE: CAPS USED IN
VCCAUX19 VTT_75
in cavity AE28 M1 0.22uF
VCCAUX20 VTT_76 +V1.5_TVDAC and
AH22 0.47uF
VCCAUX21
AJ21 VCCAUX22 +V1.5_QTVDAC should be
AH21 VCCAUX23 within 250mils of edge
la
AJ20 VCCAUX24
3,4,6,9,14,17,30,37,45,48,53,56,58 +V1.05S AH20 VCCAUX25 4,17,27,48,56,58 +V1.5S
4,17,27,48,56,58 +V1.5S AH19 58 +V1.5S_TVDAC
VCCAUX26
+V1.5S_AUX 9,58 P19
R6D6 VCCAUX27 TVDAC_FB
C4T2 C4T4 C4E2 C4E1 P16 1 3 R5F3
VCCAUX28
.
AH15 C5F3 0.002 1%
0.22uF VCCAUX29
C5R5 0.002 1% 4.7uF 2.2uF 270uF P15 C5E4 0.1uF
VCCAUX30
20% 22nF
2
AH14 VCCAUX31
0.1uF PLACE IN AG14 VCCAUX32
5,17,18,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S PLACE ON AF14
CAVITY AE14
VCCAUX33 +V1.5S_QTVDAC
THE EDGE Y14
VCCAUX34 FB5F1
w
+V3.3S 5,7,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 VCCAUX35 QTVDAC_FB
AF13 VCCAUX36 1 3
R4U3 AE13
10K VCCAUX37
AF12 C5E5 180ohm@100MHz
PM_SLP_S3_SHDN2
VCCAUX38
5,17,18,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S 22nF C5F4
2
AE12 VCCAUX39
AD12 0.1uF
VCCAUX40
U4F1 SC1563 +V3.3S_TVDAC_LDO
C5F7 C5T16 5
w
IN CALISTOGA_1p0
10uF 0.1uF OUT 4
C4F5 1
1.0uF SHDN
A GND ADJ R4U1 C4F7 C4F4 Capell Valley Intel Confidential A
+V3.3S_TVDAC_LDO 17.8K
2 3 1%
4,17,27,48,56,58 +V1.5S
22uF 0.1uF Title
w
CR4F1 TVDAC_ADJ2 CALISTOGA (5 OF 6)
3
V1_5SFOLLOW3 1 R4U4
1
BAT54 Q4U1 100

R4F3 BSS138 R4U2
47,56 +V3.3S_TVDAC 10
32,35,47,48,49,55,56 PM_SLP_S3# 1
NO_STUFF 10K Size Document Number Rev
1%
A D15378 1.501
2
R4F2 0.002 1%
5 4 3 2 1
5 4 3 2 1
U5E1I U5E1J
m
AC41 VSS_0 AK34 AT23 VSS_180 VSS_273 J11
VSS_97
AA41 VSS_1 AG34 AN23 VSS_181 VSS_274 D11
VSS_98
W41 VSS_2 VSS_99 AF34 AM23 VSS_182 VSS_275 B11
T41 VSS_3 VSS_100 AE34 AH23 VSS_183 VSS_276 AV10
P41 VSS_4 VSS_101 AC34 AC23 VSS_184 AP10
VSS_277
o
M41 VSS_5 VSS_102 C34 W23 VSS_185 AL10
VSS_278
J41 VSS_6 VSS_103 AW33 K23 VSS_186 AJ10
VSS_279
F41 VSS_7 VSS_104 AV33 J23 VSS_187 AG10
VSS_280
AV40 VSS_8 VSS_105 AR33 F23 VSS_188 AC10
VSS_281
c
AP40 VSS_9 VSS_106 AE33 C23 VSS_189 W10
VSS_282
AN40 VSS_10 AB33 AA22 VSS_190 U10
D AK40
VSS_107
Y33 K22
VSS_283
BA9 D
.
VSS_11 VSS_108 VSS_191 VSS_284
AJ40 VSS_12 VSS_109 V33 G22 VSS_192 VSS_285 AW9
AH40 VSS_13 T33 F22 VSS_193 AR9
VSS_110 VSS_286
AG40 VSS_14 R33 E22 VSS_194 AH9
VSS_111 VSS_287
AF40 VSS_15 M33 D22 VSS_195 AB9
VSS_112 VSS_288
s
AE40 VSS_16 H33 A22 VSS_196 Y9
VSS_113 VSS_289
B40 VSS_17 G33 BA21 VSS_197 R9
VSS_114 VSS_290
AY39 VSS_18 F33 AV21 VSS_198 G9
VSS_115 VSS_291
AW39 VSS_19 D33 AR21 VSS_199 E9
VSS_116 VSS_292
it c
AV39 VSS_20 B33 AN21 VSS_200 A9
VSS_117 VSS_293
AR39 VSS_21 AH32 AL21 VSS_201 AG8
VSS_118 VSS_294
AN39 VSS_22 AG32 AB21 VSS_202 AD8
VSS_119 VSS_295
AJ39 VSS_23 AF32 Y21 VSS_203 AA8
VSS_120 VSS_296
AC39 VSS_24 AE32 P21 VSS_204 U8
VSS_121 VSS_297
AB39 VSS_25 AC32 K21 VSS_205 K8
VSS_122 VSS_298
AA39 VSS_26 AB32 J21 VSS_206 C8
VSS_123 VSS_299
Y39 VSS_27 G32 H21 VSS_207 BA7
VSS_124 VSS_300
W39 VSS_28 B32 C21 VSS_208 AV7
VSS_125 VSS_301
a
V39 VSS_29 AY31 AW20 VSS_209 AP7
VSS_126 VSS_302
T39 AV31 AR20 AL7
R39
P39
VSS_30
VSS_31
VSS_32
VSS_127
VSS_128
VSS_129
AN31
AJ31
AM20
AA20
VSS_210
VSS_211
VSS_212
VSS VSS_303
VSS_304
VSS_305
AJ7
AH7
N39 AG31 K20 AF7
M39
L39
VSS_33
VSS_34
VSS_35
VSS VSS_130
VSS_131
VSS_132
AB31
Y31
B20
A20
VSS_213
VSS_214
VSS_215
VSS_306
VSS_307
VSS_308
AC7
R7
J39 AB30 AN19 G7
m
H39 VSS_37 E30 AC19 VSS_217 D7
VSS_134 VSS_310
G39 VSS_38 AT29 W19 VSS_218 AG6
VSS_135 VSS_311
F39 VSS_39 AN29 K19 VSS_219 AD6
C VSS_136 VSS_312 C
D39 VSS_40 AB29 G19 VSS_220 AB6
VSS_137 VSS_313
e
AT38 VSS_41 T29 C19 VSS_221 Y6
VSS_138 VSS_314
AM38 VSS_42 N29 AH18 VSS_222 U6
VSS_139 VSS_315
AH38 VSS_43 K29 P18 VSS_223 N6
VSS_140 VSS_316
AG38 VSS_44 G29 H18 VSS_224 K6
VSS_141 VSS_317
AF38 VSS_45 E29 D18 VSS_225 H6
VSS_142 VSS_318
h
AE38 VSS_46 C29 A18 VSS_226 B6
VSS_143 VSS_319
C38 VSS_47 B29 AY17 VSS_227 AV5
VSS_144 VSS_320
AK37 VSS_48 A29 AR17 VSS_228 AF5
VSS_145 VSS_321
AH37 VSS_49 BA28 AP17 VSS_229 AD5
VSS_146 VSS_322
c
AB37 VSS_50 AW28 AM17 VSS_230 AY4
VSS_147 VSS_323
AA37 VSS_51 AU28 AK17 VSS_231 AR4
VSS_148 VSS_324
Y37 VSS_52 AP28 AV16 VSS_232 AP4
VSS_149 VSS_325
W37 VSS_53 AM28 AN16 VSS_233 AL4
VSS_150 VSS_326
V37 AD28 AL16 AJ4
s
T37 VSS_55 AC28 J16 VSS_235 Y4
VSS_152 VSS_328
R37 VSS_56 W28 F16 VSS_236 U4
VSS_153 VSS_329
P37 J28 C16 R4
-
N37 VSS_58 E28 AN15 VSS_238 J4
VSS_155 VSS_331
M37 VSS_59 AP27 AM15 VSS_239 F4
VSS_156 VSS_332
L37 VSS_60 AM27 AK15 VSS_240 C4
VSS_157 VSS_333
J37 VSS_61 AK27 N15 VSS_241 AY3
VSS_158 VSS_334
p
H37 VSS_62 J27 M15 VSS_242 AW3
VSS_159 VSS_335
G37 VSS_63 G27 L15 VSS_243 AV3
VSS_160 VSS_336
F37 VSS_64 F27 B15 VSS_244 AL3
VSS_161 VSS_337
D37 VSS_65 C27 A15 VSS_245 AH3
VSS_162 VSS_338
AY36 VSS_66 B27 BA14 VSS_246 AG3
VSS_163 VSS_339
o
AW36 VSS_67 AN26 AT14 VSS_247 AF3
VSS_164 VSS_340
AN36 VSS_68 M26 AK14 VSS_248 AD3
VSS_165 VSS_341
B B
t
AH36 VSS_69 K26 AD14 VSS_249 AC3
VSS_166 VSS_342
AG36 VSS_70 F26 AA14 VSS_250 AA3
VSS_167 VSS_343
AF36 VSS_71 D26 U14 VSS_251 G3
VSS_168 VSS_344
AE36 VSS_72 AK25 K14 VSS_252 AT2
VSS_169 VSS_345
AC36 VSS_73 P25 H14 VSS_253 AR2
VSS_170 VSS_346
p
C36 VSS_74 K25 E14 VSS_254 AP2
VSS_171 VSS_347
B36 VSS_75 H25 AV13 VSS_255 AK2
VSS_172 VSS_348
BA35 VSS_76 E25 AR13 VSS_256 AJ2
VSS_173 VSS_349
AV35 VSS_77 D25 AN13 VSS_257 AD2
VSS_174 VSS_350
AR35 VSS_78 A25 AM13 VSS_258 AB2
VSS_175 VSS_351
la
AH35 VSS_79 BA24 AL13 VSS_259 Y2
VSS_176 VSS_352
AB35 VSS_80 AU24 AG13 VSS_260 U2
VSS_177 VSS_353
AA35 VSS_81 AL24 P13 VSS_261 T2
VSS_178 VSS_354
Y35 VSS_82 AW23 F13 VSS_262 N2
VSS_179 VSS_355
.
W35 VSS_83 D13 VSS_263 J2
VSS_356
V35 VSS_84 B13 VSS_264 H2
VSS_357
T35 VSS_85 AY12 VSS_265 F2
VSS_358
R35 VSS_86 AC12 VSS_266 C2
VSS_359
P35 VSS_87 K12 VSS_267 AL1
VSS_360
N35 H12 VSS_268
VSS_88
w
M35 E12 VSS_269
VSS_89
L35 AD11 VSS_270
VSS_90
J35 AA11 VSS_271
VSS_91
H35 Y11 VSS_272
VSS_92
G35
VSS_93
F35 CALISTOGA_1p0
VSS_94
D35
w
VSS_95
AN34
VSS_96
A A
CALISTOGA_1p0
Title
w
CALISTOGA (6 OF 6)

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
m
Layout Note:
Location of all MCH_CFG strap resistors
7 MCH_CFG_5
o
needs to be close to trace to minimize stub
5,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
c
D MCH_CFG_5 Low = DMIx2 R1D3 D
2.2K
.
High = DMIx4
NO_STUFF MCH_CFG_18 R6F1
7 MCH_CFG_12 Low = 1.05V
(VCC 1K
Select) High = 1.5V NO_STUFF
7 MCH_CFG_13
s
R1E12
2.2K 7 MCH_CFG_18
it c
NO_STUFF
7 MCH_CFG_6 R1E11
NO_STUFF
2.2K
LOW = Moby Dick 5,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

MCH_CFG_6
HIGH = Calistoga R1D4 +V3.3S
(DDR) 2.2K
a
NO_STUFF
MCH_CFG_19 Low = Normal
(DMI LANE REVERSAL) High = LANES REVERSED
R5U3
1K
NO_STUFF
m
7 MCH_CFG_7 7 MCH_CFG_16 7 MCH_CFG_19
C C
e
Low = Dynamic ODT
MCH_CFG_7 Low = RSVD R1E3 MCH_CFG_16 Disabled R1E1
(CPU Strap) High = Mobile CPU 2.2K (FSB Dynamic 2.2K
h
High = Dynamic ODT
NO_STUFF ODT) NO_STUFF
Enabled
5,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
c
MCH_CFG_20 Low = Only SDVO or PCIE x1 is
(PCIe Backward operational (defaults)
Interpoerability High = SDVO and PCIE x1 are operating
R5F1
mode) simultaneously via the PEG port
s
1K
NO_STUFF
-
7 MCH_CFG_9
7,13 MCH_CFG_20
p
MCH_CFG_9 Low = Reverse Lane
PCIE Graphics High = Normal R1E8
2.2K
Lane operation
o
B B
pt
7 MCH_CFG_10
la
MCH_CFG_10
HOST PLL VCO Low = RESERVED R1E2
High = MOBILITY 2.2K
SELECT
.
NO_STUFF
w
7 MCH_CFG_11
w
MHC_CFG_11 Low = Reserved
A R1D5 A
PSB 4x CLK
ENABLE
High = Calistoga
2.2K Capell Valley Intel Confidential
NO_STUFF
Title
w
CALISTOGA STRAPPING

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
o m
+V12S_PEG
+V12S_PEG +V3.3S_PEG
c
+V3.3S_PEG J6C1
D B1 +12V1 PRSNT1# A1 D
.
B2 +12V2 +12V4 A2
B3 +12V3 +12V5 A3
B4 GND1 GND6 A4
14,35 SMB_CLK_S4 B5 SMCLK JTAG2 A5
B6 A6 R6C4 0
14,35 SMB_DATA_S4 JTAG3 PLT_GATED_RST# 32,33,36
s
SMDAT NO_STUFF
B7 GND2 JTAG4 A7
14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A B8 A8
+3.3V1 JTAG5
B9 JTAG1 +3.3V2 A9
B10 3.3VAUX +3.3V3 A10
B11 A11 PEG_SLT_RST# R6C5 0
it c
16,28,33 PCIE_WAKE# WAKE# PWRGD PLT_RST# 7,15,24,28,32,41,42,57
Key
B12 RSVD2 GND7 A12
7 PEG_TXP[15:0] B13 GND3 REFCLK+ A13 CLK_PCIE_PEG 30
PEG_TXP15 C6C6 0.1uF PEG_C_TXP15 B14 A14
7 PEG_TXN[15:0] PEG_TXN15 PEG_C_TXN15 HSOP_0 REFCLK- CLK_PCIE_PEG# 30
C6C7 B15 A15
HSON_0 GND8 PEG_RXP15 PEG_RXP[15:0] 7
0.1uF B16 A16
GND4 HSIP_0 PEG_RXN15 PEG_RXN[15:0] 7
7 SDVO_CTRLCLK B17 PRSNT2# HSIN_0 A17
B18 GND5 GND9 A18
PEG_TXP14 C6C8 0.1uF PEG_C_TXP14
a
B19 HSOP_1 RSVD5 A19
PEG_TXN14 PEG_C_TXN14 B20 A20
C6C9 0.1uF HSON_1 GND16 PEG_RXP14
B21 GND10 HSIP_1 A21
B22 A22 PEG_RXN14
PEG_TXP13 C6C10 0.1uF PEG_C_TXP13 GND11 HSIN_1
B23 HSOP_2 GND17 A23
PEG_TXN13 PEG_C_TXN13 B24 A24
C6C11 0.1uF HSON_2 GND18 PEG_RXP13
B26 A26 PEG_RXN13
PEG_TXP12 PEG_C_TXP12 GND13 HSIN_2
m
C6C12 0.1uF B27 A27
PEG_TXN12 PEG_C_TXN12 HSOP_3 GND19
B28 HSON_3 GND20 A28
C6C13 0.1uF B29 A29 PEG_RXP12
GND14 HSIP_3 PEG_RXN12
B30 RSVD3 HSIN_3 A30
C 7 SDVO_CTRLDATA B31 PRSNT2#1 GND21 A31 C
e
B32 GND15 RSVD6 A32
PEG_TXP11 C6D3 0.1uF PEG_C_TXP11 B33 A33
PEG_TXN11 PEG_C_TXN11 HSOP_4 RSVD7
C6D4 0.1uF B35 A35 PEG_RXP11
B36 GND23 HSIN_4 A36
PEG_TXP10 C6D6 0.1uF PEG_C_TXP10 B37 A37 55,56 +VBAT_S4
h
C6D7 0.1uF B39 A39 PEG_RXP10 18,19,27,55,56 +VBATS
c
C6D9 0.1uF B43 A43 PEG_RXP9 R6N6 R6N7
GND26 HSIP_6 PEG_RXN9 0.002 0.002
PEG_TXP8 C6D10 0.1uF PEG_C_TXP8 B45 A45 +V12S_PEG 1% 1%
PEG_TXN8 PEG_C_TXN8 HSOP_7 GND35 NO_STUFF
-s
7,12 MCH_CFG_20 B48 PRSNT2#2 HSIN_7 A48
B49 GND29 GND37 A49
PEG_TXP7 C6D13 0.1uF PEG_C_TXP7 B50 A50 C6B11 C6B7 C6B4 C6B6 C6B8 C6N8
PEG_TXN7 PEG_C_TXN7 HSOP_8 RSVD8 22UF 22UF 22UF 22UF 0.1uF 0.1uF
C6D14 0.1uF B52 A52 PEG_RXP7 10% 10%
p
PEG_TXP5 C6E1 0.1uF PEG_C_TXP5 B58 A58
PEG_TXN5 PEG_C_TXN5 HSOP_10 GND57 14,15,17,25,27,32,33,34,35,36,38,45,46,55,56 +V3.3
C6E2 0.1uF PEG_RXP5 5,7,10,12,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
o
B61 A61 PEG_RXN5
PEG_TXP4 C6E3 0.1uF PEG_C_TXP4 GND43 HSIN_10
B62 HSOP_11 GND59 A62
B B
t
PEG_TXN4 PEG_C_TXN4 B63 A63 For D3 HOT/ D3 ON: R6C2 R6C3
C6E4 0.1uF HSON_11 GND60 PEG_RXP4 0.002 0.002
B65 A65 PEG_RXN4 Stuff R6N7, R6C3, and +V3.3S_PEG 1% 1%
PEG_TXP3 C6E5 0.1uF PEG_C_TXP3 GND45 HSIN_11 NO_STUFF
PEG_TXN3 PEG_C_TXN3
B66 HSOP_12 GND61 A66 R6C4, unstuff R6N6,
PEG_RXP3 R6C2 and R6C5.
p
C6E6 0.1uF B68 A68
GND46 HSIP_12 PEG_RXN3 + C6C5 C6C4 C6C3
PEG_TXP2 C6E7 0.1uF PEG_C_TXP2 B70 A70 100uF 0.1uF 0.1uF
C6E8 0.1uF B72 A72 PEG_RXP2
la
PEG_TXP1 C6E10 0.1uF PEG_C_TXP1 B74 A74
.
PEG_TXP0 C6E12 0.1uF PEG_C_TXP0 B78 A78 14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
B81 PRSNT2#3 HSIN_15 A81
B82 A82 C6C2 C6C1
RSVD4 GND69 0.1uF
PCIE_X16 22uF
w
Layout Note: place
AC coupling caps
close to GMCH. All
AC coupling caps are
w
0603 size.
A A
Title
w
PCIE GRAPHICS

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
+V3.3A 13,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57
CR6H1 17 +V3.3A_RTC
m
1 3
C6H7
BAT54 1uF
RTC Circuitry
o
CR6H2 R6H11 20K
BAT_D 1 3
C6H5 J6H1
c
BAT54 1uF
R6H9
D 1K R6H10 D
.
1M C8V1 10pF
1
BAT Y8G1 R8V5
32.768KHZ 10M
s
1
Cap values depend on Xtal
4
U7G1A
LPC_AD0 LPC_AD[3:0] 24,32,35,41,42
BT5H1 CMOS Settings J6H1 RTC_X1 AB1 AA6
Battery_Holder C8V2 10pF RTC_X2 RTXC1 LAD0 LPC_AD1 +V1.05S 3,4,6,9,10,17,30,37,45,48,53,56,58
AB2 AB5
it c
Clear CMOS Shunt RTCX2 LAD1
LPC
LPC_AD2
RTC
LAD2 AC4
Keep CMOS Open RTC_RST# AA3 Y6 LPC_AD3
RTCRST# LAD3
SM_INTRUDER# R6V11 R5V9
3
Y5 INTRUDER# LDRQ0# AC3 ICH_DRQ#0 42

13,15,17,25,27,32,33,34,35,36,38,45,46,55,56 +V3.3 ICH_INTVRMEN W4 AA5 56 56
U8F3 INTVRMEN LDRQ1#/GPIO23 ICH_DRQ#1 42
8 1 EEP_CS W1 AB3
TP_EEP_DC VCC CS EE_CS LFRAME# LPC_FRAME# 24,32,35,41,42
C8U1 7 2 EEP_SK Y1 NO_STUFF NO_STUFF 3,4,6,9,10,17,30,37,45,48,53,56,58
TP_EEP_ORG DC SK EEP_DOUT EE_SHCLK +V1.05S
6 ORG DI 3 Y2 EE_DOUT A20GATE AE22 H_A20GATE 32,35
0.1uF EEP_DIN
a
5 GND DO 4 W3 EE_DIN A20M# AH28 H_A20M# 3
V3 AG27 TP_H_CPUSLP#
33 LAN_JCLK LAN_CLK CPUSLP#
AT88SC153 R5G5 0 R6V17
H_DPRSTP# 3,35
LAN
CPU
NO_STUFF U3 AF24 H_DPRSTP#_R 56
33 LAN_RSTSYNC LAN_RSTSYNC TP1/DPRSTP# H_DPSLP#_R
AH25 R6V13 0
TP2/DPSLP# H_DPSLP# 3,35
33 LAN_RXD0 U5 LAN_RXD0
33 LAN_RXD1 V4 LAN_RXD1 FERR# AG26 H_FERR# 3
m
33 LAN_RXD2 T5 LAN_RXD2
GPIO49/CPUPWRGD AG24 H_PWRGD 3,35
33 LAN_TXD0 U7 LAN_TXD0
33 LAN_TXD1 V6 LAN_TXD1
C 33 LAN_TXD2 V7 LAN_TXD2 IGNNE# AG22 H_IGNNE# 3 C
e
INIT3_3V# AG21 FWH_INIT# 24
27 ACZ_BITCLK U1 ACZ_BIT_CLK INIT# AF22 H_INIT# 3
AC-97/AZALIA
+V3.3S R6 AF25
27 ACZ_SYNC ACZ_SYNC INTR H_INTR 3
5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
+V3.3S R5 AG23 +V1.05S 3,4,6,9,10,17,30,37,45,48,53,56,58
27 ACZ_RST# ACZ_RST# RCIN# H_RCIN# 16,32,35
5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
h
27 ACZ_SDATAIN0 T2 ACZ_SDIN0 NMI AH24 H_NMI 3,35
R7H11 T3 AF23 H_SMI#_R R6V16 R6V14
27 ACZ_SDATAIN1 ACZ_SDIN1 SMI# H_SMI# 3,35,58 56
10K T1 0
27 ACZ_SDATAIN2 ACZ_SDIN2
STPCLK# AH22 H_STPCLK# 3
ACZ_SDATAOUT
c
27 ACZ_SDATAOUT T4 ACZ_SDOUT
AF26 H_THERMTRIP_R R6V12 24.9 1%
ICH_SATA_LED# THERMTRIP# PM_THRMTRIP# 3,7
AF18 SATALED#
IDE_PDD[15:0] 39 Layout note: R6V12 needs to placed
R7J5 C7W2 3900pF SATA_RXN0_C AF3 AB15 IDE_PDD0
43 SATA_RXN0 SATA0RXN DD0 within 2" of ICH7, R6V14 must be placed
-s
330 C7W1 3900pF SATA_RXP0_C AE3 AE14 IDE_PDD1
43 SATA_RXP0 SATA0RXP DD1
C7W3 3900pF SATA_TXN0_C AG2 AG13 IDE_PDD2 within 2" of R6V12 w/o stub.
43 SATA_TXN0 C7W4 SATA_TXP0_C SATA0TXN DD2 IDE_PDD3
AH2 SATA0TXP DD3 AF13
LED_R C7J12 43 SATA_TXP0 3900pF IDE_PDD4
DD4 AD14
C7H5 3900pF SATA_RXN2_C AF7 AC13 IDE_PDD5
44 SATA_RXN2 SATA2RXN DD5
2
0.1uF R7J3 C7H6 3900pF SATA_RXP2_C AE7 AD12 IDE_PDD6

10K 44 SATA_RXP2 SATA_TXN2_C SATA2RXP DD6 IDE_PDD7
CR7J1 C7H4 3900pF AG6 AC12
44 SATA_TXN2 SATA_TXP2_C SATA2TXN DD7 IDE_PDD8
C7H3 3900pF AH6 AE12
GREEN 44 SATA_TXP2 SATA2TXP DD8
5
IDE_PDD9
p
U7J1 AF12
DD9
SATA
1 AF1 AB13 IDE_PDD10
31 CLK_PCIE_SATA# SATA_CLKN DD10 IDE_PDD11
74AHC1G08 Distance between the ICH-7 M
1
54 ATA_LED# 4 31 CLK_PCIE_SATA AE1 SATA_CLKP DD11 AC14

2 AF14 IDE_PDD12
IDE_PDACTIVE# 39 and cap on the "P" signal should SATA_RBIAS_PN DD12 IDE_PDD13
AH10 SATARBIASN DD13 AH13
be identical distance between IDE_PDD14
o
AG10 SATARBIASP DD14 AH14
IDE_PDD15
3
the ICH-7 M and cap on the "N" DD15 AC15

B signal for same pair. IDE_PDA[2:0] 39 B
t
AF15 AH17 IDE_PDA0
39 IDE_PDIOR#
AH15
DIOR# IDE DA0
AE17 IDE_PDA1
39 IDE_PDIOW# DIOW# DA1 IDE_PDA2
39 IDE_PDDACK# AF16 DDACK# DA2 AF17
39 INT_IRQ14 AH16 IDEIRQ
R7H1 AG16 AE16
39 IDE_PDIORDY IORDY DCS1# IDE_PDCS1# 39
p
Short pins AH10 and 24.9 AE15 AD16
39 IDE_PDDREQ DDREQ DCS3# IDE_PDCS3# 39
17 +V3.3A_RTC 1%
AG10 at the package. ICH7M REV 1.02 EDS
Place R7H1 within 500
R7V1 mils of ICH7 ball
la
332K
1%
ICH7 internal VR enable strap
ICH_INTVRMEN
INTVRMEN R7V1 R7V2
.
+V3.3S 5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
R7V2 Enable (default) 1 STUFF UNSTUFF
0 +V3.3A 13,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57
NO_STUFF Disable 0 UNSTUFF STUFF
R7C23 10K SMB_CLK_S2 R9D1 10K SMB_CLK_A1
R7D2 10K SMB_DATA_S2
w
R6D5 10K SMB_CLK_S3 R9D2 10K SMB_DATA_A1
R6D7 10K SMB_DATA_S3
R9A5 10K SMB_CLK_S4
R9A6 10K SMB_DATA_S4
+V3.3S 5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 13,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
+V3.3S 5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
w
R8G8 +V3.3A 13,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 C7C6
1K U7C4
A NO_STUFF R7P23 10K CL1 0.1uF A
R7P28 10K CL2
1 EXPSCL1
2 EXPSCL2
VCC 20 Capell Valley Intel Confidential
R7R2 10K DA1 18 EXPSDA1 SCL1 5 SMB_CLK_A1 25,26,28
ACZ_SDATAOUT R7P24 10K DA2 Title
w
19 EXPSDA2 SDA1 6 SMB_DATA_A1 25,26,28
RSVD9 15 16,33,58 SMB_CLK 3 SCL0 SCL2 8 SMB_CLK_S2 21,22,23

ICH7-M (1 of 4)
16,33,58 SMB_DATA 4 SDA0 SDA2 9 SMB_DATA_S2 21,22,23
R7U13 R7R6 10K I2C_EN1 7 12
1K R7D11 10K I2C_EN2 11 EN1 SCL3
13
SMB_CLK_S3 30,31
SMB_DATA_S3 30,31
NO_STUFF R7D1 10K I2C_EN3 14 EN2 SDA3
R7R5 10K I2C_EN4 17 EN3
15
A D15378 1.501
EN4 SCL4 SMB_CLK_S4 13,35
10 VSS SDA4 16 SMB_DATA_S4 13,35
EXP. 5-CH-I2C HUB Date: Wednesday, July 20, 2005 Sheet 14 of 60
5 4 3 2 1
5 4 3 2 1
+V3.3S 5,7,10,12,13,14,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
m
C7T4
Layout note: PCIE AC coupling caps
0.1uF U8E2 need to be within 250 mils of the
5
o
1 PLT_RST# driver.
32,33,35 BUF_PLT_RST# 4 74AHC1G08
2 U7G1D
F26 V26
c
33 PCIE_RXN1_LAN PERn1 DMI0RXN DMI_RXN0 7
Direct Media Interface

R8B3 Buffer to reduce F25 V25
33 PCIE_RXP1_LAN PERp1 DMI0RXP DMI_RXP0 7
D 100K C6V1 0.1uF PCIE_TXN1_C D
3
loading on E28 PETn1 DMI0TXN U28 DMI_TXN0 7
33 PCIE_TXN1_LAN
.
PLT_RST# C6U2 0.1uF PCIE_TXP1_C E27 U27
33 PCIE_TXP1_LAN PETp1 DMI0TXP DMI_TXP0 7
28 PCIE_RXN2_SLOT1 H26 PERn2 DMI1RXN Y26

DMI_RXN1 7
28 PCIE_RXP2_SLOT1 H25 PERp2 DMI1RXP Y25 DMI_RXP1 7
C6F7 0.1uF PCIE_TXN2_C G28 W28
DMI1TXN DMI_TXN1 7
s
28 PCIE_TXN2_SLOT1 C6F6 0.1uF PCIE_TXP2_C PETn2
G27 PETp2 DMI1TXP W27 DMI_TXP1 7
28 PCIE_TXP2_SLOT1
PCI-Express
R6V5 0 PCIE_RXN3_R K26 AB26
28 PCIE_RXN3_SLOT2 PCIE_RXP3_R PERn3 DMI2RXN DMI_RXN2 7
R6V4 0 K25 AB25
28 PCIE_RXP3_SLOT2 PERp3 DMI2RXP DMI_RXP2 7
C6V3 0.1uF PCIE_TXN3_C J28 AA28
it c
28 PCIE_TXN3_SLOT2 PETn3 DMI2TXN DMI_TXN2 7
C6V2 0.1uF PCIE_TXP3_C J27 AA27
28 PCIE_TXP3_SLOT2 PETp3 DMI2TXP DMI_TXP2 7
R6V8 0 PCIE_RXN4_R M26 AD25
28 PCIE_RXN4_SLOT0 PCIE_RXP4_R PERn4 DMI3RXN DMI_RXN3 7 +V1.5S_PCIE_ICH 17
R6V6 0 M25 AD24
28 PCIE_RXP4_SLOT0 PCIE_TXN4_C PERp4 DMI3RXP DMI_RXP3 7
+V3.3 13,14,17,25,27,32,33,34,35,36,38,45,46,55,56 C6G5 0.1uF L28 AC28
28 PCIE_TXN4_SLOT0 PCIE_TXP4_C PETn4 DMI3TXN DMI_TXN3 7
C6G3 0.1uF L27 AC27
28 PCIE_TXP4_SLOT0 PETp4 DMI3TXP DMI_TXP3 7
NOTE: R7F3-5 are not needed
PCIE_RXN4_SLOT0 R6G5 0 NO_STUFF PCIE_RXN5_R P26 AE28
when sharing SPI flash with PCIE_RXP4_SLOT0 R6G4 0 NO_STUFF PCIE_RXP5_R PERn5 DMI_CLKN CLK_PCIE_ICH# 30 R7U9
P25 PERp5 DMI_CLKP AE27 CLK_PCIE_ICH 30
ICH7M and Tekoa PCIE_TXN4_SLOT0 C6G1 0.1uF NO_STUFF PCIE_TXN5_C 24.9 Place within 500
a
N28 PETn5
R7F5 R7F4 R7F3 PCIE_TXP4_SLOT0 C6F5 0.1uF NO_STUFF PCIE_TXP5_C N27 C25 1% mils of ICH
10K 10K 10K PETp5 DMI_ZCOMP DMI_IRCOMP_R
DMI_IRCOMP D25
NO_STUFF NO_STUFF NO_STUFF PCIE_RXN3_SLOT2 R6G3 0 NO_STUFF PCIE_RXN6_R T25
PCIE_RXP3_SLOT2 R6G2 0 NO_STUFF PCIE_RXP6_R PERn6
T24 PERp6 USBP0N F1 USB_PN0 40
PCIE_TXN3_SLOT2 C6G7 0.1uF NO_STUFF PCIE_TXN6_C R28 F2
PCIE_TXP3_SLOT2 PCIE_TXP6_C PETn6 USBP0P USB_PP0 40
C6G6 0.1uF NO_STUFF R27 G4
PETp6 USBP1N USB_PN1 40
USBP1P G3 USB_PP1 40
m
33 SPI_SCLK R2 SPI_CLK USBP2N H1 USB_PN2 29
33 SPI_CE# P6 SPI_CS# USBP2P H2 USB_PP2 29
SPI
33 SPI_ARB P1 SPI_ARB USBP3N J4 USB_PN3 40
USBP3P J3 USB_PP3 40
C 33 SPI_SI P5 SPI_MOSI USBP4N K1 USB_PN4 29 C
USB
e
33 SPI_SO P2 SPI_MISO USBP4P K2 USB_PP4 29
USBP5N L4 USB_PN5 40
R7F15 0 D3 L5
40 USB_OC#0 OC0# USBP5P USB_PP5 40
R7F14 0 C4 M1
40 USB_OC#1 OC1# USBP6N USB_PN6 29
R7F13 0 D5 M2
R7F12 0 D4 N4
h
40 USB_OC#3 OC3# USBP7N USB_PN7 40
R7F8 0 E5 N3
R7F9 0 C3
40 USB_OC#5 OC5#/GPIO29
R7F11 0 A2 D2
29 USB_OC#6 OC6#/GPIO30 USBRBIAS#
R7F10 0 B3 D1 USB_RBIAS_PN
40 USB_OC#7 OC7#/GPIO31 USBRBIAS
c
ICH7M REV 1.02 EDS
USB_OC#0_R
R8U5
USB_OC#1_R Place within 500 22.6
USB_OC#2_R
mils of ICH 1%
USB_OC#3_R
-s
USB_OC#4_R
USB_OC#5_R
USB_OC#6_R
USB_OC#7_R
p
PCI_GNT#3 25
o
U7G1B
25,26 PCI_AD[31:0]
PCI_AD0 E18 D7 R8U4 R7U18 - A16 swap override
B AD0 REQ0# PCI_REQ#0 16,26 B
t
PCI_AD1 C18 E7 1K
PCI_AD2 A16
AD1 PCI GNT0#
C16
PCI_GNT#0 26 NO_STUFF by default
AD2 REQ1# PCI_REQ#1 16,26 STUFF for A16 swap override
PCI_AD3 F18 D16 NO_STUFF
AD3 GNT1# PCI_GNT#1 26
PCI_AD4 E16 C17
AD4 REQ2# PCI_REQ#2 16,25
PCI_AD5 A18 D17
AD5 GNT2# PCI_GNT#2 25
p
PCI_AD6 E17 E13
AD6 REQ3# PCI_REQ#3 16,25
PCI_AD7 A17 F13
PCI_AD8 AD7 GNT3#
A15 AD8 REQ4#/GPIO22 A13 FWH_WP# 24,35
PCI_AD9 C14 A14
AD9 GNT4#/GPIO48 FWH_TBL# 24,35
PCI_AD10 E14 C8 R8U3 0
AD10 GPIO1/REQ5# PCI_GNT#5_R PCI_REQ#5 16,26 PCI_GNT#5 26
PCI_AD11
la
D14 AD11 GPIO17/GNT5# D8 PCI_GNT#5_R
PCI_AD12 B12 AD12 GNT5_SPI 29
PCI_AD13 C13 B15
AD13 C/BE0# PCI_C/BE#0 25,26
PCI_AD14 G15 C12 R7F7 R8U2
AD14 C/BE1# PCI_C/BE#1 25,26
PCI_AD15 G13 D12 1K 1K
AD15 C/BE2# PCI_C/BE#2 25,26
.
PCI_AD16 E12 C15
AD16 C/BE3# PCI_C/BE#3 25,26
PCI_AD17 C11 NO_STUFF ICH7 Boot BIOS select
PCI_AD18 AD17
D11 AD18 IRDY# A7 PCI_IRDY# 16,25,26
PCI_AD19 A11 E10
AD19 PAR PCI_PAR 25,26
PCI_AD20 A10 B18 GNT5# GNT4#
AD20 PCIRST# PCI_RST# 25,26,32 STRAP
PCI_AD21 F11 A12 R8U2 R7F7
AD21 DEVSEL# PCI_DEVSEL# 16,25,26
PCI_AD22 F10 C9 PCI_PERR# 16,25,26
w
PCI_AD23 AD22 PERR#
E9 E11 PCI_LOCK# 16,25,26 LPC (default) 11
PCI_AD24 D9
AD23 PLOCK#
B10
UNSTUFF UNSTUFF
AD24 SERR# PCI_SERR# 16,25,26
PCI_AD25 B9 F15
PCI_AD26 AD25 STOP# PCI_STOP# 16,25,26 PCI 10 UNSTUFF STUFF
A8 AD26 TRDY# F14 PCI_TRDY# 16,25,26
PCI_AD27 A6 F16
PCI_AD28 AD27 FRAME# PCI_FRAME# 16,25,26 SPI 01 STUFF UNSTUFF
C7 AD28
PCI_AD29 B6 C26
w
AD29 PLTRST# PLT_RST# 7,13,24,28,32,41,42,57
PCI_AD30 E6 A9
AD30 PCICLK CLK_PCIF_ICH 31
PCI_AD31 D6 B19
AD31 PME# PCI_PME# 25,26,35
A Intel Confidential A
16,25 INT_PIRQA# A3
Interrupt I/F G8 INT_PIRQE# 16,26
Capell Valley
PIRQA# GPIO2/PIRQE#
B4 F7
16,25,26 INT_PIRQB# PIRQB# GPIO3/PIRQF# INT_PIRQF# 16,25,26 Title
w
16,25 INT_PIRQC# C5 PIRQC# GPIO4/PIRQG# F8 INT_PIRQG# 16,25,26
16,25 INT_PIRQD# B5 PIRQD# GPIO5/PIRQH# G7 INT_PIRQH# 16,26 ICH7-M (2 of 4)
TP_ICH_RSVD1 AE5
MISC AE9 TP_ICH_RSVD6
RSVD[1] RSVD[6]
TP_ICH_RSVD2
TP_ICH_RSVD3
AD5 RSVD[2] RSVD[7] AG8 TP_ICH_RSVD7
TP_ICH_RSVD8
AG4 RSVD[3] RSVD[8] AH8
TP_ICH_RSVD4
TP_ICH_RSVD5
AH4 RSVD[4] RSVD[9] F21 RSVD9 14 A D15378 1.501
AD9 RSVD[5] MCH_SYNC# AH20 MCH_ICH_SYNC# 7
ICH7M REV 1.02 EDS
5 4 3 2 1
5 4 3 2 1
ICH7 Pullups RP9C1B 2 7 8.2K
m
5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
+V3.3S 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
RP9D1A 1 8 8.2K
15,25,26 PCI_FRAME#
RP9D1B 2 7 8.2K
R7F16 - No Reboot Strap 15,25,26 PCI_IRDY#
RP9D1C 3 6 8.2K
o
SATA0_R1 15,25,26 PCI_TRDY#
NO_STUFF by default +V3.3S 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 RP9D2A 1 8 8.2K
SATA0_R2 15,25,26 PCI_STOP#
STUFF for No Reboot RP9D2D 4 5 8.2K
15,25,26 PCI_SERR#
RP9D1D 4 5 8.2K
14,33,58 SMB_CLK 15,25,26 PCI_DEVSEL#
U7G1C RP9D2C 3 6 8.2K
14,33,58 SMB_DATA SATA0_R0 15,25,26 PCI_PERR#
R7W2 100 RP9D2B 2 8.2K
c
C22 SMBCLK GPIO21/SATA0GP AF19 15,25,26 PCI_LOCK# 7
SMB
D B22 AH18 R7W5 100 RP9B1A 1 8 8.2K D
SMBDATA GPIO19/SATA1GP 15,26 PCI_REQ#0
SATA
GPIO
R7F16 SMB_LINK_ALERT# A26 AH19 R7W3 100 RP9B3B 2 7 8.2K
LINKALERT# GPIO36/SATA2GP SATA_DET#2 32,44 15,26 PCI_REQ#1
.
1K SMLINK0 B25 AE19 SATA0_R3 R7W6 100 RP9C1D 4 5 8.2K
SMLINK1 SMLINK0 GPIO37/SATA3GP 15,25 PCI_REQ#2
NO_STUFF A25 RP9C1C 3 6 8.2K
SMLINK1 15,25 PCI_REQ#3
AC1 RP9C1A 1 8 8.2K
CLK14 CLK_REF_ICH 31 15,26 PCI_REQ#5
Clocks
A28 B2 RP9B3A 1 8 8.2K
35,42 PM_RI# RI# CLK48 CLK_USB48 30 15,25 INT_PIRQA#
RP9B1D 4 5 8.2K
s
15,25,26 INT_PIRQB#
A19 C20 RP9B2A 1 8 8.2K
27 ACZ_SPKR SPKR SUSCLK SUS_CLK 35,41 15,25 INT_PIRQC#
A27 RP9B1C 3 6 8.2K
32,35,42,57 PM_SUS_STAT# SUS_STAT# SLP_S3#_R 15,25 INT_PIRQD#
A22 B24 R8G7 100 RP9B2B 2 7 8.2K
54 PM_SYSRST# SYS_RST# SLP_S3# SLP_S4#_R PM_SLP_S3#_UNBUF 47 15,26 INT_PIRQE#
R6W3 R6W4 D23 R8G2 100 RP9B2C 3 6 8.2K
SLP_S4# PM_SLP_S4# 26,32,35,46,55,56 15,25,26 INT_PIRQF#
10K 10K RP9B2D 4 8.2K
it c
7 PM_BMBUSY# AB18 GPIO0/BM_BUSY# SLP_S5# F22 PM_SLP_S5# 55 15,25,26 INT_PIRQG# 5
RP9B1B 2 7 8.2K
PM_ICH_PWROK 15,26 INT_PIRQH#
NO_STUFF NO_STUFF B23 AA4 RP9B3D 4 5 8.2K
33 SMB_ALERT# GPIO11/SMBALERT# PWROK 25 PCI_REQ64#
Power MGT
RP9B3C 3 6 8.2K
R7W8 0 PM_STPPCI_ICH# PM_DPRSLPVR_R R7H9 100 25 PCI_ACK64#
30,35 PM_STPPCI# AC20 GPIO18/STPPCI# GPIO16/DPRSLPVR AC22 PM_DPRSLPVR 7,35,51
GPIO
R7W7 0 PM_STPCPU_ICH# AF21 R9W12 8.2K
30,35 PM_STPCPU# GPIO20/STPCPU# 25,26,32,35,42 PM_CLKRUN#
SYS
C21 PM_BATLOW#_R R8F9 0
TP0/BATLOW# PM_BATLOW# 32,35
29 PCIE_SLOT0_CARD_ID#1 A21 GPIO26
C23 13,14,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
PWRBTN# PM_PWRBTN# 32,35
BIOS_REC_R B21 GPIO27
a
E23 R7T6 10K
FWH_MFG_MODE_R GPIO28 35,42 PM_RI#
LAN_RST# C19 PM_LAN_ENABLE 32,34,35
25,26,32,35,42 PM_CLKRUN# AG18 GPIO32/CLKRUN#
R7H13 0 Y4 PM_RSMRST#_R R8G14 100 SMB_LINK_ALERT# R6U2 10K
27 DOCK_AZ_EN# RSMRST# PM_RSMRST# 32,35
AC19 SMLINK0 R6U3 10K
DOCK_AZ_EN#_R GPIO33/AZ_DOCK_EN#
U2 E20 SMLINK1 R6U1 10K
27 DOCK_AZ_RST# GPIO34/AZ_DOCK_RST# GPIO9 IDE_PATADET 35,39
GPIO10 A20 PCIE_SLOT0_CARD_ID#0 29
F20 F19 PATA_PWR_EN#_R
13,28,33 PCIE_WAKE# WAKE# GPIO12
m
AH21 E19 SMC_WAKE_SCI#_R 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
25,32,35,42 INT_SERIRQ SERIRQ GPIO13
5,32,35 PM_THRM# AF20 THRM# GPIO14 R4 PCIE_SLOT1_CARD_ID#1 29
GPIO15 E22 SV_SET_UP
C AD22 R3 R7P22 10K C
31 VR_PWRGD_CK410 VRMPWRGD GPIO24 CRB_SV_DET_R 31 CLK_PCIE_SATA_OE#
R7H12 0 D20
43 SATA_PWR_EN#0 GPIO25
e
AC21 AD21 R9W4 8.2K
SATA_PWR_EN#0_R SMC_RUNTIME_SCI#_R AC18 GPIO6 GPIO35 CLK_PCIE_SATA_OE# 31 5,32,35 PM_THRM#
GPIO7 GPIO GPIO38 AD20 PCIE_SLOT1_CARD_ID#0 29
SMC_EXTSMI#_R E21 AE20 R7V3 10K
GPIO8 GPIO39 SATA_PWR_EN#2 44 14,32,35 H_RCIN#
ICH7M REV 1.02 EDS R7T8 10K
25,32,35,42 INT_SERIRQ
h
R8G11 10K
32,35,48 ALL_SYS_PWRGD
+V3.3S 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 R8G12 10K
32,35 PM_RSMRST#
c
R8H3
10K R8G5 0 13,14,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
35,39 PATA_PWR_EN#
s
PATA_PWR_EN#_R
R7N1 2.2K
14,33,58 SMB_CLK
Default is 1-X BIOS_REC R8H2 0 BIOS_REC_R
for BIOS recovery 1-2 R7N2 2.2K
14,33,58 SMB_DATA
-
J8H1
R9E1 1K
13,28,33 PCIE_WAKE#
p
13,14,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
R8B4 10K
33 SMB_ALERT#
+V3.3S 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
J2J10
o
1
2 CRB_SV_DET R8V4 10K CRB_SV_DET_R
B 3 B
t
SMC_RUNTIME_SCI#_R
SMC_RUNTIME_SCI#_R
CON3_HDR R7W4 0
SMC_RUNTIME_SCI# 32,35
13,14,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A SMC_EXTSMI#_R

SMC_EXTSMI#_R
p
R8V6 0
SMC_EXTSMI# 32,35,42,57
+V3.3A 13,14,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 R8F11 SMC_WAKE_SCI#_R

SMC_WAKE_SCI#_R
8.2K R8V2 0
SMC_WAKE_SCI# 32,35
la
PM_BATLOW#_R
R9Y1
10K
.
J9J8
2
1 FWH_MFG_MODE R9Y3 0 FWH_MFG_MODE_R
NO_STUFF
w
+V3.3S 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
w
+V3.3S 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
A A
R3P1 Capell Valley Intel Confidential
2K
1%
w
U8C1 Title
5
PM_ICH_PWROK
1 ALL_SYS_PWRGD 32,35,48 ICH7-M (3 of 4)
4 74AHC1G08
2 DELAY_VR_PWRGOOD 7
R8C8 Size Document Number Rev
10K
1.501
3
A D15378

5 4 3 2 1
5 4 3 2 1
+V5S 5,10,18,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56 Layout Note:

+V3.3S 5,7,10,12,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 U7G1F Place at MCH edge +V1.05S 3,4,6,9,10,14,30,37,45,48,53,56,58
VCC5REF G10 L11
m
V5REF[1] Vcc1_05[1]
Vcc1_05[2] L12
+V5A 29,40,46,47,48,49,54,55,57 AD17 L14
+V3.3A 13,14,16,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 V5REF[2] Vcc1_05[3] C7V9 C7V10
1 Vcc1_05[4] L16
1 V5REF_SUS F6 L17 0.1uF 1uF C6V4
R7F6 CR7F1 V5REF_Sus Vcc1_05[5] 10% 10V 20% 270uF
Vcc1_05[6] L18 20%
o
100 BAT54 R8U6 CR8U1 AA22 M11 SMC0402
10 BAT54 Vcc1_5_B[1] Vcc1_05[7]
AA23 Vcc1_5_B[2] Vcc1_05[8] M18
CORE
AB22 Vcc1_5_B[3] Vcc1_05[9] P11
3
AB23 Vcc1_5_B[4] Vcc1_05[10] P18
3
AC23 T11
c
C7V15 Vcc1_5_B[5] Vcc1_05[11] Layout Note:
AC24 Vcc1_5_B[6] Vcc1_05[12] T18
D 0.1uF C7V2 AC25 Vcc1_5_B[7] Vcc1_05[13] U11 Place on D
.
10% 10V 0.1uF AC26 U18 secondary
SMC0402 10% 10V Vcc1_5_B[8] Vcc1_05[14]
AD26 Vcc1_5_B[9] Vcc1_05[15] V11 side under
SMC0402 AD27 V12
Vcc1_5_B[10] Vcc1_05[16] MCH
AD28 Vcc1_5_B[11] Vcc1_05[17] V14
Layout note: C7V15 needs be placed D26 V16
Vcc1_05[18]
s
Layout note: C7V2 needs be placed Vcc1_5_B[12]
within 100mils of pin AD17 of ICH7 D27 Vcc1_5_B[13] Vcc1_05[19] V17
within 100mils of pin F6 of ICH7 on the D28 V18 13,14,15,25,27,32,33,34,35,36,38,45,46,55,56 +V3.3
on the bottom side or 140 mils on
bottom side or 140 mils on the top E24
Vcc1_5_B[14] VCC PAUX Vcc1_05[20]
the top Vcc1_5_B[15]
E25 Vcc1_5_B[16] VccSus3_3/VccLAN3_3[1] V5
E26 V1 +V3.3S/1.5S_AZ_IO 27
it c
Vcc1_5_B[17] VccSus3_3/VccLAN3_3[2] C7V5
F23 Vcc1_5_B[18] VccSus3_3/VccLAN3_3[3] W2 Place within 100
4,10,27,48,56,58 +V1.5S F24 W7 mils of ICH on 0.1uF
15 +V1.5S_PCIE_ICH Vcc1_5_B[19] VccSus3_3/VccLAN3_3[4] +V3.3A/1.5A_AZ_IO 27 C7V6 10% 10V
G22 Vcc1_5_B[20] the bottom side
G23 U6 0.1uF SMC0402
FB6G1 Vcc1_5_B[21] Vcc3_3/VccHDA 10% 10V or 140 mils on
H22 Vcc1_5_B[22]
H23 R7 SMC0402 the top near pin
100ohm@100MHz C6F4 C6G10 C6G8 Vcc1_5_B[23] VccSus3_3/VccSusHDA
J22 Vcc1_5_B[24]
C6G9 0.1uF 0.1uF 0.1uF J23 AE23 3,4,6,9,10,14,30,37,45,48,53,56,58 +V1.05S
220uF 10% 10V 10% 10V 10% 10V Vcc1_5_B[25] V_CPU_IO[1]
Layout note: Place above K22 Vcc1_5_B[26] V_CPU_IO[2] AE26
4V SMC0402 SMC0402 SMC0402
a
K23 AH26
VCCA3GP
Caps within 100 mils of 20% Vcc1_5_B[27] V_CPU_IO[3] 5,7,10,12,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
L22 Vcc1_5_B[28]
ICH on the bottom side L23 AA7 C7V18 C7V16 C7V21
Vcc1_5_B[29] Vcc3_3[3] +V3.3S 0.1uF 0.1uF 4.7uF
or 140 mils on the top M22 Vcc1_5_B[30] Vcc3_3[4] AB12
near D28, T28, AD28 M23 AB20 10% 10V 10% 10V 10% 10V
Vcc1_5_B[31] Vcc3_3[5] SMC0402 SMC0402 SMC1206
N22 Vcc1_5_B[32] Vcc3_3[6] AC16
+V1.5S 4,10,27,48,56,58 N23 AD13 Place within 100 mils of
Vcc1_5_B[33] Vcc3_3[7]
IDE
5,7,10,12,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S P22 AD18 ICH7 on the bottom side C7V12
Vcc1_5_B[34] Vcc3_3[8]
m
L6H1 1uH P23 AG12 or 140 mils on the top 0.1uF 5,7,10,12,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
R6H3 1 GPLL_R GPLL_R_L Vcc1_5_B[35] Vcc3_3[9] 10% 10V +V3.3S
1 2 R22 Vcc1_5_B[36] Vcc3_3[10] AG15 near pin
R23 AG19 SMC0402
Place within 100 C6H1 C7H2 C6U1 Vcc1_5_B[37] Vcc3_3[11]
R24 Vcc1_5_B[38]
C mils of ICH on the 0.01UF 10uF 0.1uF R25 Vcc1_5_B[39] Vcc3_3[12] A5 C
10% 50V 6.3V 10% 10V
e
bottom side or 140 R26 Vcc1_5_B[40] Vcc3_3[13] B13
SMC0603 20% SMC0402 T22 B16 C7U2 C7U4 C7V13
mils on the top Vcc1_5_B[41] Vcc3_3[14] 0.1uF 0.1uF 0.1uF
T23 Vcc1_5_B[42] Vcc3_3[15] B7
T26 C10 10% 10V 10% 10V 10% 10V
Vcc1_5_B[43] Vcc3_3[16]
PCI
T27 D15 SMC0402 SMC0402 SMC0402
Vcc1_5_B[44] Vcc3_3[17]
T28 F9
h
4,10,27,48,56,58 +V1.5S Vcc1_5_B[45] Vcc3_3[18] Layout Note: Distribute in PCI section 14 +V3.3A_RTC
U22 Vcc1_5_B[46] Vcc3_3[19] G11
U23 Vcc1_5_B[47] Vcc3_3[20] G12
V22 Vcc1_5_B[48] Vcc3_3[21] G16
V23 Vcc1_5_B[49]
c
W22 W5 C7V7 C7V8
Vcc1_5_B[50] VccRTC 0.1uF 0.1uF
W23 Vcc1_5_B[51]
C7V20 Y22 P7 +V3.3A 10% 10V 10% 10V
0.1uF Vcc1_5_B[52] VccSus3_3[1] SMC0402 SMC0402
Y23 Vcc1_5_B[53]
Place within 100 mils 10% 10V A24 13,14,16,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57
VccSus3_3[2]
-s
of ICH on the bottom SMC0402 B27 C24
Vcc3_3[1] VccSus3_3[3] C7U6 C8G2
side or 140 mils on VccSus3_3[4] D19
AG28 D22 0.1uF 0.1uF
the top near pin AG5 VccDMIPLL VccSus3_3[5]
G19 10% 10V 10% 10V
VccSus3_3[6]
AB7 SMC0402 SMC0402
4,10,27,48,56,58 +V1.5S Vcc1_5_A[1]
AC6 Vcc1_5_A[2] VccSus3_3[7] K3
AC7 Vcc1_5_A[3] VccSus3_3[8] K4
AD6 K5 +V3.3A 13,14,16,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57
Vcc1_5_A[4] VccSus3_3[9]
ARX
p
C7V14 AE6 K6
Place within 100 mils of 0.1uF AF5 L1
ICH on the bottom side 10% 10V AF6 L2
USB
SMC0402 AG5 L3 C7V4 C7V1
or 140 mils on the top Vcc1_5_A[8] VccSus3_3[13]
AH5 L6 0.1uF 0.1uF
10% 10V 10% 10V
o
VccSus3_3[15] L7
+V3.3S 5,7,10,12,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
AD2 VccSATAPLL M6 SMC0402 SMC0402
VccSus3_3[16]
VccSus3_3[17] M7
B B
t
AH11 N7 4,10,27,48,56,58 +V1.5S
Vcc3_3[2] VccSus3_3[18]
Place within 100 mils of C7V19 +V1.5S 4,10,27,48,56,58 AB10 AB17
Vcc1_5_A[10] Vcc1_5_A[19]
ICH on the bottom side or 0.1uF AB9 AC17
Vcc1_5_A[11] Vcc1_5_A[20]
140 mils on the top 10% 10V AC10 Vcc1_5_A[12]
p
SMC0402 AD10 T7
Vcc1_5_A[13] Vcc1_5_A[21]
13,14,16,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A AE10 F17
Vcc1_5_A[14] Vcc1_5_A[22]
ATX
AF10 Vcc1_5_A[15] Vcc1_5_A[23] G17

C7H1 AF9 +V1.5S 4,10,27,48,56,58
1UF Vcc1_5_A[16]
AG9 Vcc1_5_A[17] Vcc1_5_A[24] AB8
Place within 100 mils of ICH on 20% C7U7
la
AH9 Vcc1_5_A[18] Vcc1_5_A[25] AC8
the bottom side or 140 mils on 0.1uF
the top near AG9 10% 10V +V1.5S 4,10,27,48,56,58 E3 K7 TP_ICHVCCSUS1
VccSus3_3[19] VccSus1_05[1]
SMC0402
C1 C28 TP_ICHVCCSUS2 4,10,27,48,56,58 +V1.5S
VccUSBPLL VccSus1_05[2]
.
G20 TP_ICHVCCSUS3
TP_VCCSUSLAN1 VccSus1_05[3]
C7U5 AA2
0.1uF TP_VCCSUSLAN2 VccSus1_05/VccLAN1_05[1]
Y7 VccSus1_05/VccLAN1_05[2]Vcc1_5_A[26] A1
10% 10V H6
Vcc1_5_A[27]
USB CORE
SMC0402 H7 +V1.5S 4,10,27,48,56,58

Vcc1_5_A[28]
J6 4,10,27,48,56,58 +V1.5S
Vcc1_5_A[29]
J7
w
Vcc1_5_A[30]
C7V3
ICH7M REV 1.02 EDS 0.1uF
Place within 100 mils of 10% 10V C7V11
ICH on the bottom side SMC0402 0.1uF
10% 10V
or 140 mils on the top
SMC0402
w
AG11
AG14
AG17
AG20
AG25
AC11
AD11
AD15
AD19
AD23
AH12
AH23
AH27
AA24
AA25
AA26
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AE11
AE13
AE18
AE21
AE24
AE25
AF11
AF27
AF28
ICH7M REV 1.02 EDS

W24
W25
W26
AG1
AG3
AG7
AC2
AC5
AC9
AD1
AD3
AD4
AD7
AD8
AH1
AH3
AH7
AA1
AB4
AB6
AE2
AE4
AE8
R11
R12
R13
R14
R15
R16
R17
R18
U12
U13
U14
U15
U16
U17
U24
U25
U26
AF2
AF4
AF8
P28
V13
V15
V24
V27
V28
Y24
Y27
Y28
T12
T13
T14
T15
T16
T17
W6
R1
U4
V2
Y3
T6
A A
U7G1E Capell Valley Intel Confidential
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
Title
w
ICH7-M (4 of 4)
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]

M12
M13
M14
M15
M16
M17
M24
M27
M28
G14
G18
G21
G24
G25
G26
C27
D10
D13
D18
D21
D24
H24
H27
H28
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
A D15378 1.501
A23
B11
B14
B17
B20
B26
B28
E15
K24
K27
K28
P12
P13
P14
P15
P16
P17
P24
P27
F12
F27
F28
L13
L15
L24
L25
L26
J24
J25
J26
M3
M4
M5
G1
G2
G5
G6
G9
C2
C6
H3
H4
H5
N1
N2
N5
N6
A4
B1
B8
E1
E2
E4
E8
P3
P4
F3
F4
F5
J1
J2
J5

5 4 3 2 1
5 4 3 2 1
m
10,20,49,56,58 +V2.5S 5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
C6D15 C7T1
0.1uF 0.1uF
7
Vp
Vp
CR7D1 ESD DIODE ARRAY CR7T1 ESD DIODE ARRAY
c
D D
CRT_Q_VSYNC
.
CRT_RED 1 8 1 8
I/O1 I/O6 7,20 TV_DACA_OUT I/O1 I/O6 CRT_Q_HSYNC
CRT_GREEN 2 6 2 6
I/O2 I/O5 7,20 TV_DACB_OUT I/O2 I/O5
CRT_BLUE 4 5 4 5
I/O3 I/O4 7,20 TV_DACC_OUT I/O3 I/O4
s
Vn
Vn
it c
3
3
5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
a
+V3.3S
+V3.3S 5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
R7R12 C6D12
10K 5 0.1uF 5,10,17,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S
13,19,27,55,56 +VBATS
m
5% U7D7
INVERTER +V5S_F_DAC
DOCK_VGA_EN# 2 4 CRT_EN# F2A1
+
C R2M7 C
R7R13 1K
e
1.1A
2
10K 3
5% DDC_GATE
1 Q2B1
NO_STUFF Note: FB2A3
10,20,49,56,58 +V2.5S BSS138 50OHM
For video bandwidths > 200MHz:
R2M8
h
C3B1, C3A4, C2B1, C2A5, C2B2, C2B3 = 3.3pF
C7R11 100K
C3A1, C2A4, C2A6 = No_Stuff
DDC_SRC
3
U7D6
5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
0.1uF +V3.3S FB3A1, FB2A5, FB2B2 = Short
+V5S_L_DAC
1 OE1# VCC 8
c
2 R2A5 R2B1
7 CRT_RED 1A OE2# 7 CRT_Q_RED 2.2k 2.2k
3 1B 2B 6
TP_DOCK_VGA_RED 4 R8E1
GND 2A 5 2.2K Q8E1
74CB3Q330 BSS138
-s
2 3 CRT_DDC_DATA_ISO
7 CRT_DDC_DATA
10,20,49,56,58 +V2.5S
5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
C7R7 +V3.3S
CRT_DDC_CLK_ISO
U7D8 0.1uF
1
1 OE1# VCC 8
p
2 7 CRT_Q_RED FB3B1 CRT_L_RED FB3A1
7 CRT_GREEN 1A OE2#
3 6 CRT_Q_GREEN 47ohm@100MHz 47ohm@100MHz
TP_DOCK_VGA_GRN 1B 2B C3B1 C3A4 C3A1
4 GND 2A 5
R3B1 10pF 22pF 10pF
74CB3Q330 150 5%
5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S 1% J2A2B
o
GND1 19
CRT_L2_RED RED 14 24 NC2
B B
t
10,20,49,56,58 +V2.5S GND2 18
R8E2 CRT_Q_GREEN FB3B2 CRT_L_GREEN FB2A5 CRT_L2_GREEN GRN 13 23 DATA
C7R9 2.2K Q8E3 47ohm@100MHz 47ohm@100MHz GND3 17
R3B2 C2B1 C2A5 C2A4 CRT_L2_BLUE BLU 12 22 HSYNC
BSS138 150
U7D9 0.1uF 10pF 22pF 10pF VCC 16
1%
p
1 8 2 3 5% NC1 11 21 VSYNC
OE1# VCC 7 CRT_DDC_CLK GND4
7 CRT_BLUE 2 1A OE2# 7 15
3 6 CRT_Q_BLUE GND5 10 20 CLK
TP_DOCK_VGA_BLUE 1B 2B +V3.3S
4 GND 2A 5
5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 CRT_Q_BLUE FB2B3 CRT_L_BLUE FB2B2 2IN1
74CB3Q330 1 47ohm@100MHz 47ohm@100MHz
la
R2B2 C2B2 C2B3 C2A6
150 10pF 22pF 10pF
1% 5%
+V3.3S 5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
.
C7R12
U7D11 0.1uF CRT_Q_VSYNC R7E1 39 CRT_R_VSYNC

1 OE1# VCC 8
7 CRT_VSYNC 2 1A OE2# 7
3 6 TP_DOCK_Q_VSYNC CRT_Q_HSYNC R7E2 39 CRT_R_HSYNC
w
CRT_Q_VSYNC 2Y 1Y
4 GND 2A 5
C7E1 C7D1
SN74LVC2G125 33pF 33pF
5% 5%
NO_STUFF NO_STUFF
w
Buffers provide
voltage translation +V3.3S 5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
A from 2.5 to 3.3V A
C7T2 Capell Valley Intel Confidential
U7E1 0.1uF Title
w
1 8
7 CRT_HSYNC 2
OE1#
1A
VCC
OE2# 7 CRT
3 6 TP_DOCK_Q_HSYNC
CRT_Q_HSYNC 2Y 1Y
4 GND 2A 5
SN74LVC2G125 Size Document Number Rev

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
m
+V5S 5,10,17,18,20,25,26,39,41,43,44,45,47,51,52,54,55,56
o
C6G2
+V3.3S
+VBAT 52,54,55,56 0.1uF 5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
c
C6G4 C6F2
D 0.1uF D
10%
.
0.1uF
it cs
LVDS Panel Backlight
BIOS Note: Disable both
BKLTSEL lines before
enabling one.
+V3.3S 5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
+V3.3S 5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
a
5,10,17,18,20,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S
C7T11
R7T10 +V3.3S
U7E5 0.1uF 10K R6F2 5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
1 8 10K C7E5 +VBAT 52,54,55,56
35,42 L_BKLTSEL0# OE1# VCC
7 L_BKLTCTL 2 1A OE2# 7 L_BKLTSEL1# 35,42
m
3 6 U6F1 0.1uF
1B 2B
4 GND 2A 5 L_CLKCTLB 7,37 35,42 L_BKLTSEL1# 1 OE# VCC 5
GMCH_PWM Support +V5S 5,10,17,18,20,25,26,39,41,43,44,45,47,51,52,54,55,56
74CBT3306 2 J5F1
GM_Data_D Support 7,37 L_CLKCTLA A
C 1 VDD_BLI C
GM_CLK_D Support
e
3 GND Y 4 2 VSS_BLI
3 VSS_DBC
74CBTLV1G125 4 VDD_DBC
DBL_CLK 5 DBL_CLK
L_BRIGHTNESS 6 DBL_DATA
7 ENA_BL
h
7 L_BKLTEN
5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S R6V3 100K 8 NC
9 VDD_ALS
5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S 10 VSS_ALS
32,36 EMA_ALS_CLK 11 ALS_CLK
c
Q5G2 32,36 EMA_ALS_DATA 12 ALS_DATA
5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S 13 ALS_INTR
32,45 KBC_PROG_TX# L_VBATS_LPP
13,18,27,55,56 +VBATS SI4425DY 14 VDD_LPP
3 8 R6V2 15 VSS_VDL
2 7 10K
5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
R6V1 +V3.3S L_VDD_VDL1 16 VDD_VDL1
-s
1 6 10K L_VDD_VDL2 17 VDD_VDL2
5 18 VDD_VCL
19 RSVD
C5V5 20 VCL_CLK
7 L_DDC_CLK
R5V12 1000pF C5G2 C6F3
4
7 L_DDC_DATA 21 VCL_DATA
1M 22UF 0.1uF 22 A0M
10% 7 LA_DATAN0
7 LA_DATAP0 23 A0P
3 L_VDDEN_LPP#
R5V11 100K L_VDDEN_LPP_D# 24 VSS_SHIELD1
p
7 LA_DATAN1 25 A1M
7 LA_DATAP1 26 A1P
27 VSS_SHIELD2
7 LA_DATAN2 28 A2M
7 LA_DATAP2 29 A2P
o
30 VSS_SHIELD3
7 LA_CLKN 31 VDL_CLKAM
7 LA_CLKP 32 VDL_CLKAP
B B
t
L_VDDEN Q6G1 33 VSS
BSS138 J6E1 34 B0M
7 LB_DATAN0
1 L_VBATS_LPP 7 LB_DATAP0 35 B0P
7 L_VDDEN L_VDD_VDL2 1
2 36 VSS_SHIELD4
3 7 LB_DATAN1 37 B1M
p
R6V10
2
4 7 LB_DATAP1 38 B1P
L_VDD_VDL1 39 VSS_SHIELD5
100K L_VDD_VDL 5
6 7 LB_DATAN2 40 B2M
7 LB_DATAP2 41 B2P
6Pin_HDR 42 VSS_SHIELD6
la
7 LB_CLKN 43 VDL_CLKBM
7 LB_CLKP 44 VDL_CLKBP
+V3.3S 5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 LVDS,CONN44

LPP Jumper J6E1 Key
SI2307DS
.
Jumper Default Option Description
Q6E1
2 3
J6E1 5-6 J5F1 Pin-16 gets +V3.3S
C6E14 C7E6 4-5 J5F1 Pin-16 gets +VBATS
w
R6E2 C6E9
1M 1000pF 22uF 0.1uF J6E1 2-3 J5F1 Pin-17 gets +V3.3S
1-2 J5F1 Pin-17 gets +VBATS
1
R6E3 100K L_VDDEN_D#

3 L_VDDEN#
w
A A
Q6E2 Capell Valley Intel Confidential
BSS138
L_VDDEN Title
w
1
LVDS
2

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
5,7,10,12,13,14,15,16,17,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
+V3.3S +V3.3S
5,7,10,12,13,14,15,16,17,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
m
C6M9
R6M10 0.1uF
10K 5
5% U6A4
INVERTER
o
DOCK_TV_EN# 2 4 TV_EN#
Layout Note:
R6M12 Place 150 Ohm termination
10K 3
c
resistors, ferrite beads and
5% 10,18,49,56,58 +V2.5S
capicators close to
D NO_STUFF
connector
D
.
C6M11
U6A5
1 8 0.1uF
OE1# VCC
7,18 TV_DACA_OUT 2 1A OE2# 7
3 6 DACA FB2A2 DACA_L
s
TP_DOCK_TV_DACA_OUT 1B 2B 150ohm@100MHz
4 GND 2A 5
C1A3 C1A1
74CB3Q330 R1M1 5.6pF 5.6pF
150 4.5% 4.5%
1%
it c
10,18,49,56,58 +V2.5S
C6M7
U6B1
1 8 0.1uF
OE1# VCC Note:
7,18 TV_DACB_OUT 2 1A OE2# 7
3 6 DACB FB2A1 DACB_L ESD Diode Array for the TV
TP_DOCK_TV_DACB_OUT 1B 2B 150ohm@100MHz
4 GND 2A 5 DAC A, DAC B, DAC C signals
C2A3 C2A2
located on CRT page.
74CB3Q330 R2M6 5.6pF 5.6pF
a
150 4.5% 4.5%
1%
10,18,49,56,58 +V2.5S Port Value Voltage
IO2 IO1 IO0 Format Aspect Ratio Line1 Line2 Line3
C6N1 0 0 0b 525i (480) 4:3 0V 0V 0V
U6A2 0 0 1b 525i (480) 16:9 0V 0V 5V
1 8 0.1uF 0 0 Xb 525i (480) 4:3 Letterbox 0V 0V 2.2V
OE1# VCC
m
2 7 0 1 0b 525p (480) 4:3 0V 5V 0V
7,18 TV_DACC_OUT 1A OE2# DACC 0 1 1b 525p (480) 16:9 0V 5V 5V
3 6 FB1A1 DACC_L
TP_DOCK_TV_DACC_OUT 1B 2B 150ohm@100MHz 0 1 Xb 525p (480) 4:3 Letterbox 0V 5V 2.2V
4 GND 2A 5
C1A4 C1A2 X 1 0b 750p (720) 4:3 2.2V 5V 0V
C 74CB3Q330 R1M2 5.6pF 5.6pF X 1 1b 750p (720) 16:9 2.2V 5V 5V C
150 4.5% 4.5% J2A1 1 0 0b 1125i (1080) 4:3 5V 0V 0V
e
1% 1 8 1 0 1b 1125i (1080) 16:9 5V 0V 5V
2 9 1 1 0b 1125p (1080) 4:3 5V 5V 0V
3 10 1 1 1b 1125p (1080) 16:9 5V 5V 5V
4 11
5 12
h
6 13
7 14
CON14_DCONN-CP4120
c
Note:
Pins 12 & 14 are shorted
inside D-Connector plug.
- s
5,10,17,18,19,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S
p
5,10,17,18,19,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
C2A7
o
R2A11 R2A12 R2A13 R2A14 R2A15
2.2K 2.2K 1.0uF 10K
B B
t
5.90K 5.90K
U2A2 1% 1%
10 1 DLINE3_IO R2A16 10K DLINE3
I2C_RST#
VDD IO_0 DLINE2_IO R2A17 10K DLINE2

7 TV_DCONSEL1 9 SDA IO_1 2
8 3 DLINE1_IO R2A18 10K DLINE1
7 TV_DCONSEL0 SCL IO_2
p
7 INT# IO_3 4
6 RESET# VSS 5
R2A19 R2A20
I2C - PCA9537 4.7K 4.7K
. la
A
ww Capell Valley
Title
Intel Confidential
A
w
TV

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
o m
c
D D
.
M_A_DQ[63:0] 8
s
J5P1A CON200_DDR2-SODIMM-STAN
8,23 M_A_A[13:0] M_A_A0 M_A_DQ0
102 A0 DQ0 5
M_A_A1 101 7 M_A_DQ1
M_A_A2 A1 DQ1 M_A_DQ2
100 A2 DQ2 17
M_A_A3 99 M_A_DQ3
DQ3 19
it c
M_A_A4 A3 M_A_DQ4
98 A4 DQ4 4
M_A_A5 97 M_A_DQ5
M_A_A6 A5 DQ5 6 M_A_DQ6
94 A6 DQ6 14
M_A_A7 92 M_A_DQ7
M_A_A8 A7 DQ7 16 M_A_DQ8
93 A8 DQ8 23
M_A_A9 91 25 M_A_DQ9 7,9,22,34,46,47,56,58 +V1.8 J5P1B CON200_DDR2-SODIMM-STAN
M_A_A10 A9 DQ9 M_A_DQ10
105 A10/AP DQ10 35
M_A_A11 90 37 M_A_DQ11 112 18
M_A_A12 A11 DQ11 M_A_DQ12 VDD1 VSS16
89 A12 DQ12 20 111 VDD2 VSS17 24
M_A_A13 M_A_DQ13
a
116 A13 DQ13 22 117 VDD3 VSS18 41
86 M_A_DQ14
A14 DQ14 36 M_A_DQ15
96 VDD4 VSS19 53
84 A15 DQ15 38 95 VDD5 VSS20 42
85 M_A_DQ16
8,23 M_A_BS2 A16_BA2 DQ16 43 M_A_DQ17
118 VDD6 VSS21 54
DQ17 45 M_A_DQ18
81 VDD7 VSS22 59
8,23 M_A_BS0 107 BA0 DQ18 55 82 VDD8 VSS23 65
106 57 M_A_DQ19
5,7,10,12,13,14,15,16,17,18,19,20,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S 87 60
8,23 M_A_BS1 BA1 DQ19 M_A_DQ20 VDD9 VSS24
7,23 M_CS#0 110 S0# DQ20 44 103 VDD10 VSS25 66
M_A_DQ21
m
7,23 M_CS#1 115 S1# DQ21 46 88 VDD11 VSS26 127
30 M_A_DQ22
7 M_CLK_DDR0 CK0 DQ22 56 M_A_DQ23 C4C12 C4C10
104 VDD12 VSS27 139
7 M_CLK_DDR#0 32 CK0# DQ23 58 VSS28 128
164 M_A_DQ24 2.2uF
7 M_CLK_DDR1 CK1 DQ24 61 199 VDDSPD VSS29 145
C 7 M_CLK_DDR#1 166 CK1# DQ25 63
M_A_DQ25 0.1uF
VSS30 165 C
M_A_DQ26
e
7,23 M_CKE0 79 CKE0 DQ26 73 83 NC1 VSS31 171
80 75 M_A_DQ27 120 172
7,23 M_CKE1 CKE1 DQ27 M_A_DQ28 NC2 VSS32
8,23 M_A_CAS# 113 CAS# DQ28 62 50 NC3 VSS33 177
108 64 M_A_DQ29 69 187
8,23 M_A_RAS# RAS# DQ29 M_A_DQ30 7,23 PM_EXTTS#0 NC4 VSS34
8,23 M_A_WE# 109 WE# DQ30 74 163 NCTEST VSS35 178
SA0_DIM0 198 M_A_DQ31
DQ31 76 190
h
SA1_DIM0 SA0 M_A_DQ32 VSS36
200 SA1 DQ32 123 47,58 M_VREF_DIMM0 1 VREF VSS37 9
197 M_A_DQ33
14,22,23 SMB_CLK_S2 SCL DQ33 125 M_A_DQ34 C6P2 C6P1 VSS38 21
14,22,23 SMB_DATA_S2 195 SDA DQ34 135 201 GND0 VSS39 33
M_A_DQ35 2.2uF
DQ35 137 M_A_DQ36
202 GND1 VSS40 155
c
R4C17 R4C25 7,23 M_ODT0 114 124 0.1uF 34
ODT0 DQ36 M_A_DQ37 VSS41
7,23 M_ODT1 119 ODT1 DQ37 126 VSS42 132
134 M_A_DQ38 47 144
8 M_A_DM[7:0] M_A_DM0 DQ38 M_A_DQ39 VSS1 VSS43
10K 10K 10
M_A_DM1 DM0 DQ39 136 M_A_DQ40
133 VSS2 VSS44 156
26 DM1 DQ40 141 183 VSS3 VSS45 168
s
M_A_DM2 52 M_A_DQ41 7,9,22,34,46,47,56,58 +V1.8
M_A_DM3 DM2 DQ41 143 M_A_DQ42
77 VSS4 VSS46 2
67 DM3 DQ42 151 12 VSS5 VSS47 3
M_A_DM4 130 M_A_DQ43
DM4 DQ43 153 48 VSS6 VSS48 15
-
M_A_DM6 DM5 DQ44 140 M_A_DQ45 C4C11 C5C9 C5B17 C5R1
184 VSS7 VSS49 27
170 DM6 DQ45 142 78 VSS8 VSS50 39
DM7 DQ46 152 M_A_DQ47 0.1uF 0.1uF 0.1uF 0.1uF
71 VSS9 VSS51 149
8 M_A_DQS[7:0] DQ47 154 72 VSS10 VSS52 161
M_A_DQS0 13 M_A_DQ48
M_A_DQS1 DQS0 DQ48 157 M_A_DQ49
121 VSS11 VSS53 28
p
31 DQS1 DQ49 159 122 VSS12 VSS54 40
196 VSS13 VSS55 138
70 DQS3 DQ51 175 Layout Note: Place these Caps near So-Dimm0. 193 VSS14 VSS56 150
8 VSS15 VSS57 162
148 DQS5 DQ53 160
M_A_DQS6 M_A_DQ54
o
169 DQS6 DQ54 174
8 M_A_DQS#[7:0] M_A_DQS#0 DQS7 DQ55 176 M_A_DQ56
11 DQS#0 DQ56 179
B B
t
M_A_DQS#1 29 M_A_DQ57
M_A_DQS#2 DQS#1 DQ57 181 M_A_DQ58
49 DQS#2 DQ58 189
129 DQS#4 DQ60 180
p
167 DQS#6 DQ62 192
M_A_DQS#7 186 194 M_A_DQ63
DQS#7 DQ63
Layout Note: Place these Caps near So-Dimm0.
la
7,9,22,34,46,47,56,58 +V1.8
.
C4C15 C5C12 C5C5 C5C10 C5C4
2.2uF 2.2uF 2.2uF 2.2uF 2.2uF
ww Capell Valley
Title
Intel Confidential
A
w
DDR SODIMM 0

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
J5N1A
M_B_DQ[63:0] 8
CON200_DDR2-SODIMM-REV
8,23 M_B_A[13:0] M_B_A0 M_B_DQ0
102 A0 DQ0 5
M_B_A1 101 7 M_B_DQ1
M_B_A2 A1 DQ1 M_B_DQ2
100 DQ2 17
it c
M_B_A3 A2 M_B_DQ3
99 A3 DQ3 19
M_B_A4 98 M_B_DQ4
M_B_A5 A4 DQ4 4 M_B_DQ5
97 A5 DQ5 6
M_B_A6 94 M_B_DQ6 7,9,21,34,46,47,56,58 +V1.8 J5N1B CON200_DDR2-SODIMM-REV
M_B_A7 A6 DQ6 14 M_B_DQ7
92 A7 DQ7 16
M_B_A8 93 23 M_B_DQ8 112 18
M_B_A9 A8 DQ8 M_B_DQ9 VDD1 VSS16
91 A9 DQ9 25 111 VDD2 VSS17 24
M_B_A10 105 M_B_DQ10
M_B_A11 A10/AP DQ10 35 M_B_DQ11
117 VDD3 VSS18 41
90 A11 DQ11 37 96 VDD4 VSS19 53
M_B_A12 M_B_DQ12
a
89 A12 DQ12 20 95 VDD5 VSS20 42
M_B_A13 116 M_B_DQ13
A13 DQ13 22 M_B_DQ14
118 VDD6 VSS21 54
86 A14 DQ14 36 81 VDD7 VSS22 59
84 M_B_DQ15
A15 DQ15 38 M_B_DQ16
82 VDD8 VSS23 65
8,23 M_B_BS2 85 A16_BA2 DQ16 43 87 VDD9 VSS24 60
45 M_B_DQ17 103 66
DQ17 M_B_DQ18 VDD10 VSS25
8,23 M_B_BS0 107 BA0 DQ18 55 88 VDD11 VSS26 127
106 57 M_B_DQ19
5,7,10,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S 104 139
8,23 M_B_BS1 BA1 DQ19 M_B_DQ20 VDD12 VSS27
m
7,23 M_CS#2 110 S0# DQ20 44 VSS28 128
115 M_B_DQ21
7,23 M_CS#3 S1# DQ21 46 199 VDDSPD VSS29 145
5,7,10,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
30 M_B_DQ22
7 M_CLK_DDR3 CK0 DQ22 56 M_B_DQ23 C4B11 C4B13 VSS30 165
7 M_CLK_DDR#3 32 CK0# DQ23 58 83 NC1 VSS31 171
C 7 M_CLK_DDR2 164 CK1 DQ24 61
M_B_DQ24 2.2uF 120 NC2 VSS32 172 C
M_B_DQ25 0.1uF
e
7 M_CLK_DDR#2 166 CK1# DQ25 63 50 NC3 VSS33 177
79 73 M_B_DQ26 69 187
7,23 M_CKE2 CKE0 DQ26 M_B_DQ27 NC4 VSS34
7,23 M_CKE3 80 CKE1 DQ27 75 163 NCTEST VSS35 178
+V3.3S 113 M_B_DQ28
8,23 M_B_CAS# CAS# DQ28 62 M_B_DQ29 7,23 PM_EXTTS#1 VSS36 190
8,23 M_B_RAS# 108 RAS# DQ29 64 47,58 M_VREF_DIMM1 1 VREF VSS37 9
109 M_B_DQ30
DQ30 74 21
h
8,23 M_B_WE# SA0_DIM1 WE# M_B_DQ31 VSS38
198 C6B10 C6B9
R4B19 SA1_DIM1 SA0 DQ31 76 M_B_DQ32 2.2uF
201 GND0 VSS39 33
200 SA1 DQ32 123 202 GND1 VSS40 155
10K 197 M_B_DQ33 0.1uF
14,21,23 SMB_CLK_S2 SCL DQ33 125 M_B_DQ34 VSS41 34
14,21,23 SMB_DATA_S2 195 SDA DQ34 135 VSS42 132
M_B_DQ35 7,9,21,34,46,47,56,58 +V1.8
c
DQ35 137 47 VSS1 VSS43 144
114 M_B_DQ36
7,23 M_ODT2 ODT0 DQ36 124 M_B_DQ37
133 VSS2 VSS44 156
7,23 M_ODT3 119 ODT1 DQ37 126 183 VSS3 VSS45 168
M_B_DQ38
8 M_B_DM[7:0] M_B_DM0 DQ38 134 M_B_DQ39 C5C11 C4R2 C5B15 C4R1
77 VSS4 VSS46 2
10 DM0 DQ39 136 12 VSS5 VSS47 3
s
R4B20 M_B_DM1 26 M_B_DQ40
M_B_DM2 DM1 DQ40 141 M_B_DQ41 0.1uF 0.1uF 0.1uF 0.1uF
48 VSS6 VSS48 15
52 DM2 DQ41 143 184 VSS7 VSS49 27
M_B_DM3 67 M_B_DQ42
DM3 DQ42 151 78 VSS8 VSS50 39
-
10K M_B_DM4 130 M_B_DQ43
M_B_DM5 DM4 DQ43 153 M_B_DQ44
71 VSS9 VSS51 149
147 DM5 DQ44 140 72 VSS10 VSS52 161
M_B_DM6 170 M_B_DQ45
M_B_DM7 DM6 DQ45 142 M_B_DQ46
121 VSS11 VSS53 28
185 DM7 DQ46 152 122 VSS12 VSS54 40
M_B_DQ47
8 M_B_DQS[7:0] M_B_DQS0 DQ47 154 M_B_DQ48
196 VSS13 VSS55 138
p
13 DQS0 DQ48 157 Layout Note: Place these Caps near So-Dimm1. 193 VSS14 VSS56 150
M_B_DQS1 31 M_B_DQ49
M_B_DQS2 DQS1 DQ49 159 M_B_DQ50
8 VSS15 VSS57 162
51 DQS2 DQ50 173
131 DQS4 DQ52 158
M_B_DQS5 M_B_DQ53 7,9,21,34,46,47,56,58 +V1.8
o
148 DQS5 DQ53 160
8 M_B_DQS#[7:0] 188 DQS7 DQ55 176
B B
t
M_B_DQS#0 11 M_B_DQ56
M_B_DQS#1 DQS#0 DQ56 179 M_B_DQ57
29 DQS#1 DQ57 181
M_B_DQS#2 49 M_B_DQ58 C4C14 C4B15 C4B12 C5B14 C4C13
68 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF
129 DQS#4 DQ60 180
M_B_DQS#5 M_B_DQ61
p
146 DQS#5 DQ61 182
M_B_DQS#6 167 192 M_B_DQ62
M_B_DQS#7 DQS#6 DQ62 M_B_DQ63
186 DQS#7 DQ63 194
la
Layout Note: Place these Caps near So-Dimm1.
.
SO-DIMM 1 is placed farther from
the GMCH than SO-DIMM 0
ww Capell Valley
Title
Intel Confidential
A
w
DDR2 SODIMM 1

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
DDR2 Thermal Sensor So-Dimm 0 & 1
m
Layout Note:
Place Q5N2
under DIMM0
o
DDR_THERM1 +V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
Q5N2
2
2N3904 U5P1
c
1 DDR_THERM2 1 Vdd SCLK 8 SMB_CLK_S2 14,21,22
D +V0.9 46,56,58
D
.
2 D+ SDATA 7 SMB_DATA_S2 14,21,22
3
3 D- ALERT# 6 PM_EXTTS#0_D PM_EXTTS#0 7,21
R5P1 0 R5C6 56
PM_EXTTS#1_D M_CKE0 7,21
4 5 R5C11 56
7,22 PM_EXTTS#1 M_CKE1 7,21
s
R5P4 0 THERM# GND R5B10 56
M_CKE2 7,22
ADM1032AR R5C1 56
M_CKE3 7,22
Layout Note: R4C23 56
M_ODT0 7,21
R4C15 56
it c
Place U5P1 M_ODT1 7,21
R4C6 56
under DIMM1 M_ODT2 7,22
R4B17 56
M_ODT3 7,22
R4C16 56
M_A_BS0 8,21
R4C20 56
M_A_BS1 8,21
R5C7 56
M_A_BS2 8,21
R4C12 56
M_A_WE# 8,21
R4C13 56
M_A_CAS# 8,21
R4C21 56
a
M_A_RAS# 8,21
R4B13 56
M_B_BS0 8,22
R4C3 56
M_B_BS1 8,22
R5B11 56
M_B_BS2 8,22
Layout note: Place one cap close to every 2 pullup resistors terminated to +V0.9
+V0.9 46,56,58 R4B14 56
M_B_WE# 8,22
R4B15 56
M_B_CAS# 8,22
m
R4C4 56
M_B_RAS# 8,22
R4C22 56
M_CS#0 7,21
R4C14 56
M_CS#1 7,21
C C4C6 C5C14 C5C7 C4C8 C4C2 C4B9 C5B9 C4C3 C4C4 C5B10 C4C9 C4C7 C5B8 R4C5 56
M_CS#2 7,22 C
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R4B16 56
e
M_CS#3 7,22
M_A_A0 M_A_A[13:0] 8,21

R4C19 56
R4C10 56 M_A_A1
R4C18 56 M_A_A2
h
C5C13 C5C1 C4C1 C4B7 C5C2 C4C18 C4C16 C4C17 C5B12 C5C8 C5C6 C4B6 C4B8 R4C9 56 M_A_A3
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R5C15 56 M_A_A4
R4C8 56 M_A_A5
R5C14 56 M_A_A6
M_A_A7
c
R5C13 56
R5C10 56 M_A_A8
R5C9 56 M_A_A9
R4C11 56 M_A_A10
R5C12 56 M_A_A11
s
R5C8 56 M_A_A12
R4C24 56 M_A_A13
M_B_A[13:0] 8,22
-
R4C2 56 M_B_A0
R4B11 56 M_B_A1
R4C1 56 M_B_A2
R4B10 56 M_B_A3
R5C5 56 M_B_A4
M_B_A5
p
R4B9 56
R5C4 56 M_B_A6
R5C3 56 M_B_A7
R5B14 56 M_B_A8
R5B13 56 M_B_A9
R4B12 56 M_B_A10
o
R5C2 56 M_B_A11
R5B12 56 M_B_A12
B B
t
R4C7 56 M_B_A13
la p
w .
w
A A
Title
w
DDR2 TERMINATION AND THERMAL SENSOR

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
13,14,16,17,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
m
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
13,14,16,17,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
R9G6
C9G2 1.40K
1%
o
0.1uF
R8V11 R8W9 R8W2 R8V10 R8W1 C8W1 C8W2 C8W3
0.1uF 10UF 0.1uF U9G2
10K 10K 10K 10K 10K 16 15 PCA9557_RST#
U8G1 VDD RESET#
8
c
VSS BOARD_ID0
I/O0 6
D 37 11 1 7 BOARD_ID1 D
14 FWH_INIT# INIT# VPP 32,35,50 SMB_BS_CLK SCLK I/O1 BOARD_ID2
100 PLT_RST#_D12
.
R8W6 10 2 9
7,13,15,28,32,41,42,57 PLT_RST# RST# VCC2 32,35,50 SMB_BS_DATA SDATA I/O2 BOARD_ID3
VCC1 31 I/O3 10
9 39 R9V9 A0_R
0 3 11 REV_FAB_ID0
31 CLK_PCIF_FWH CLK VCCA A1_R A0 I/O4 REV_FAB_ID1
R9V8 0 4 12
FGPI4 R9V7 A2_R
0 A1 I/O5 REV_FAB_ID2
7 5 13
s
FGPI3 FGPI4 TBL# R8F4 100 A2 I/O6 REV_FAB_ID3
15 FGPI3 TBL# 20 FWH_TBL# 15,35 I/O7 14
FGPI2 16 19 WP# R8W7 100
FGPI1 FGPI2 WP# FWH_WP# 15,35 PCA9557PW
17 FGPI1
FGPI0 18 38
FGPI0 FWH4 LPC_FRAME# 14,32,35,41,42
28
it c
TP_FWH_ID3 FWH3 LPC_AD3 14,32,35,41,42
21 FWH 27
TP_FWH_ID2 ID3 FWH2 LPC_AD2 14,32,35,41,42
TP_FWH_ID1
22 ID2 FWH1 26 LPC_AD1 14,32,35,41,42 8-bit I/O Port Expander
23 ID1 FWH0 25 LPC_AD0 14,32,35,41,42
TP_FWH_ID0 24 ID0 IC_R
IC 2
TP_FWH_RSVD2 32
TP_FWH_RSVD1 RSVD2 TP_FWH_NC1
33 RSVD1 NC1 1
TP_FWH_RSVD5 34 3 TP_FWH_NC2
TP_FWH_RSVD4 RSVD5 NC2 TP_FWH_NC3
35 RSVD4 NC3 4
TP_FWH_RSVD3 TP_FWH_NC4
a
36 RSVD3 NC4 5
6 TP_FWH_NC5
NC5 TP_FWH_NC6
29 GND2 NC6 8
TP_FWH_NC7
slave address
30 GND1 NC7 13
40 14 TP_FWH_NC8 R8W3
GNDA NC8 10K
0 0 1 1 A2 A1 A0 R/W
m
fixed programmable
FWH sits in the PCA9557 Address
C FWH_TSOP_Socket, C
Not on the board
h e
FAB ID Strapping Table
FAB_REV BOARD FAB
c
3 2 1 0
0 0 0 0 1
0 0 0 1 2
0 0 1 0 3
-s
0 0 1 1 4
13,14,16,17,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
0 1 0 0 5
0 1 0 1 6
FAB REVISION 0 1 1 0 7
0 1 1 1 8
1 0 0 0 9
p
R9G9 R9G13 R9G10 R9G11 1 0 0 1 10
10K 10K 10K 10K 1 0 1 0 11
NO_STUFF NO_STUFF NO_STUFF 1 0 1 1 12
1 1 0 0 13
1 1 0 1 14
o
REV_FAB_ID3 1 1 1 0 15
REV_FAB_ID2 1 1 1 1 16
B B
t
REV_FAB_ID1
REV_FAB_ID0
BOARD REVISION Strapping Table
BOARD REVISION
p
R9G14 R9H4 R9G15 R9G16 BOARD ID
10K 10K 10K 10K 3 2 1 0
NO_STUFF
0 0 0 0 Capell Valley
0 0 0 1 Reserved
0 0 1 0 Reserved
la
0 0 1 1 TBD
0 1 0 0 TBD
0 1 0 1 TBD
.
0 1 1 0 TBD
0 1 1 1 TBD
13,14,16,17,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A 1 0 0 0 TBD
1 0 0 1 TBD
1 0 1 0 TBD
BOARD REVISION 1 0 1 1 TBD
w
1 1 0 0 TBD
1 1 0 1 TBD
R9H5 R9H6 R9V3 R9V4 1 1 1 0 TBD
10K 10K 10K 10K 1 1 1 1 TBD
NO_STUFF NO_STUFF NO_STUFF NO_STUFF
w
A BOARD_ID0 A
BOARD_ID1 Capell Valley Intel Confidential
BOARD_ID2
BOARD_ID3 Title
w
FWH and I/O Port Expander
R9H2 R9H3 R9V5 R9V6
10K 10K 10K 10K
A D15378 1.501
5 4 3 2 1
5 4 3 2 1
m
+V3.3 13,14,15,17,27,32,33,34,35,36,38,45,46,55,56 +V3.3_PCISLT3 26,55 -V12S
26,28,35,39,43,44,55,56,58 +V12S
+V5_PCISLT3 +V3.3A 13,14,16,17,24,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57
+V12S 26,28,35,39,43,44,55,56,58 26,27,35,38,47,54,55,56,58 +V5
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
+V5 26,27,35,38,47,54,55,56,58 +V3.3A 13,14,16,17,24,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57
5,10,17,18,19,20,26,39,41,43,44,45,47,51,52,54,55,56 +V5S B1 +V5S 5,10,17,18,19,20,26,39,41,43,44,45,47,51,52,54,55,56
TRST# A1
o
26,55 -V12S -12V
B2 TCK +12V A2
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S B3 +V3.3S
R9B3 0.002 +V5_PCISLT3 GND1 TMS A3
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
B4 TDO TDI A4
1% +V3.3_PCISLT3 B5
R8B2 +5V (1) +5V (7) A5
B1 -12V A1 B6 INTA# A6 INT_PIRQD# 15,16
c
0.002 NO_STUFF TRST# +5V (2)
B2 TCK +12V A2 15,16 INT_PIRQC# B7 INTB# INTC# A7 INT_PIRQF# 15,16,26
B3 GND1 A3 15,16,26 INT_PIRQG# B8 +5V (8) A8
D 1% B4 TDO
TMS SLT4_PRSNT1# INTD# D
TDI A4 B9 RSV3 A9
.
PRSNT1# PM_CLKRUN# 16,26,32,35,42
B5 +5V (1) C9B9 0.01uF
+5V (7) A5 C9C1 SLT4_PRSNT2#
B10 RSV1 +5V (9) A10
B6 +5V (2) INTA# A6 INT_PIRQC# 15,16 B11 PRSNT2# RSV4 A11 PCI_GATED_RST# 32
15,16 INT_PIRQD# B7 INTB# INTC# A7 INT_PIRQB# 15,16,26 B12 GND2 GND14 A12
B8 INTD# 0.01uF
15,16 INT_PIRQA#
0.01uF C8B9 SLT3_PRSNT1# +5V (8) A8 B13 GND3 GND15 A13
B9 PRSNT1# RSV3 A9 B14 A14
s
PM_CLKRUN# 16,26,32,35,42 16,32,35,42 INT_SERIRQ RSV2 3.3VAUX
B10 RSV1 +5V (9) A10 B15 GND4 RST# A15 PCI_RST# 15,26,32
39,41,43,44,45,47,51,52,54,55,56 +V5S 0.01uF C8C4 SLT3_PRSNT2# B11 PRSNT2# A11 B16
26,27,35,38,47,54,55,56,58 RSV4 PCI_GATED_RST# 32 31 CLK_PCI_PCISLOT4 CLK +5V (10) A16
B12 GND2 GND14 A12 B17 GND5 GNT# A17 PCI_GNT#3 15
+V5 R8B5 0.002 B13 GND3 R8B10
1% GND15 A13 0 NO_STUFF 15,16 PCI_REQ#3
B18 REQ# GND16 A18
B14 RSV2 3.3VAUX A14 B19 A19
it c
16,32,35,42 INT_SERIRQ PCIRST# +5V (3) PME# PCI_PME# 15,26,35
R8A4 B15 GND4 A15 B20
0.002 NO_STUFF RST# R8C1 0 PCI_RST# 15,26,32 15,26 PCI_AD31 AD31 AD30 A20 PCI_AD30 15,26
31 CLK_PCI_PCISLOT3 B16 CLK +5V (10) A16 15,26 PCI_AD29 B21 AD29 +3.3V (7) A21
B17 GND5 A17 S3_PCI_GNT#2 B22
1% GNT# GND6 AD28 A22 PCI_AD28 15,26
B18 REQ# GND16 A18 15,26 PCI_AD27 B23 AD27 AD26 A23 PCI_AD26 15,26
15,16 PCI_REQ#2
B19 +5V (3) PME# A19 PCI_PME# 15,26,35 15,26 PCI_AD25 B24 AD25 GND17 A24
15,26 PCI_AD31 B20 AD31 AD30 A20 PCI_AD30 15,26 B25 +3.3V (1) AD24 A25 SLT4_IDSEL PCI_AD24 15,26
15,26 PCI_AD29 B21 AD29 +3.3V (7) A21 15,26 PCI_C/BE#3 B26 C/BE3# IDSEL A26 PCI_AD19 15,26
B22 GND6 680
AD28 A22 PCI_AD28 15,26 15,26 PCI_AD23 B27 AD23 +3.3V (8) A27 R9C3
15,26 PCI_AD27 B23 AD27 AD26 A23 PCI_AD26 15,26 B28 GND8 AD22 A28 PCI_AD22 15,26
15,26 PCI_AD25 B24 AD25 GND17 A24 15,26 PCI_AD21 B29 AD21 AD20 A29 PCI_AD20 15,26
a
B25 +3.3V (1) AD24 A25 SLT3_IDSEL PCI_AD24 15,26 15,26 PCI_AD19 B30 AD19 GND18 A30
15,26 PCI_C/BE#3 B26 C/BE3# IDSEL A26 PCI_AD18 15,26 B31 +3.3V (2) AD18 A31 PCI_AD18 15,26
B27 AD23 R8C6 680
15,26 PCI_AD23 +3.3V (8) A27 15,26 PCI_AD17 B32 AD17 AD16 A32 PCI_AD16 15,26
Note: B28 GND8 AD22 A28 PCI_AD22 15,26 15,26 PCI_C/BE#2 B33 C/BE2# +3.3V (9) A33
To Power PCI Slot 3 in suspend, 15,26 PCI_AD21 B29 AD21 AD20 A29 PCI_AD20 15,26 B34 GND9 FRAME# A34 PCI_FRAME# 15,16,26
15,26 PCI_AD19 B30 AD19 GND18 A30 15,16,26 PCI_IRDY# B35 IRDY# GND19 A35
Stuff R8A4, R8B2, R8B10 B31 +3.3V (2) AD18 A31 PCI_AD18 15,26 B36 +3.3V (3) TRDY# A36 PCI_TRDY# 15,16,26
and Unstuff R9B3, R8B5, R8C1 15,26 PCI_AD17 B32 AD17 AD16 A32 PCI_AD16 15,26 15,16,26 PCI_DEVSEL# B37 DEVSEL# GND20 A37
B33 C/BE2# +3.3V (9) A33 B38 STOP# A38
m
15,26 PCI_C/BE#2 GND10 PCI_STOP# 15,16,26
B34 GND9 FRAME# A34 PCI_FRAME# 15,16,26 15,16,26 PCI_LOCK# B39 LOCK# +3.3V (10) A39
15,16,26 PCI_IRDY# B35 IRDY# GND19 A35 15,16,26 PCI_PERR# B40 PERR# SMBCLK A40 SMB_CLK_A1 14,26,28
B36 +3.3V (3) TRDY# A36 PCI_TRDY# 15,16,26 B41 +3.3V (4) SMBDAT A41 SMB_DATA_A1 14,26,28
15,16,26 PCI_DEVSEL# B37 DEVSEL# GND20 A37 15,16,26 PCI_SERR# B42 SERR# GND21 A42
B38 GND10 A38 PCI_STOP# 15,16,26 B43 PAR A43 PCI_PAR 15,26
C STOP# +3.3V (5) C
e
15,16,26 PCI_LOCK# B39 LOCK# +3.3V (10) A39 15,26 PCI_C/BE#1 B44 C/BE1# AD15 A44 PCI_AD15 15,26
15,16,26 PCI_PERR# B40 PERR# SMBCLK A40 SMB_CLK_A1 14,26,28 15,26 PCI_AD14 B45 AD14 +3.3V (11) A45
B41 +3.3V (4) SMBDAT A41 SMB_DATA_A1 14,26,28 B46 GND11 AD13 A46 PCI_AD13 15,26
15,16,26 PCI_SERR# B42 SERR# GND21 A42 15,26 PCI_AD12 B47 AD12 AD11 A47 PCI_AD11 15,26
B43 +3.3V (5) PAR A43 PCI_PAR 15,26 15,26 PCI_AD10 B48 AD10 GND22 A48
15,26 PCI_C/BE#1 B44 C/BE1# AD15 A44 PCI_AD15 15,26 B49 GND12 AD09 A49 PCI_AD9 15,26
h
15,26 PCI_AD14 B45 AD14 +3.3V (11) A45
B46 GND11 A46 KEY
AD13 PCI_AD13 15,26
15,26 PCI_AD12 B47 AD12 AD11 A47 PCI_AD11 15,26 15,26 PCI_AD8 B52 AD08 C/BE0# A52 PCI_C/BE#0 15,26
15,26 PCI_AD10 B48 AD10 GND22 A48 15,26 PCI_AD7 B53 AD07 +3.3V (12) A53
B49 GND12 AD09 A49 PCI_AD9 15,26 B54 +3.3V (6) AD06 A54 PCI_AD6 15,26
c
15,26 PCI_AD5 B55 AD05 AD04 A55 PCI_AD4 15,26
KEY
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 B56 A56
15,26 PCI_AD3 AD03 GND23
B52 AD08 +V3.3S
15,26 PCI_AD8 C/BE0# A52 PCI_C/BE#0 15,26 B57 GND13 AD02 A57 PCI_AD2 15,26
15,26 PCI_AD7 B53 AD07 +3.3V (12) A53 15,26 PCI_AD1 B58 AD01 AD00 A58 PCI_AD0 15,26
B54 +3.3V (6) AD06 A54 PCI_AD6 15,26 B59 +5V (4) +5V (11) A59
-s
15,26 PCI_AD5 B55 AD05 AD04 A55 PCI_AD4 15,26 16 PCI_ACK64# B60 ACK64# REQ64# A60 PCI_REQ64# 16
B56 AD03 +V3.3_PCISLT3
15,26 PCI_AD3 GND23 A56 B61 +5V (5) +5V (12) A61
B57 GND13 AD02 A57 PCI_AD2 15,26 B62 +5V (6) +5V (13) A62
B59 +5V (4) R8C4 J9B1 CON120_PCI
+5V (11) A59
16 PCI_ACK64# B60 ACK64# REQ64# A60 PCI_REQ64# 16 1K
R8C3
B61 +5V (5) +5V (12) A61 10K
SLOT4
B62 +5V (6) +5V (13) A62
V3.3S_PCI_D
p
J8B1 CON120_PCI PCI Slot 4 is farthest from processor
SLOT3
3
Slots 1&2&6 are on the 1 Q8C1
o
Extension Board to 2N3904
+V5_PCISLT3 Optimize routing 2
t
Place close to PCI Slot 3
B PCI_GNT#2 15 B
+V5S 5,10,17,18,19,20,26,39,41,43,44,45,47,51,52,54,55,56
C8N1 C8C5 C8C6 C8E4 C8B8
p
22uF 0.1uF 0.1uF 0.1uF 0.1uF C9N1 C9E4 C9E3 C9B7 C9B8 C9B10 C9C2 C9C3 C9E2
22uF 22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
+V3.3_PCISLT3
la
26,28,35,39,43,44,55,56,58 +V12S
C8C10 C9D3 C8C8 C8E1 C8D3 C8C7 C8D5

.
22uF 22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
C9B3 C8B4 C9B6
10uF 0.1uF 0.1uF C9D1 C9D4 C9D2 C9C4 C9C5 C9D5 C9E1
22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
ww 26,55 -V12S
C8B1
22uF
C9B4
0.1uF
C8B3
0.1uF
C9B5
0.1uF
Note:
Place one 0.1uF cap
next to each PCI Slot
and the Goldfinger A
w
Title
PCI Slot 3 & 4

D15378 1.501
5 4 3 2 1
5 4 3 2 1
o m
c
D D
.
25,55 -V12S
25,27,35,38,47,54,55,56,58 +V5 25,28,35,39,43,44,55,56,58 +V12S
s
+V3.3A 13,14,16,17,24,25,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57
5,10,17,18,19,20,25,39,41,43,44,45,47,51,52,54,55,56 +V5S
+V5S 5,10,17,18,19,20,25,39,41,43,44,45,47,51,52,54,55,56
S9C1
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S B1 A1 +V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
it c
-12V GND(TRST#)
B2 GND(TCK) +12V A2
B3 GND1 INT#(TMS) A3 INT_PIRQH# 15,16
B4 REQ#0(TDO) GNT#0(TDI) A4 PCI_GNT#0 15
15,16 PCI_REQ#0
B5 +5V_1 +5V_5 A5
B6 +5V_2 INTA# A6 INT_PIRQB# 15,16,25
15,16 INT_PIRQE# B7 INTB# INTC# A7 INT_PIRQG# 15,16,25
B8 A8 +V5S 5,10,17,18,19,20,25,39,41,43,44,45,47,51,52,54,55,56
15,16,25 INT_PIRQF# INTD# +5V_6
B9 REQ#1(PRSNT1#) RSV3 A9 PM_CLKRUN# 16,25,32,35,42
15,16 PCI_REQ#1
B10 RSV1 +5V(+V_I/O3) A10
B11 A11 PM_SLP_S4#_R R9C2 0
15 PCI_GNT#1 GNT#1(PRSNT2#) +5V(RSV4)
a
B12 GND2 GND13 A12
B13 A13 R9C1
GND3 GND14 0 NO_STUFF PM_SLP_S4# 16,32,35,46,55,56
B14 +3.3V(RSV2) 3.3Vaux A14
B15 GND4 RST# A15 PCI_RST# 15,25,32
31 CLK_PCI_PCIGOLDF B16 CLK +5V(+V_I/O4) A16
B17 GND5 GNT#5(GNT#) A17 PCI_GNT#5 15 Stuff R9C1and unstuff R9C2 if NOTE: Default is to use
B18 REQ#5(REQ#) GND15 A18 using ATX power supply pin A11 as a +V5S power
15,16 PCI_REQ#5
B19 +5V(+V_I/O1) PME# A19 PCI_PME# 15,25,35
B20 A20 directly on extension board. DO pin (R9C2 stuffed)
m
15,25 PCI_AD31 AD31 AD30 PCI_AD30 15,25
15,25 PCI_AD29 B21 AD29 +3.3V_11 A21 NOT STUFF BOTH R9C1 AND
B22 GND6 AD28 A22 PCI_AD28 15,25
B23 A23 R9C2 AT THE SAME TIME
15,25 PCI_AD27 AD27 AD26 PCI_AD26 15,25
15,25 PCI_AD25 B24 AD25 GND16 A24
B25 A25 PCI_AD24 15,25
C +3.3V_2 AD24 C
e
15,25 PCI_C/BE#3 B26 C/BE3# +3.3V(IDSEL) A26
15,25 PCI_AD23 B27 AD23 +3.3V_12 A27
B28 GND7 AD22 A28 PCI_AD22 15,25
15,25 PCI_AD19 B30 AD19 GND17 A30
B31 +3.3V_3 AD18 A31 PCI_AD18 15,25
h
15,25 PCI_C/BE#2 B33 C/BE2# +3.3V_13 A33
B34 GND8 FRAME# A34 PCI_FRAME# 15,16,25
15,16,25 PCI_IRDY# B35 IRDY# GND18 A35
B36 +3.3V_4 TRDY# A36 PCI_TRDY# 15,16,25
c
15,16,25 PCI_DEVSEL# B37 DEVSEL# GND19 A37
B38 GND9 STOP# A38 PCI_STOP# 15,16,25
15,16,25 PCI_LOCK# B39 LOCK# +3.3V_14 A39
15,16,25 PCI_PERR# B40 PERR# SMBCLK A40 SMB_CLK_A1 14,25,28
B41 +3.3V_5 SMBDAT A41 SMB_DATA_A1 14,25,28
-s
15,16,25 PCI_SERR# B42 SERR# GND20 A42
B43 +3.3V_6 PAR A43 PCI_PAR 15,25
15,25 PCI_C/BE#1 B44 C/BE1# AD15 A44 PCI_AD15 15,25
15,25 PCI_AD14 B45 AD14 +3.3V_15 A45
B46 GND10 AD13 A46 PCI_AD13 15,25
15,25 PCI_AD10 B48 AD10 GND21 A48
B49 GND11 AD09 A49 PCI_AD9 15,25
p
5V KEY
15,25 PCI_AD8 B52 AD08 C/BE0# A52 PCI_C/BE#0 15,25
15,25 PCI_AD7 B53 AD07 +3.3V_16 A53
B54 +3.3V_7 AD06 A54 PCI_AD6 15,25
B56 A56
o
15,25 PCI_AD3 AD03 GND22
B57 GND12 AD02 A57 PCI_AD2 15,25
t
B59 +5V(+V_I/O2) +5V(+V_I/O5) A59
B60 A60
B B61
+5V(ACK64#) +5V(REQ64#)
A61 B
+5V_3 +5V (7)
B62 +5V_4 +5V (8) A62
PCI_EXTENSION_GOLDFINGERS_5V
p
NO_STUFF
PCI - EDGE CONNECTOR

(GOLDFINGER)
. la
A
ww A
w
Title
PCI Edge Connector (Goldfinger)

D15378 1.501
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
it c
13,14,16,17,24,25,26,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
R8T1
10K
a
Layout Note: MDC Interposer Header
Place all series 13,14,16,17,24,25,26,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
resistors 0.6 to 2.6 25,26,35,38,47,54,55,56,58 +V5 +V1.5A_AZ_IO 47
U8E1 SC1563
inches from the ICH
5 IN
OUT 4
13,18,19,55,56 +VBATS C8E2 1 SHDN
m
1.0uF
SC1563_SHDN
13,14,15,17,25,32,33,34,35,36,38,45,46,55,56 +V3.3 GND ADJ R8T4 C8E3 C8T1
2.55K
2 3 1%
13,14,16,17,24,25,26,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A 22uF 0.1uF
C C
AZ_IO_ADJ
e
J8E1 17 +V3.3A/1.5A_AZ_IO
3
2X8_HDR_KEY12
R7F2 39 ACZ_MDC_BITCLK 16 15 Q8T1 R8T2 R8T3
14 ACZ_BITCLK R8F2 39 ACZ_MDC_RST# BSS138 100 10K
14 ACZ_RST# 14 13 1%
R8F3 39 ACZ_MDC_SYNC 12 11 1
h
14 ACZ_SYNC ACZ_MDC_SDO 49,54 VR_ALW_ENABLE
R8F1 39 10 9
14 ACZ_SDATAOUT
14 ACZ_SDATAIN0 8 7
2
14 ACZ_SDATAIN1 6
4 3
c
14 ACZ_SDATAIN2 2 1
ACZ_AUDIO_PWRDN_NET 1 2 ACZ_SPKR 16
3 4 13,14,16,17,24,25,26,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
5 6 +V1.5A_AZ_IO 47
-s
16 DOCK_AZ_RST# 7 8 DOCK_AZ_EN# 16
J8E2
8Pin HDR NO_STUFF Option to power
R8E5 R8D3 R8D4 Az I/O w/ 1.5
10K 0.002 1% 0.002 1% for LV signaling +V3.3A/1.5A_AZ_IO 17
Layout Note:
Place both headers
p
in-line and exactly
200 mils from
each other,
pin-to-pin. Draw
one silkscreen box 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
o
around both parts. +V1.5S 4,10,17,48,56,58
B B
t
NO_STUFF Option to power
R8F8 R8F10 Az I/O w/ 1.5S
0.002 1% 0.002 1% for LV signaling +V3.3S/1.5S_AZ_IO 17
la p
w .
w
A A
Title
w
AC'97-AZALIA

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
m
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
25,26,35,39,43,44,55,56,58 +V12S 25,26,35,39,43,44,55,56,58 +V12S
o
12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,5 +V3.3S
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 C7C3 C8B10 C8C1
13,14,16,17,24,25,26,27,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A J8C1 0.1uF 0.1uF
B1 A1 PRSNT#0 22uF 10% 10%
c
+12V1 PRSNT1#
B2 +12V2 +12V3 A2
D B3 RSVD1 +12V4 A3 D
.
B4 A4 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
GND1 GND6 R8B9
14,25,26 SMB_CLK_A1 B5 SMCLK JTAG2 A5
B6 A6 0
14,25,26 SMB_DATA_A1 SMDAT JTAG3
B7 GND2 JTAG4 A7
B8 A8
s
+3.3V1 JTAG5 C7B6 C7B5 C7C1
B9 JTAG +3.3V2 A9
,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,5 +V3.3S B10 A10 0.1uF 0.1uF
3.3Vaux +3.3V3 22uF 10% 10%
B11 WAKE# PWRGD A11 PLT_RST# 7,13,15,24,32,41,42,57
13,16,33 PCIE_WAKE#
Key
it c
B12 A12 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
R8C2 RSVD2 GND7
B13 GND3 REFCLK+ A13 CLK_PCIE_SLOT0 31
10K B14 A14
15 PCIE_TXP4_SLOT0 HSOp_0 REFCLK- CLK_PCIE_SLOT0# 31
15 PCIE_TXN4_SLOT0 B15 HSOn_0 GND8 A15
B16 GND4 HSLp_0 A16 PCIE_RXP4_SLOT0 15
B17 A17 C8D4 C8D7 C8D6
31 CLK_SLOT0_OE# PRSNT2# HSLn_0 PCIE_RXN4_SLOT0 15
B18 A18 0.1uF 0.1uF
GND5 GND9 22uF 10% 10%
PCIE_X1
a
25,26,35,39,43,44,55,56,58 +V12S
NOTE: SLOTS SLOT 0
0 AND 2 ARE
C8B5 C8B7 C8B6
PHYSICALY 0.1uF 0.1uF
22uF 10% 10%
IN-LINE
m
25,26,35,39,43,44,55,56,58 +V12S
25,26,35,39,43,44,55,56,58 +V12S 25,26,35,39,43,44,55,56,58 +V12S
C C7B4 C7B3 C7B2 C

3,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,5 +V3.3S +V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 0.1uF 0.1uF
e
J7C1 22uF 10% 10%
B1 +12V1 PRSNT1# A1 PRSNT#1
13,14,16,17,24,25,26,27,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A B2 A2
+12V2 +12V3 25,26,35,39,43,44,55,56,58 +V12S
B3 RSVD1 +12V4 A3
B4 A4 R7B16
h
GND1 GND6 0
B6 A6 C8C9 C8D1 C8D2
14,25,26 SMB_DATA_A1 SMDAT JTAG3
B7 A7 0.1uF 0.1uF
GND2 JTAG4 22uF 10% 10%
B8 +3.3V1 JTAG5 A8
c
B9 JTAG +3.3V2 A9
B10 3.3Vaux +3.3V3 A10
0,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,5 +V3.3S B11 A11
Key
-s
R7C1 B12 A12
10K RSVD2 GND7
B13 GND3 REFCLK+ A13 CLK_PCIE_SLOT1 31
B14 A14 13,14,16,17,24,25,26,27,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
31 CLK_SLOT1_OE# B17 PRSNT2# HSLn_0 A17 PCIE_RXN2_SLOT1 15
B18 A18 C8C3 C8C2
GND5 GND9 0.1uF
p
PCIE_X1 22uF 10%
SLOT 1 C7C2 C7B7
o
0.1uF
22uF 10%
B B
pt
C8D9 C8D8
0.1uF
22uF 10%
25,26,35,39,43,44,55,56,58 +V12S 25,26,35,39,43,44,55,56,58 +V12S
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
la
3,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,5 +V3.3S
J8D1
13,14,16,17,24,25,26,27,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A B1 A1 PRSNT#2
+12V1 PRSNT1#
B2 +12V2 +12V3 A2
.
B3 RSVD1 +12V4 A3
B4 A4 R7D3
GND1 GND6 0
14,25,26 SMB_DATA_A1 B6 SMDAT JTAG3 A6
B7 GND2 JTAG4 A7
B8 +3.3V1 JTAG5 A8
B9 A9
w
JTAG +3.3V2
B10 3.3Vaux +3.3V3 A10
30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,5 +V3.3S B11 A11
Key
B12 RSVD2 GND7 A12
R8D2 B13 A13
GND3 REFCLK+ CLK_PCIE_SLOT2 31
10K B14 A14
w
B17 A17
A 31 CLK_SLOT2_OE# PRSNT2# HSLn_0 PCIE_RXN3_SLOT2 15 A
B18 GND5 GND9 A18
PCIE_X1
Title
w
SLOT 2 PCIE

D15378 1.501
5 4 3 2 1
5 4 3 2 1
USBPWR_FPIO_FR USBPWR_HEADER_FR
m
J6H2 J7E2 NOTE: To enable SPI as the
1 2 1 2 boot BIOS destination, shunt
15 USB_PN4 3 4 USB_PN2 15 3 4 USB_PN6
5 6 5 6 15 pins 8 and 10. This will
15 USB_PP4 USB_PP2 15 USB_PP6
o
7 8 7 8 15 prevent use of Duck Bay FPIO
10 10 GNT5_SPI 15 header J7E2
USB_2X5-Header USB_2X5-Header
c
D D
s.
USB FPIO 2x5 Header +V5A 17,40,46,47,48,49,54,55,57 +V5A 17,40,46,47,48,49,54,55,57
J9A1 J7A1
1 BT_WAKE 1 BT_WAKE
it c
BT_ON BT_WAKE 32,35 BT_ON
2 C9A4 C9A3 2 C9A5 C9A7
BT_DETACH BT_ON 32,35 BT_DETACH
3 0.1uF 4.7uF 3 0.1uF 4.7uF
PCIE_SLOT0_CARD_ID#0 BT_DETACH 32,35 PCIE_SLOT1_CARD_ID#0
4 10% 4 10%
PCIE_SLOT0_CARD_ID#1 PCIE_SLOT0_CARD_ID#0 16 PCIE_SLOT1_CARD_ID#1 PCIE_SLOT1_CARD_ID#0 16
5 PCIE_SLOT0_CARD_ID#1 16 5 PCIE_SLOT1_CARD_ID#1 16
6 TP_DUCK_BAY_0 6 TP_DUCK_BAY_1
7 7
8 8
8Pin_HDR 8Pin_HDR
a
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
m
R9A2 R9A4 R7A1 R7A4
100K 100K 100K 100K
C C
e
PCIE_SLOT0_CARD_ID#0 PCIE_SLOT0_CARD_ID#1 PCIE_SLOT1_CARD_ID#0 PCIE_SLOT1_CARD_ID#1
h
R9A1 R9A3 R7A2 R7A5
10K 10K 10K 10K

s c
USB FPIO and Sideband header for PCIE Slot 0 and Slot 2 USB and Sideband header for PCIE Slot 1
p
+V3.3A 13,14,16,17,24,25,26,27,28,32,35,38,40,42,45,46,47,48,49,50,54,55,57
-
o
USB_OC#4 15
1
RP6Y1A RP6Y1B
t
10K 10K
B CARD ID Definition on Napa Platform B
CARD_ID#0 CARD_ID#1 CARD PRESENT
+V5A 17,40,46,47,48,49,54,55,57
8
-----------------------------------------------------------------------
p
U6J1 FB6J1
1 GND OC1# 8 50 OHM 0 0 Duck Bay 2
2 7 USBPWR_FPIO USBPWR_FPIO_FR
R6W6 1K EN1_C 3
IN OUT1
6
0 1 Upham II
EN1 OUT2
1
R6W5 1K EN2_C 4 5 C6H8 + C6H6 1 0 RSVD

EN2 OC2# USB_OC#2 15 220uF
C6Y1
la
TPS2052 470PF 10% 1 1 Empty
0.1uF
2
.
+V3.3A 13,14,16,17,24,25,26,27,28,32,35,38,40,42,45,46,47,48,49,50,54,55,57
w
USB_OC#6 15
3
RP6Y1C
10K
+V5A 17,40,46,47,48,49,54,55,57
6
U7E2 FB6E1
w
1 8 50 OHM
GND OC1# USBPWR_HEADER USBPWR_HEADER_FR
2 IN OUT1 7
R7T3 1K EN1_D 3 6
EN1 OUT2
1
R7T4 1K EN2_D 4 5 C7E3 + C7E4

C6T1 EN2 OC2# 220uF
0.1uF TPS2052 470PF 10%
A A
2
w
Title
RP6Y1D
USB FPIO and Sideband Header
4 5
10K
Decoupling caps for one Size Document Number Rev
USB port are already on D15378 1.501
the daughter card

5 4 3 2 1
5 4 3 2 1
FSA FSB FSC Host Clock

frequency
BSEL0 BSEL1 BSEL2
m
For Intel XDP (Stuff RP1D1 and
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
R1D1, NO_STUFF RP1E1 and R1T1)
VDD_A R5W1 2.2 VDD_SRC_CPU FB5H1 120ohm@100MHz For Arium XDP (NO_Stuff RP1D1 1 0 0 133
and R1D1, STUFF RP1E1 and R1T1)
o
C5W7 C5W1 C5H1 C5W6 C5W2 1 1 0 166
C5W3 C5W4 0.1uF 0.1uF 0.1uF 0.1uF
0.1uF 10% 10% 10% 10% 10uF
10% 10uF
CK410M
c
D VDD_PCI D
TSSOP56
.
VDD_48 R5W3 2.2 VDD_PCI FB5H2 120ohm@100MHz
C5W8 C5W5 C6W1 C6W2 C5V7

0.1uF 0.1uF 0.1uF
1
10% 10uF 10% 10% 10uF U6H1
VDD_SRC_CPU 21 11 VDD_48
VDD_PCI1
VDD_PCI0
VDD_SRC0 VDD_48
28 VDD_SRC1
VDD_REF R6W1 1 34 48 VDD_REF
VDD_SRC2 VDD_REF
it c
PCI_STOP# 55 PM_STPPCI# 16,35
C6G11 42 54
VDD_CPU CPU_STOP# PM_STPCPU# 16,35
0.1uF
10% VDD_A 37 41 CPU1 R5G17 33
VDD_A CPU1 CPU#1 CLK_MCH_BCLK 6
40 R5G18 33
CPU1# CLK_MCH_BCLK# 6
38 VSS_A
44 CPU0 R6G11 33
CPU0 CLK_CPU_BCLK 3
Y6H1 43 CPU#0 R5G16 33
XTAL_IN CPU0# CLK_CPU_BCLK# 3
1 2 50 XTAL_IN CLK_MCH_BCLK R5G9 49.9 1%
a
14.318MHZ XTAL_OUT 49 36 CPU2_ITP R5G19 33 CLK_MCH_BCLK# R5G10 49.9 1%
XTAL_OUT CPU_2_ITP/SRC_7 CPU2_ITP# CLK_XDP 37 CLK_CPU_BCLK
35 R5G20 33 R6G8 49.9 1%
FSA CPU2_ITP/SRC7# CLK_XDP# 37 CLK_CPU_BCLK#
R6H8 33 12 R5G8 49.9 1%
C6H4 C6H2 16 CLK_USB48 FSA/USB_48 CLK_XDP R5G11 49.9 1%
SRC6 33
33pF 33pF CLK_BSEL0 R5H31 2.2K 16 32 CLK_XDP# R5G12 49.9 1%
5% 5% CLK_BSEL1 5% FSB/TEST_MODE SRC6# CLK_PCIE_PEG R5G13 49.9 1%
CLK_BSEL2 53 31 SRC5 R5G21 33 CLK_PCIE_PEG# R5G14 49.9 1%
FSC/TEST_SEL SRC5 SRC5# CLK_PCIE_PEG 13 CLK_PCIE_ICH
m
30 R5G22 33 R5H29 49.9 1%
SRC5# CLK_PCIE_PEG# 13 CLK_PCIE_ICH#
5 R5H30 49.9 1%
PCI5 SRC4 R5H16 33
SRC4 26 CLK_PCIE_ICH 15
+V3.3S 4 27 SRC4# R5H17 33
PCI4 SRC4# CLK_PCIE_ICH# 15
C 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 CLK_PCIE_XDP_3GPLL R5H23 49.9 1% C
CLK_PCIE_XDP_3GPLL# R5H24 49.9 1%
e
3 PCI3 SRC3 24
R6H6 25 CLK_SRC_DB800 R5H21 49.9 1%
10K R6G10 33 PCI2 SRC3# CLK_SRC_DB800# R5H22 49.9 1%
56 PCI2
31 CLK_PCI SRC2 R5H12 33 DREFCLK R5H19 49.9 1%
SRC2 22 CLK_PCIE_DMI_LAI
R6H7 33 PCIF1 9 23 SRC2# R5H13 33 DREFCLK# R5H20 49.9 1%
31 CLK_PCIF PCIF1 SRC2# CLK_PCIE_DMI_LAI#
CLK_PCIE_DMI_LAI R5H25 49.9 1%
h
PCIF0/ITP_EN 8 19 SRC1 R5H18 33 CLK_PCIE_DMI_LAI# R5H26 49.9 1%
PCIF0/ITP_EN SRC1 SRC1# CLK_PCIE_XDP_3GPLL 37
20 R5H7 33
SRC1# CLK_PCIE_XDP_3GPLL# 37
14,31 SMB_CLK_S3 46 SCLOCK
17 SRC0 R5H10 33
SRC0 CLK_SRC_DB800 31
c
47 18 SRC0# R5H11 33
14,31 SMB_DATA_S3 SDATA SRC0# CLK_SRC_DB800# 31
IREF 39 IREF DOT96 R5H8 33
DOT96 14 DREFCLK 7
13 15 DOT96# R5H9 33
VSS_48 DOT96# DREFCLK# 7
-s
29 VSS_SRC
R5G15 45
475 VSS_CPU
2 VSS_PCI0 VTT_PWRGD#/PD 10 VR_PWRGD_CK410# 31
6 VSS_PCI1
51 VSS_REF REF 52 CLK_REF14 31
J6G2 CK-410M
1 XTAL_IN_D R6H1 0 XTAL_IN
p
NO_STUFF
5 3 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
2 4 R6W2 0 XTAL_OUT
NO_STUFF
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
FSB Frequency Select:
CK-SSCD
SMA CON NO_STUFF
o
R7D23 R7D14 R7D12 R7R11 SSCD_VDDA R7R7 1
B
TSSOP16 B
t
J1G2 -> 1 - 2 10K 10K 10K 10K
CPU NO_STUFF NO_STUFF NO_STUFF C7R5 C6D2 C6D5
J1G1 -> 1 - 2 0.1uF 0.1uF 22uF
DRIVEN J1F4 -> 1 - 2
U7D3
p
+V1.05S 3,4,6,9,10,14,17,37,45,48,53,56,58 1 16
31 CLK_SSCD_IN CLKIN VDDA
J1G2 -> 2 - 3 VDD 9
533 SSC_S3 2
J1G1 -> 2 - 3 SSC_S2 S3
3 S2
R1G1 J1F4 -> 2 - 3 SSC_S1 4 12 SS_CLKOUT R7D21 33
S1 CLKOUT SS_CLKOUT# DREFSSCLK 7
56 +V1.05S 3,4,6,9,10,14,17,37,45,48,53,56,58 FSB R7D24 33
la
CLKOUT# 11 DREFSSCLK# 7
Freq 14,31 SMB_CLK_S3 7 SCLOCK
J1G2 -> 2 - 3 8 14 SSCD_IREF
(MHz) 14,31 SMB_DATA_S3 SDATA IREF
667 13 R6D3 49.9 1%
J1G1 -> OPEN VSSIREF
BSEL0_PULLUP
R7D25 R7D22 R7D4 R7R10 5 10 R6D4 49.9 1%

31 VR_PWRGD_CK410# PWRDWN VSS
.
R1T4 R1T3 J1F4 -> 2 - 3 10K 10K 10K 10K 6 15
1K 1K REFOUT/SEL VSSA
J1G2 NO_STUFF REFOUT/SEL CK_SSCD R7R8
475 CK_SSCD Spread Select:
3 CPU_BSEL0 1
2 CLK_BSEL0 R1E5 1K CK_SSCD REF OUT SELECT S1 S2 S3 Spread
3 PIN 6 PULLED UP 100Mhz 0 0 0 -0.8%
MCH_BSEL0 7 PIN 6 PULLED down 96Mhz
R1T2 RP1E1A 8 1 0 0 0 1 -1.25%
w
CON3_HDR 1K NO_STUFF
0 1 0 -1.75%
R7R9 0
RP1D1A 0 1 1 -2.5%
8 1 0 XDP_BPM#1 3
37 XDP_OBS2 1 0 0 0.3%
J1G1 5 4 AGND_SSCD 1 0 1 0.5%
1 RP1D1D 0 1 1 0 0.8%
3 CPU_BSEL1 CLK_BSEL1
2 R1E6 1K
w
1 1 1 1.25%
3 MCH_BSEL1 7 5 4
RP1E1B 7 2 0 RP1E1D 0
CON3_HDR NO_STUFF NO_STUFF
A A
RP1D1B 7 2 0 Capell Valley Intel Confidential
37 XDP_OBS1 XDP_BPM#2 3
J1F4 Title
w
3 CPU_BSEL2 1
2 CLK_BSEL2 R1E4 1K CK-410M
3 MCH_BSEL2 7
RP1E1C 6 3 0
CON3_HDR NO_STUFF
J1F9 Size Document Number Rev
RP1D1C 3 0
1
2
37 XDP_OBS0
6 XDP_BPM#3 3,58 A D15378 1.501
3 NOTE: For PPV builds only:
CON3_HDR
NO_STUFF NO_STUFF J1F4, Stuff J1F9 Date: Wednesday, July 20, 2005 Sheet 30 of 60
5 4 3 2 1
5 4 3 2 1
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
m
C7C5 C7P17 C7R1 C7P16 C7R3 C7R2 CLK_XDP_CPU R7C4 49.9 1%
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF CLK_XDP_CPU# R7C5 49.9 1%
22uF U7D1 CLK_PCIE_SLOT0 R7D15 49.9 1%
R7P26 2 8 DIF0 R7D5 33 CLK_PCIE_SLOT0# R7D16 49.9 1%
VDD1 DIF0 CLK_PCIE_SLOT0 28
o
11 9 DIF#0 R7D6 33 CLK_PCIE_SLOT1 R7D17 49.9 1%
For DB800 rev 1 stuff R7P19 10K VDD2 DIF#0 CLK_PCIE_SLOT0# 28 CLK_PCIE_SLOT1#
19 6 R7D18 49.9 1%
VDD3 OE0# CLK_SLOT0_OE# 28 CLK_PCIE_SLOT2
For rev 2 stuff R7P21 31 R7D19 49.9 1%
C7R4 VDD4 DIF1 R7D7 33 CLK_PCIE_SLOT2# R7D20 49.9 1%
39 VDD5 DIF1 12 CLK_PCIE_SLOT1 28
0.1uF R7C11 1 +V3.3S_DB800_VDDA 48 13 DIF#1 R7D8 33 CLK_PCIE_LAN R6D32 49.9 1%
c
DB800_OEINV VDDA DIF#1 CLK_PCIE_SLOT1# 28 CLK_PCIE_LAN#
40 14 R6D33 49.9 1%
OE_INV OE1# CLK_SLOT1_OE# 28 CLK_PCIE_3GPLL
D C7P14 R7C6 49.9 1% D
DIF2 CLK_PCIE_3GPLL#
.
R7P21 0 4 16 R7D9 33 R7C7 49.9 1%
30 CLK_SRC_DB800 SRC_IN DIF2 DIF#2 CLK_PCIE_SLOT2 28
0.1uF 5 17 R7D10 33 CLK_PCIE_SATA R7C9 49.9 1%
30 CLK_SRC_DB800# SRC_IN# DIF#2 CLK_PCIE_SLOT2# 28 Place C7C4
15 CLK_PCIE_SATA# R7C10 49.9 1%
OE2# CLK_SLOT2_OE# 28
5 14,30 SMB_CLK_S3 23 SCLK near CPU
U7D2 24 20 +V3.3S
14,30 SMB_DATA_S3
s
INVERTER SDATA DIF3 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
DIF#3 21
2 4 R7P19 0 DB800_PD 26 7 OE3# R7C14 10K
30 VR_PWRGD_CK410# DB800_SRC_STOP PWRDWN OE3#
NO_STUFF 27 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
+V3.3S SRC_STOP DIF4 R7C20 33 CLK_XDP_CPU C7C4 +V3.3S
DIF4 30
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 45 29 DIF#4 R7C21 33 CLK_XDP_CPU# 1UF
it c
3 DB800_HIGH_BW# LOCK DIF#4 OE4 NO_STUFF
28 HIGH_BW# OE4# 43
DB800_SRC_DIV# 1 R7R1 10K
SRC_DIV# DIF5 R7C15 33
16 VR_PWRGD_CK410 DIF5 34 CLK_PCIE_3GPLL 7
R7C25 R7D13 R7P25 DB800_BYPASS#/PLL 22 33 DIF5# R7C16 33
BYPASS#/PLL DIF#5 CLK_PCIE_3GPLL# 7
10K 10K 10K 35
DB800_IREF OE5# CLK_MCH_OE#
NO_STUFF NO_STUFF 46 R7P29 10K R7P27 10K
IREF DIF6 R7C17 33
DIF6 38 CLK_PCIE_SATA 14
R7C13 3 37 DIF6# R7C18 33 NO_STUFF
GND1 DIF#6 CLK_PCIE_SATA# 14
475 10 36
GND2 OE6# CLK_PCIE_SATA_OE# 16
a
18 GND3
25 42 DIF7 R6D30 33
GND4 DIF7 DIF7# R6D31 CLK_PCIE_LAN 33
32 41 33 NOTE: To Enable clocks
GND5 DIF#7 CLK_PCIE_LAN# 33
47 GNDA OE7# 44 CLK_REQ#_LAN 33 for XDP Interposer,
R7C27 R7C24 R7R3 R7R4 DB800 STUFF R7P27, NO STUFF
10K 10K 10K R7P20 0 R7R1
10K NO_STUFF
m
AGND_DB800
NOTE:
C OE pull-ups are on clock C
destination pages
e
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
High Bandwidth
Ouput frequency = SRC_IN
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S C7P15 PLL Bypass mode
h
+V3.3S 0.1uF
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
U7C3
6 8 CLKOUT R7C19 33
VDD CLKOUT CLK3 CLK_REF_ICH 16
c
U7C2 5 R7C26 33
CLK3 CLK2 CLK_REF_SIO 42
1 24 1 2 R7C12 33
GND1 CLK CLK_PCIF 30 30 CLK_REF14 REF CLK2 CLK_REF_LPC 35
CLK1 3
2 23 4 7 CLK4 R7C22 33
VDD1 VDD6 GND CLK4 CLK_SSCD_IN 30
-s
3 22 ICS9112-16
1Y0 VDD5
4 21 PCIF_2Y0 R7P12 33
1Y1 2Y0 CLK_PCIF_ICH 15
5 20 PCIF_2Y1 R7P13 680
1Y2 2Y1
6 GND2 GND5 19
p
7 GND3 GND4 18
8 17 PCIF_2Y2 R7P14 33
1Y3 2Y2 CLK_PCIF_PORT80 41
9 16 PCIF_2Y3 R7P15 33
1Y4 2Y3 CLK_PCIF_FWH 24
o
10 15 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
VDD2 VDD4 +V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
B B
t
R7P16 10K PCIF_OE1_DIS 11 14
1G VDD3
R7P18 680 PCIF_2Y4 12 13 PCIF_OE2_EN R7P17 10K
2Y4 2G
CDCVF2310 C7P12 C7P10 C7P11 C7P8 C7P9 C7P13
p
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
10% 10% 10% 10% 10% 10%
U7C1
1 GND1 CLK 24 CLK_PCI 30 Decoupling caps for both
la
2 VDD1 VDD6 23 CDCVF2310 devices
R7P1 33 PCI_1Y0 3 22 +V3.3S

32 CLK_PCI_KBC 1Y0 VDD5 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
.
R7P2 33 PCI_1Y1 4 21 PCI_2Y0 R7P3 15 1%
25 CLK_PCI_PCISLOT3 1Y1 2Y0 CLK_PCI_SIODOCK 42
R7P4 33 PCI_1Y2 5 20 PCI_2Y1 R7P5 33
25 CLK_PCI_PCISLOT4 1Y2 2Y1 CLK_PCI_PCIGOLDF 26
6 19 C7P2 C7P4 C7P3 C7P5 C7P6 C7P7
GND2 GND5 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
7 18 10% 10% 10% 10% 10% 10%
w
GND3 GND4
R7P6 33 PCI_1Y3 8 17 PCI_2Y2 R7P7 33
35 CLK_PCI_LPC 1Y3 2Y2 CLK_PCI_XDP
9 16 PCI_2Y3 R7P8 33
1Y4 2Y3 CLK_PCI_SIO 42
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
+V3.3S 10 15
VDD2 VDD4 +V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
w
R7P9 10K PCI_OE1_EN 11 14
1G VDD3
R7P11 33 PCI_2Y4 12 13 PCI_OE2_EN R7P10 10K
A 35 CLK_PCI_TPM 2Y4 2G
Intel Confidential A
CDCVF2310 Capell Valley
Title
w
DB800M AND CK-SSCD

A D15378
1.501
5 4 3 2 1
5 4 3 2 1
Y8H1 KSC J8G1

1 2 NOTE: Shunt both J9J2 and
J9J6 as default and for 13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A Enable 1-2 (Default)
m
10MHZ external programming. Disable 2-3
C9H2 C9H1
18PF 18PF 13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
+V3.3A 13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57
o
+V3.3A 13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57 R9G8 R9G7 R9G5
13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57 VCL C9W3 C9W5 C9W1 C9W4 240 240 240
+V3.3A C9W2 C8H2 0.1uF 0.1uF 0.1uF 0.1uF
Boot Mode Programming Straps
2 LEDD2
2 LEDD3
2 LEDD1
R9G4 R9W7 R9G3 0.1uF NOTE: Place C9W2 22uF
Y8G2 10K 10K 10K P90-P92 needs to be at VCC for boot mode programming. They are
c
R8G13 10K 1 4
decoupling cap
INH# VDD already pulled up in the design. MD0, MD1 needs to be at Vss.
D NO_STUFF 2 GND OUT 3 close to VCL pin 13 D
INH#_TP System needs to supply +V3.3A to flash connector.
.
CR9G3 CR9G2 CR9G1
TP8G1 10MHZ +V3.3A 13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57 GREEN GREEN GREEN
NO_STUFF NO_STUFF
U9H1 Thermal Monitoring R2B5 R2B8
3LED_CAPS
1 33 KBC_GP_DATA 38 Enabled (Default) Non-stuffed Stuffed
s
J8G1 R9W9 R9W8 VCC1 PA7/KIN15#/PS2CD
3 LED_SCROLL 1
1
86 VCC3 PA6/KIN14/PS2CC 34 KBC_GP_CLK 38
1 0 0 Disabled Stuffed Non-stuffed
38 SMC_RST# VCL 13
2 VCL PA3/KIN11#/PS2AD 38 KBC_MOUSE_DATA 38
3 36 39 KBC_MOUSE_CLK 38
LED_NUM
SMC_MD0 SMC_MD1 VCC2 PA2/KIN10#/PS2AC
77
it c
CON3_HDR AVREF 13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
76 AVCC PA5/KIN13#/PS2BD 35 KBC_KB_DATA 38
PA4/KIN12#/PS2BC 37 KBC_KB_CLK 38
J9J2 J9J6 MD1 9 19 KBC_CAPSLOCK 1
+V3.3A 13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57 MD0 10 MD1 P95/IRQ14# KBC_SCROLLOCK Q9G3
MD0 P94/IRQ13# 20
21 KBC_NUMLOCK BSS138
J9J1 1-X P93/IRQ12# R2B5
2
140 X1
(Default) 141 78 KBC_SCANIN0 1 100K
R9H19 10K KBC_DISABLE# SMC_XTAL X2 P60/KIN0#/FTCI/TMIX KBC_SCANIN1 Q9G2 NO_STUFF
143 XTAL P61/KIN1#/FTOA 79
3
SMC_EXTAL 144 80 KBC_SCANIN2 BSS138
EXTAL P62/KIN2#/FTIA/TMIY FAN_ON 5,35
KBC_SCANIN3
2
a
P63/KIN3#/FTIB 81 FAN_ON
J9J1 SMC_RES# 8 82 KBC_SCANIN4
SMC_STBY# RES# P64/KIN4#/FTIC KBC_SCANIN5
12 STBY# P65/KIN5#/FTID 83 1
R9G17 100 NMI_R 11 84 KBC_SCANIN6 Q9G1 R2B8
38 SMC_INITCLK NMI P66/IRQ6#/KIN6#/FTOB
85 KBC_SCANIN7 BSS138
P67/IRQ7#/KIN7#/TMOX 100K
2
15 P51/TMOY KBC_SCANIN[7:0] 38
R9G2 0 ALL_SYS_PWRGD_R 16 96 KBC_SCANOUT15
16,35,48 ALL_SYS_PWRGD P50/EXEXCL P27/PW15
14 97 KBC_SCANOUT14
24,35,50 SMB_BS_CLK P52/EXIRQ6#/SCL0 P26/PW14
m
13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57 17 98 KBC_SCANOUT13
24,35,50 SMB_BS_DATA P97/IRQ15#/SDA0 P25/PW13
+V3.3A +V3.3A 18 99 KBC_SCANOUT12 13,14,15,17,25,27,33,34,35,36,38,45,46,55,56 +V3.3
35,50 BC_ACOK P96/0/EXCL P24/PW12
13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57 8.2K 22 100 KBC_SCANOUT11 +V3.3A 13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57
H8_P91_IRQ1#35,50 SMB_BS_ALRT# P92/IRQ0# P23/PW11
R9W1 23 101 KBC_SCANOUT10 R9W5 1.40K 1%
P91/IRQ1# P22/PW10 EMA_ALS_DATA 19,36
C R9J1 10K +V3.3A
35,54 SMC_ONOFF# 24 P90/IRQ2#/ADTRG# P21/PW9 102 KBC_SCANOUT9 R9W11 1.40K 1%
EMA_ALS_CLK 19,36 C
13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57 KBC_SCANOUT8
e
1 P20/PW8 103
2 VCORE_IN_R 68 104 KBC_SCANOUT7
35 SMC_LID ICORE_IN_R P70/EXIRQ0#/AN0 P17
3 69 105 KBC_SCANOUT6 R9A10
16,26,35,46,55,56 P71/EXIRQ1#/AN1 P16 10K
J9J5 SW9J2 R9H16 70 106 KBC_SCANOUT5
10K P73/EXIRQ3#/AN3 PM_SLP_S4# P72/EXIRQ2#/AN2 P15 5%
71 107 KBC_SCANOUT4 +V3.3A 13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57
SPDT_SLIDE 5% P73/EXIRQ3#/AN3 P14 KBC_SCANOUT3
72 108
h
35,54 ATX_DETECT# P74/EXIRQ4#/AN4 P13 BT_ON
73 109 KBC_SCANOUT2
29,35 BT_WAKE P75/EXIRQ5#/AN5 P12 29,35 BT_ON
74 110 KBC_SCANOUT1 R9W18 10K
35,50 BC_ICHG P76/AN6 P11 SMC_EXTSMI# 16,35,42,57
75 112 KBC_SCANOUT0 R9W19 10K
BT_ON 35,50 BC_IINP P77/AN7 P10 SMC_WAKE_SCI# 16,35
40 R9W3 1.40K 1%
PA1/KIN9# KBC_SCANOUT[15:0] 38 SMB_BS_DATA 24,35,50
c
41 121 R9W2 1.40K 1%
16,34,35 PM_LAN_ENABLE PA0/KIN8# P30/LAD0 LPC_AD0 14,24,35,41,42 SMB_BS_CLK 24,35,50
LID JUMPER & SWITCH 136 122 R9W17 10K
16,35 PM_PWRBTN# P40/TMCI0/TXD2/DSERIRQ P31/LAD1 LPC_AD1 14,24,35,41,42 NMI_GATE 38
137 123 R7M3 10K KBC_PROG_TX#
FAN_ON 35 IMVP_VR_ON P41/TMO0/RXD2/DCLKRUN# P32/LAD2 LPC_AD2 14,24,35,41,42
J9J5 1-X (Default) 2 P43/TMCI1 P33/LAD3 124 LPC_AD3 14,24,35,41,42
SW9J2 1-2 (Default) 3 P44/TMO1 P34/LFRAME# 125 LPC_FRAME# 14,24,35,41,42
-s
38 NMI_GATE PLT_RST_R R9H1 100 +V3.3S
16,35 PM_RSMRST# 4 P45/TMRI1 P35/LRESET# 126 BUF_PLT_RST# 15,33,35
R9G18 0 PM_THERM#_R5 127
5,16,35 PM_THRM# P46/PWX0 P36/LCLK CLK_PCI_KBC 31
6 128 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
35,54 SMC_SHUTDOWN P47/PWX1 P37/SERIRQ INT_SERIRQ 16,25,35,42
+V3.3A 13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57 115 131 R9W16 10K
14,16,35 H_RCIN# PB5/WUE5#/DLAD2 P82/CLKRUN# PM_CLKRUN# 16,25,26,35,42 SMC_RUNTIME_SCI# 16,35
4,25,26,27,28,29,30,31,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,5 +V3.3S 116 132
35 SMC_RSTGATE# PB4/WUE4#/DLAD3 P83/LPCPD# PM_SUS_STAT# 16,35,42,57
R9J4 10K 117 134
5,35 SMB_THRM_CLK PB3/WUE3#/DLFRAME# P85/IRQ4#/RXD1/IRRXD KBCPROG_RX# 45
R8H1 8.2K 118 135
5,35 SMB_THRM_DATA PB2/WUE2# P86/IRQ5#/SCK1/SCL1 EMA_ALS_CLK 19,36
p
SPDT_SLIDE 119 138 R5H5
35 VIRTUAL_BATTERY 16,35 SMC_RUNTIME_SCI# PB1/WUE1#/LSCI P42/EXIRQ7#/TMRI0/SCK2/SDA1 EMA_ALS_DATA 19,36 47 VRPWRGD_1_5A_R
1 SW9J1 120 0
16,35,42,57 SMC_EXTSMI# PB0/WUE0#/LSMI#
2 16,35 SMC_WAKE_SCI# 129 P80/PME# VSS1 7
J9J7 3 H_A20GATE_R 130 42 R9H13 0
P81/GA20 VSS2 49 5130_PWRGD RSMRST#_PWRGD 35
R9H9 0 95 1
14,35 H_A20GATE VSS3
o
35,50 BS_DISA# 113 PB7/WUE7#/DLAD0 VSS4 111
114 139 CR5W1 RSMRST#_PWRGD
16,35 PM_BATLOW# PB6/WUE6#/DLAD1 VSS5
67 BAT54
B AVSS B
t
19,45 KBC_PROG_TX# 133 P84/IRQ3#/TXD1/IRTXD
PC7/WUE15#/DLDRQ 87 BS_CHGB# 35,50
TP_KSC_RES0 3
142 RESO# PC6/WUE14#/LDRQ 88 BS_CHGA# 35,50 54 ATX_PWROK
VIRTUAL BATTERY JUMPER & SWITCH PC5/WUE13# 89 BS_CLR_LTCH# 35,50
RSMRST#_PWRGD 51 90 SMC_LID MODE TYPE MD0 MD1 MD2 NMI J9H1(p38) J9G3 (page38)
PG7/EXIRQ15#/EXSCLB PC4/WUE12# VIRTUAL_BATTERY
p
J9J7 1-X (Default) 45 SIO_VID6 52 PG6/EXIRQ14#/EXSDAB PC3/WUE11# 91
SW9J1 1-2 (Default) 45 SIO_VID5 53 PG5/EXIRQ13#/EXSCLA PC2/WUE10# 92 BT_DETACH 29,35 Run Mode 0 0 1 0 x Stuffed
54 93 TP_TV_DCON_MODE
45 SIO_VID4 PG4/EXIRQ12#/EXSDAA PC1/WUE9#
45 SIO_VID3 55 PG3/EXIRQ11#/EXTMIY PC0/WUE8# 94 SATA_DET#2 16,44 Program Boot Block 0 0 1 1 Stuffed Open
45 SIO_VID2 56 PG2/EXIRQ10#/EXTMIX
Program Flash 0 0 1 1 Stuffed x
la
45 SIO_VID1 57 PG1/EXIRQ9#/EXTMCI1 PD7/TIOCB2/TCLKD 59 BC_SHDN 35,50
13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A 58 60
45 SIO_VID0 PG0/EXIRQ8#/EXTMCI0 PD6/TIOCA2 BS_DISB# 35,50
PD5/TIOCB1/TCLKC 61 KSC_LPC_DOCK# 42
R9H8 10K TP_PF7 43 62
TP_PF6 PF7/EXPW15 PD4/TIOCA1 EMA_DISP_UP 36
R9W6 10K 44 63
PF6/EXPW14 PD3/TIOCD0/TCLKB EMA_DISP_DOWN 36
.
R9H10 10K TP_PF5 45 64
TP_PF4 PF5/EXPW13 PD2/TIOCC0/TCLKA EMA_DISP_SEL 36
R9W15 10K 46 65 +V3.3A 13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57
TP_PF3 PF4/EXPW12 PD1/TIOCB0 EMA_DISP_ESC 36
R9H11 10K 47 66 +V3.3A 13,14,16,17,24,25,26,27,28,29,35,38,40,42,45,46,47,48,49,50,54,55,57
TP_PF2 PF3/IRQ11#/EXTMOX PD0/TIOCA0 EMA_DISP_GESC 36
R9H12 10K 48
R9H7 10K TP_PF1 PF2/IRQ10# KBC_MDE R9F5 4.7K
49 PF1/IRQ9# MD2 25
50 26 KBC_FWE R9F2 4.7K
10,35,47,48,49,55,56 PM_SLP_S3# PF0/IRQ8# FWE TP_KBC_PE5 R9F7
27 4.7K NOTE: Stuff R9F1 for
w
R9H15 0 VCORE_IN_R ETRST# TP_KBC_PE4 R9F4 4.7K
VCORE_IN PE4/ETMS 28 write protect
NO_STUFF 29 TP_KBC_PE3 R9F6 4.7K
PE3/ETDO TP_KBC_PE2 R9F8 4.7K R9F1 J9J4
PE2/ETDI 30
31 TP_KBC_PE1 R9F9 4.7K 0 MD2 J9J4
PE1/ETCK TP_KBC_PE0 R9F10 4.7K NO_STUFF
PE0/LID3# 32 Normal Operation 1-X
C9H3 Advanced Single Chip Mode
0.1uF H8S/2104 1-2
w
10%
NO_STUFF LAYOUT NOTE: Bring R9F11
0
A test point to edge of NO_STUFF A
board Capell Valley Intel Confidential
Title
w
R9H14 0 ICORE_IN_R Q8H1 Q8H2
ICORE_IN
NO_STUFF 13,14,15,17,25,27,33,34,35,36,38,45,46,55,56+V3.3 BSS138
13,14,15,17,25,27,33,34,35,36,38,45,46,55,56 +V3.3
BSS138 H8 2104 KBC
3 2 PLT_RST# 7,13,15,24,28,41,42,57 3 2 PCI_RST# 15,25,26
C9H4
0.1uF R8W8 R8W10 Size Document Number Rev
10%
NO_STUFF 10K 10K A D15378 1.501
SMC_RSTGATE# SMC_RSTGATE#
1
13,33,36 PLT_GATED_RST# 25 PCI_GATED_RST# Date: Wednesday, July 20, 2005 Sheet 32 of 60

5 4 3 2 1
5 4 3 2 1
Tekoa EkronR
STUFF: STUFF:
TP8A1,TP8A2, TP8B2, TP8B5, TP8B4, TP8B3, TP8B1, J7A2, J7B1, J8A1, R8M5, R8M6, R8M9, R7A3, R7M4, R7B2, R7B3, R7B4, R7B5, R7B9, R7B8, R7B7, R7B6, R5M1, R5A5, R7M1, R8N1, R7A6, R7A22, R7M6,
R7M8, R7M9, R7M10, R7M11, R7M12, Q7M1
m
R8M10,R8M11, R8A1, R8M7, R7A14, R7A16, R7A18, R7A19, R7A20, R5A2, R8M1, R7B1, R8A2,
R7M2, R4M7, R5A6, R5B1, R7M7, C7A1,C8A1, C8M1, C8A2, C7M5, C7M4, C7M7, C7M11 NO_STUFF:
NO_STUFF: TP8A1,TP8A2, TP8B2, TP8B5, TP8B4, TP8B3, TP8B1, J7A2, J7B1, J8A1, R8M5, R8M6, R8M9, R8M10, R8M11, R8A1,
R7A3, R7M4, R7B2, R7B3, R7B4, R7B5, R7B9, R7B8, R7B7, R7B6, R5A3, R5M1, R5A5, R7M1, R8M7, R7A14, R7A16, R7A18, R7A19, R7A20, R5A2, R8M1, R7B1, R8A2, R7M2, R4M7, R5A6, R5B1, R7M7,
R8N1, R7A6, R7A22, R7M6, R7M8, R7M9, R7M10, R7M11, R7M12, Q7M1
o
C7A1,C8A1, C8M1, C8A2, C7M5, C7M4, C7M7, C7M11
R7A8 = 3.3K R7A8 = 200
R7A7, R7A10, R7A12, R7A13 = 49.9_1% R7A7, R7A10, R7A12, R7A13 = 54.9_1%
U8A2 = TEKOA = 82573E, IPN = C88180-003 U8A2 = EKRON-R = 82562GZ, IPN = C78326-001
J5A1 = 1000 BASE-T, IPN: A74307-003 J5A1 = 10/100 BASE-T, IPN: A74314-002
c
D Note:
+V3.3 13,14,15,17,25,27,32,34,35,36,38,45,46,55,56
D
.
LAN controller symbol pin-out naming convention is (Tekoa-EkronR). Ex: PER-NC. T Stuffed for Tekoa +V3.3 13,14,15,17,25,27,32,34,35,36,38,45,46,55,56
Stuffing option: T for Tekoa, and E for EkronR. E Stuffed for EkronR
+V2.5_LAN 34
s
Default: No_Stuff R8B8. It is for R8B8
3.3K R5A3
Tekoa’s Validation support only, NO_STUFF 0 C5A1
and will not be used on CRB. R5A2 T 0.01uF
T NO_STUFF 0
it c
U8A2A
F2 N11 LAN_SMBA# R7B1
15 PCIE_TXP1_LAN PE_R0p-NC SMB_ALRT#-NC SMB_ALERT# 16
F1 M11 0 J5A1A
15 PCIE_TXN1_LAN PE_R0n-NC SMB_DATA-NC SMB_DATA 14,16,58 VCC0
SMB_CLK-NC P11 SMB_CLK 14,16,58 9 VCC0
C8M11 0.1uF PCIE_RXP1_LAN_C D1
15 PCIE_RXP1_LAN PCIE_RXN1_LAN_C PE_T0p-NC
C8M7 C1 C13 LAN_MDI0P R6A4 0 LANMDI0P_R 10
15 PCIE_RXN1_LAN PE_T0n-NC MDI0p-TDP 0+
0.1uF C14 LAN_MDI0N R6A5 0 LANMDI0N_R 11
MDI0n-TDN LAN_MDI1P R6A8 0 LANMDI1P_R 0-
31 CLK_PCIE_LAN G1 PE_CLKp-NC MDI1p-RDP E13 12 1+
G2 E14 LAN_MDI1N R6A10 0 LANMDI1N_R 13
31 CLK_PCIE_LAN# PE_CLKn-NC MDI1n-RDN 1-
LAN_MDI2P R6A12 0 LANMDI2P_R
a
MDI2p-NC F13 14 2+
T LAN_THER_TESTP L3 F14 LAN_MDI2N R6A14 0 LANMDI2N_R 15
TP8A1 LAN_THER_TESTN THERMp-NC MDI2n-NC LAN_MDI3P R6A16 0 LANMDI3P_R 2-
TP8A2 L2 THERMn-NC MDI3p-NC H13 16 3+
T H14 LAN_MDI3N R6B1 0 LANMDI3N_R 17
E NO_STUFF J7A2 HS_DAS_TOUTB12 MDI3n-NC 3-
R7A3 649 1% RBIAS100 PHY_HSDACp-TOUT LINK_100_LED#
B13 PHY_HSDACn-RBIAS100 LED0#-SPDLED B11
R7M4 619 1% RBIAS10 B14 C11 LINK/ACT-ACT_LED# 19
NO_STUFF PHY_TSTPT-RBIAS10 LED1#-ACTLED LINK_1000-LINK_UP_LED# LED_LINK#
LED2#-LILED A12 20 LED_ACT
E
m
TP_LAN_SDP3 C7 21
TP_LAN_SDP2 SDP[3]-NC LAN_RXD2_R R7B2 E 0 NO_STUFF LED_100#
C8 SDP[2]-NC NC-LAN_RXD[2] M12 LAN_RXD2 14 22 LED_1000#
TP_LAN_SDP1 B8 N13 LAN_RXD1_R R7B4 E 0 NO_STUFF
SDP[1]-NC NC-LAN_RXD[1] LAN_RXD0_R E LAN_RXD1 14
TP_LAN_SDP0 A8 P13 R7B3 0 NO_STUFF
13,14,15,17,25,27,32,34,35,36,38,45,46,55,56 +V3.3 SDP[0]-NC NC-LAN_RXD[0] LAN_RXD0 14
C NC-LAN_RSTSYNC M13 LAN_RSTSYNC_R R7B5 E 0 NO_STUFF
LAN_RSTSYNC 14 18 GND0
C
e
SPI_SI A9 T RJ45 1000 WITH DUAL USB
SPI_SO NVM_SI-NC LAN_TXD2_R R7B9 E 0 NO_STUFF
B9 NVM_SO-NC CLK_VIEW-LAN_TXD[2] L14 LAN_TXD2 14
T SPI_CE# B10 J7B1 C5B1 Place this cap close
R8M6 SPI_SCLK NVM_CE#-NC LAN_TXD1_R R7B8 E 0 NO_STUFF 470pF
C9 NVM_SK-NC NC-LAN_TXD[1] L13 LAN_TXD1 14 to RJ45 connector.
3k 5%
h
LAN_XTAL1 K14 M14 LAN_TXD0_R R7B7 E 0 NO_STUFF
XTAL1-X1 NC-LAN_TXD[0] LAN_TXD0 14
LAN_XTAL2 J14 XTAL2-X2 LAN_JCLK_R R7B6 E 0 NO_STUFF
NC-LAN_CLK N14 LAN_JCLK 14 ACTIVITY LED
AUX_PRESENT C6
AUX_PRESENT-NC VLAN_PWRGD Green = LINK UP
c
R7B22 0
P10 P5 BLINKING = TX/RX ACTIVITY
13,16,28 PCIE_WAKE# PE_WAKE#-NC LAN_PWR_GOOD-NC LAN_PWRGD_IN R7B21 0 NO_STUFF
J8A1 NVM_TYPE PLT_GATED_RST# 13,32,36 C5A2
T A6 NVM_TYPE-NC PE_RST#-NC P7 BUF_PLT_RST# 15,32,35 Place Cap close to SPEED LED
Default is 1-X Protection Mode NVM_PROT A5 470pF
NVM_PROT-NC RJ45 connector. Off = Link 10 Mbps
-s
B4 N10 TP_ALT_CLK125 5%
Override NVM Protection 1-2 15 SPI_ARB NVM_SHRD NVM_REQ-NC ALT_CLK125-NC Green = Link 100 Mbps
D3 NVM_SHARED-NC
Orange = Link 1000 Mbps
NVM_TYPE DOCK_IND-NC C3 M9 TP_LAN_NC1 NO_STUFF
DOCK_IND-NC NC-NC1 TP_LAN_NC2 E
NC-NC2 N9
M7 TP_LAN_NC3 LINK_1000-LINK_UP_LED# R5M1 0 LINK_1000-LINK_UP_LED#_R
T R8M5 TP_LAN_TEST0 NC-NC3 TP_LAN_NC4 +V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
H1 TEST0-NC NC-NC4 L8
3.3K R8M9 TP_LAN_TEST1 H2 P14 TP_LAN_NC5 +V3.3 13,14,15,17,25,27,32,34,35,36,38,45,46,55,56
3.3K TP_LAN_TEST2 TEST1-NC NC-NC5 TP_LAN_NC6
p
T H3 J13 T R4M7 0 T
TP_LAN_TEST3 TEST2-NC NC-NC6 TP_LAN_NC7 R5A6 0
J1 TEST3-NC NC-NC7 M5
TP_LAN_TEST4 J2 D11 TP_LAN_NC8 R7B19
TP_LAN_TEST5 TEST4-NC NC-NC8 10K LINK/ACT-ACT_LED# R7M1 E 0 LINK/ACT-ACT_LED#_R
J3 TEST5-NC
TP_LAN_TEST6 K1
TP_LAN_TEST7 TEST6-NC TP_LAN_TEST16 LINK_100_LED# NO_STUFF
o
L1 TEST7-NC TEST16-NC A14 NO_STUFF
Install to use SPI NVM_SHRD TP_LAN_TEST8 M1 E3 TP_LAN_TEST15
TP_LAN_TEST9 TEST8-NC TEST15-NC
FLASH (Tekoa only) M3 TEST9-NC TEST14-NC P9 CLK_REQ#_LAN 31
B B
t
TP_LAN_TEST10 N2 M8 TP_LAN_TEST13 T
R8M10 TP_LAN_TEST11 TEST10-NC TEST13-NC TP_LAN_TEST12 LINK_1000-LINK_UP_LED# R5B1 0 LINK1000_PU_ALT
P1 TEST11-NC TEST12-NC N3
3.3K R7B20
Install when DUAL_LAN_TEKOA_EKR_REV 0.5 10K
T +V3.3 13,14,15,17,25,27,32,34,35,36,38,45,46,55,56
sharing SPI Flash E
p
with the ICH7 R5A5 0
NO_STUFF
R8A1,R8M7, and R8M11 LAN_MDI0P +V3.3 13,14,15,17,25,27,32,34,35,36,38,45,46,55,56
LAN_MDI0N
la
should be placed less
than 0.5" from the LAN_MDI1P
3
LAN_MDI1N C7M12 U7B11
SPI Flash LAN_XTAL1
VCC
.
LAN_MDI2P
15 SPI_CE# LAN_MDI2N VLAN_PWRGD
22pF 2
15 SPI_SCLK RST#
GND
15 SPI_SI LAN_MDI3P Y7A1
15 SPI_SO LAN_MDI3N
+V3.3 13,14,15,17,25,27,32,34,35,36,38,45,46,55,56 25MHZ MAX809
U8A1
1
w
SI_R R8M11 T 47 SPI_SI C7M14
1
8 VDD SI 5 SO_R R8A1 T 47 SPI_SO T T T T LAN_XTAL2
SO 2 SPI__CE# SPI_CE# R7A12 R7A13 R7A7 R7A10 R7A14 R7A16 R7A18 R7A19
R8M8 SPI_WP# 3 CE# 1 SCLK_R R8M7 T 47 SPI_SCLK 49.9 49.9 49.9 49.9 22pF
3.3K WP# SCK 6 49.9_1% 49.9_1% 49.9_1% 49.9_1% 1% 1% 1% 1%
R8M4 SPI_HOLD#7 4 LANMDI1_R LANMDIO_R LANMDI2_R LANMDI3_R
w
3.3K HOLD# VSS
SST SPI FLASH Skt
T T T T C7M7 C7M11
A C7A1 C8A1 C8M1 C8A2 R8M3 T T C7M4 T T A
33pF 33pF 33pF 33pF 10K 0.1uF 0.1uF Capell Valley Intel Confidential
5% 5% 5% 5% NO_STUFF C7M5 0.1uF
0.1uF Title
w
LAN (1 of 2)
For Tekoa, stuff R7A7,R7A10, Place termination resistors
These capacitors should be placed less R7A12, R7A13 with 49.9_1% and caps as close to LAN Size Document Number Rev
than 0.5" from the LAN Controller. controller as possible
For EkronR, stuff R7A7, R7A10, A D15378 1.501
NOTE: R8M3 is not needed when sharing R7A12, R7A13 with 54.9_1%
SPI flash with ICH7M and Tekoa
5 4 3 2 1
5 4 3 2 1
o m
13,14,15,17,25,27,32,33,35,36,38,45,46,55,56 +V3.3
+V1.2_LAN
R8N1
c
E 0.002
D 1% D
.
U8A2B NO_STUFF R8A2
A1 E1 T 0.002
VSS1-NC NC-VCC3.3-1
C2 VSS2-NC NC-VCC3.3-2 L4
D2 E11 1%
VSS3-NC NC-VCC3.3-3
G4 VSS4-NC NC-VCC3.3-4 E12
s
D4 VSS5-VSS
D5 VSS6-VSS VCC1.2-NC1 F12
B3 H12 C8M15 C8M13 C7M8
VSS7-VSS VCC1.2-NC2 10uF 0.01uF 0.01uF
E4 VSS8-VSS VCC1.2-NC3 G12
E5 C5
it c
VSS9-VSS VCC1.2-NC4
E10 VSS10-VSS VCC1.2-NC5 C4
F11 VSS11-VSS VCC1.2-NC6 A10
F10 VSS12-VSS
G11 VSS13-VSS
G10 VSS14-VSS VCC1.2-VCC3.3-1 G6
H10 VSS15-VSS VCC1.2-VCC3.3-2 H6
F5 H7 +VLAN_1.2-3.3
+V3.3 13,14,15,17,25,27,32,33,35,36,38,45,46,55,56 VSS16-VSS VCC1.2-VCC3.3-3
F4 VSS17-VSS VCC1.2-VCC3.3-4 J6
VCC1.2-VCC3.3-5 J7
a
VCC1.2-VCC3.3-6 J8
C10 K4 C8M17 C7M10
VSS-VSS1 VCC1.2-VCC3.3-7 0.01uF 0.01uF
D6 VSS-VSS2 VCC1.2-VCC3.3-8 K5
Q8A1 Requires C8M10 C8M6 D7 K7
4.7uF 0.1uF VSS-VSS3 VCC1.2-VCC3.3-9
Heat-Sink D8 VSS-VSS4 VCC1.2-VCC3.3-10 K8
10% 10% E6 L5
surface pad of VSS-VSS5 VCC1.2-VCC3.3-11
E7 VSS-VSS6 VCC1.2-VCC3.3-12 H8
+V2.5_LAN 33 E8 J9
1cm x 1cm min. VSS-VSS7 VCC1.2-VCC3.3-13
m
3 E9 VSS-VSS8 VCC1.2-VCC3.3-14 J10
F6 VSS-VSS9 VCC1.2-VCC3.3-15 J11
1 Q8A1 F7 K9
VSS-VSS10 VCC1.2-VCC3.3-16
PBSS5540Z F8 VSS-VSS11 VCC1.2-VCC3.3-17 K10
C C8M5 C8M9 C8M2 C8M3 F9 L9 +V3.3 13,14,15,17,25,27,32,33,35,36,38,45,46,55,56 C
10uF 10uF 0.1uF 0.1uF VSS-VSS12 VCC1.2-VCC3.3-18
e
G7 VSS-VSS13 VCC1.2-VCC3.3-19 L10
2 4 10% 10% G8 VSS-VSS14 VCC1.2-VCC3.3-20 K11
G9 K6 +V3.3 13,14,15,17,25,27,32,33,35,36,38,45,46,55,56
13,14,15,17,25,27,32,33,35,36,38,45,46,55,56 +V3.3 VSS-VSS15 VCC1.2-VCC3.3-21
H9 VSS-VSS16 VCC1.2-VCC3.3-22 H11
G14 K3 +V2.5_LAN 33
K2 G13
h
E2 VSS-VSS19
NOTE: STUFF R7A15, NOTE: Stuff N1 VSS-VSS20
T
R8M2 M10 R7A6 R7M2
R7A11, R7A17, and R7A9 R8M2 for 3.3K VCC3.3-NC1 E 0.002 0.002 +VLAN_2.5-3.3
VCC3.3-NC2 J4
for Full Power Down internal 2.5 on
c
P8 F3 1%
NO_STUFF VSS1-VSS VCC3.3-NC3 NO_STUFF 1%
Mode, 82562GX/GZ Tekoa C12 VSS2-VSS VCC3.3-NC4 D9
D13 VSS3-VSS IREG2.5_IN-NC5 A2
LAN DISABLE CIRCUIT N12 VSS4-VSS FUSEV-NC6 M2
Note: Default T C7M1 C7M2 C7M13
-s
Stuff for 82562 only, not R8M1 10uF 0.01uF 0.01uF
+V3.3 13,14,15,17,25,27,32,33,35,36,38,45,46,55,56 stuff R8M1 for 3.3K
for 82562 enhanced mode B7 NC1-VSS VCC2.5-VCC3.3-1 J5
external 2.5 on M6 G5
NC2-VSS VCC2.5-VCC3.3-2
Tekoa L6 NC3-VSS VCC2.5-VCC3.3-3 H5
K12 NC4-VSS VCC2.5-VCC3.3-4 K13
R7A22 L11 H4
13,14,15,17,25,27,32,33,35,36,38,45,46,55,56 +V3.3 E 470 NC5-VSS VCC2.5-NC1
VCC2.5-NC2 N7
NO_STUFF +V3.3 13,14,15,17,25,27,32,33,35,36,38,45,46,55,56
VCC2.5-NC3 M4
EN2.5_REG
p
TPs provide B5 EN2.5REG-NC VCC2.5-NC4 G3
LAN_PWR_CTRL2.5 A4 B6
access to CTRL_2.5-NC VCC2.5-NC5
LAN_ISOL
R7A23 T J12
VCC2.5-NC6
3
10K Q7M1 NO_STUFF Tekoa's JTAG L12 13,14,15,17,25,27,32,33,35,36,38,45,46,55,56 +V3.3

E NO_STUFF LAN_JTMS VCC2.5-NC7
signals. TP8B5 N4 JTAG_TMS-NC VCC2.5-VCC3.3 A11
E BSS138 R7A15 R7A11 R7A17 R7A9 LAN_JTCK
o
TP8B4 N5 JTAG_TCK-NC
R7M12 LAN_RST#_R
1 E 200 200 200 200 LAN_JTDI P4
16,32,35 PM_LAN_ENABLE E 5% 5% 5% 5% TP8B3 LAN_JTDO JTAG_TDI-NC
1K NO_STUFF P6 P2
B TP8B1 JTAG_TDO-NC VCC3.3-VCC3.3-1 B
t
NO_STUFF E NO_STUFF NO_STUFF N6 C8B2 C8M18 C8M4
E VCC3.3-VCC3.3-2 10uF 0.01uF 0.01uF
2
VCC3.3-VCC3.3-3 A7
R7M9 100 NO_STUFF LAN_TI_R D12 P12
R7M8 100 NO_STUFF LAN_TCK_R PHY_REF-ISOL_TI VCC3.3-VCC3.3-4
D14 NC-ISOL_TCK VCC3.3-VCC3.3-5 N8
R7M10 100 NO_STUFF LAN_EXEC_R D10 A3
LAN_ADV10 NC-ISOL_TXE IREG2.5_IN-VCC3.3
p
R7M6 100 NO_STUFF L7 DEVICE_OFF#-LAN_DIS# LAN_PWR_CTRL1.2
CTRL_1.2-NC P3
7,9,21,22,46,47,56,58 +V1.8
T LAN_TEST-TEST_EN A13 B2 33 +V2.5_LAN
R7A20 0 TEST_EN-TEST_EN 2.5V_OUT-NC1
2.5V_OUT-NC2 B1
T
la
R7M7 DUAL_LAN_TEKOA_EKR_REV 0.5 C8M12 C8M8
Note: Stuff R7M11 and Resistor Value: 1% 4.7uF 0.1uF
R7M11 R7A8 4.99k 10% 10%
Un-stuff R7A20 to disable E 1K
82573E = 3.3K 3.3K
.
Tekoa LAN Controller. 82562GZ = 200
NO_STUFF 3
+V1.2_LAN
NOTE: 1 Q8A2
TP8B2 PBSS5540Z
T Place near Q8A2 Requires
the TP's Heat-Sink
w
2 4 C8M14 C8M16 C8A3 C8A4
for JTAG surface pad of 4.7uF 10uF 0.1uF 0.1uF
signals 1cm x 1cm min. 10% 10% 10%
w
A A
Title
w
LAN (2 of 2)

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
m
+V5 25,26,27,38,47,54,55,56,58
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S TPM HEADER
J9A2
o
LPC SLOT 31 CLK_PCI_TPM 1
3
2
14,24,32,41,42 LPC_FRAME#
15,32,33 BUF_PLT_RST# 5 6
14,24,32,41,42 LPC_AD3 7 8 LPC_AD2 14,24,32,41,42
25,26,28,39,43,44,55,56,58 +V12S 13,14,16,17,24,25,26,27,28,29,32,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A 9 10
c
LPC_AD1 14,24,32,41,42
25,26,28,39,43,44,55,56,58 +V12S 11 12
14,24,32,41,42 LPC_AD0
D +V3.3 13,14,15,17,25,27,32,33,34,36,38,45,46,55,56
13,14 SMB_CLK_S4 13 14 SMB_DATA_S4 13,14 D
.
13,14,15,17,25,27,32,33,34,36,38,45,46,55,56 +V3.3 15 16 INT_SERIRQ 16,25,32,42
+V5 25,26,27,38,47,54,55,56,58 17 18 PM_CLKRUN# 16,25,26,32,42
17,24,25,26,27,28,29,32,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A J8F1 19 20
16,32,42,57 PM_SUS_STAT# TPM_DRQ#0 42
B1 +V12S_1 +12VS_2 A1
B2 A2 2x10-HDR_P4KEY
16,41 SUS_CLK
s
SUSCLK_32KHz NC(-12V)
B3 GND1 GND2 A3
29,32 BT_WAKE B4 BT_WAKE PM_DPRSLPVR A4 PM_DPRSLPVR 7,16,51
B5 +V3_3 +V3_1 A5
B6 NC3 NC1 A6
B7 A7 CAD NOTE:
it c
GND3 GND5 J3F2
15,24 FWH_WP# B8 FWH_WP# FWH_TBL# A8 FWH_TBL# 15,24
B9 NC4 BT_DETACH A9 BT_DETACH 29,32 7,16,51 PM_DPRSLPVR 1 2 H_DPRSTP# 3,14 Place close to TPM Header J9A2
B10 GND4 GND7 A10 3 4 H_DPSLP# 3,14
3,14 H_NMI
16,39 PATA_PWR_EN# B11 IDE_SPWR_EN# IDE_PATA_DET A11 IDE_PATADET 16,39 5 6 H_CPUSLP# 3,6
3,14,58 H_SMI#
B12 NC5 IDE_SATA_DET A12 7 8
3,14 H_PWRGD
B13 GND6 +V5_1 A13
B14 A14 8Pin HDR
+V3ALWAYS NC2 +V3.3A 13,14,16,17,24,25,26,27,28,29,32,38,40,42,45,46,47,48,49,50,54,55,57
B15 NC6 GND10 A15
14,16,32 H_RCIN# B16 CPU_RESET# SERIRQ A16 INT_SERIRQ 16,25,32,42
+V3.3S
a
14,32 H_A20GATE B17 KBC_A20_GATE CLKRUN# A17 PM_CLKRUN# 16,25,26,32,42
B18 A18 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
GND8 GND12 +V5 25,26,27,38,47,54,55,56,58
16,32,42,57 SMC_EXTSMI# B19 LSMI# NC7 A19 PM_RI# 16,42
NO_STUFF TP7E1
PM_STPCPU# 16,30
KEY NO_STUFF TP6H2
PM_STPPCI# 16,30
25,26,27,38,47,54,55,56,58 +V5 NO_STUFF TP6H1 C9A6 C9A2 C9A1
PM_CLKRUN# 16,25,26,32,42
B20 A20 NO_STUFF TP8F1 0.1uF 0.1uF 0.1uF
+V53 +V52 PCI_PME# 15,25,26
B21 A21 NO_STUFF TP8C1
42 LPC_DRQ#1 LDRQ1# LDRQ0# LPC_DRQ#0 42
m
14,24,32,41,42 LPC_FRAME# B22 LFRAME1# GND14 A22
B23 GND9 LAD3 A23 LPC_AD3 14,24,32,41,42
14,24,32,41,42 LPC_AD2 B24 LAD2 LAD1 A24 LPC_AD1 14,24,32,41,42
14,24,32,41,42 LPC_AD0 B25 LAD0 GND15 A25
C B26 GND11 LCLK A26 CLK_PCI_LPC 31 C
e
15,32,33 BUF_PLT_RST# B27 LRST# LPCPD# A27 PM_SUS_STAT# 16,32,42,57
B28 GND13 GND16 A28
31 CLK_REF_LPC B29 OSC_14MHz PME# A29 LPCS_PME# 42
B30 +V3_4 +V3_2 A30
60Pin_CardCon
h
+V5 25,26,27,38,47,54,55,56,58
c
13,14,15,17,25,27,32,33,34,36,38,45,46,55,56 +V3.3
C8F4
C8G1
0.1uF
CAD NOTE:
s
22uF Place close to LPC Slot J8F1
C8G3 C8G4 C8F1
C8F3 0.1uF 0.1uF 0.1uF
-
22uF
NOTE: SBH definintion pending
p
LPC SIDEBAND HEADER
o
B B
t
J9G2
16,32 PM_PWRBTN# 1 PM_PWRBTN# ALL_SYS_PWRGD 2 ALL_SYS_PWRGD 16,32,48
16,32 PM_RSMRST# 3 PM_RSMRST# IMVP_VR_ON 4 IMVP_VR_ON 32
5,16,32 PM_THRM# 5 PM_THRM# FAN_ON 6 FAN_ON 5,32
16,32 PM_BATLOW# 7 PM_BATLOW# BT_ON 8 BT_ON 29,32
p
10,32,47,48,49,55,56 PM_SLP_S3# 9 PM_SLP_S3# ATX_DETECT# 10 ATX_DETECT# 32,54
+V3.3A 13,14,16,17,24,25,26,27,28,29,32,38,40,42,45,46,47,48,49,50,54,55,57 11 12
16,26,32,46,55,56 PM_SLP_S4# PM_SLP_S4# BKLTSEL0# L_BKLTSEL0# 19,42
16,32,34 PM_LAN_ENABLE 13 PM_LAN_ENABLE BKLTSEL1# 14 L_BKLTSEL1# 19,42
15 GND1 GND3 16
16,32 SMC_RUNTIME_SCI# 17 SMC_RUNTIME_SCI# BC_IINP 18 BC_IINP 32,50
la
16,32 SMC_WAKE_SCI# 19 SMC_WAKE_SCI# BC_ICHG 20 BC_ICHG 32,50
32 SMC_RSTGATE# 21 SMC_RSTGATE# BC_ACOK 22 BC_ACOK 32,50
R9B7 R9B6 23 24
32,54 SMC_ONOFF# SMC_ONOFF# BC_SHDN BC_SHDN 32,50
1K 1K 25 26
32 SMC_LID SMC_LID GND4
32,54 SMC_SHUTDOWN 27 SMC_SHUTDOWN BS_CLR_LTCH 28 BS_CLR_LTCH# 32,50
.
U9N1 29 30
GND2 RSMRST#_PWRGD RSMRST#_PWRGD 32
3 A2 5,32 SMB_THRM_CLK 31 SMB_THRM_CLK BS_CHGA# 32 BS_CHGA# 32,50
PPV_EEPROM_A1 2 33 34
PPV_EEPROM_A0 A1 5,32 SMB_THRM_DATA SMB_THRM_DATA BS_CHGB# BS_CHGB# 32,50
1 A0 24,32,50 SMB_BS_CLK 35 SMB_BS_CLK BS_DISA# 36 BS_DISA# 32,50
24,32,50 SMB_BS_DATA 37 SMB_BS_DATA BS_DISB# 38 BS_DISB# 32,50
13,14 SMB_CLK_S4 6 SCL SDA 5 SMB_DATA_S4 13,14 32,50 SMB_BS_ALRT# 39 SMB_BS_ALRT# VIRTUAL_BATTERY 40 VIRTUAL_BATTERY 32
7
w
WP LPC Sideband Header - Napa
8 VCC GND 4
C9N2 AT24C02
0.1uF
w
A A
Title
w
LPC SLOT, TPM and FPH HEADERS

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
o m
c
D J7J2 D
.
+V3.3 13,14,15,17,25,27,32,33,34,35,38,45,46,55,56
VDD1 1
s
VDD2
Molex 52746_1090
2
RST# 3
SCL PLT_GATED_RST# 13,32,33
4 EMA_ALS_CLK 19,32
SDA 5
VSS EMA_ALS_DATA 19,32
6
it c
P_SAVE1 7 PSAVE1
VLCD1 8 VLCD1
P_SAVE2 9 PSAVE2 C7J9
VLCD2 10 VLCD2 1uF C7J13
C7J11 0.1uF
1uF
C7J10
A05477-005 0.1uF
C7J8
a
0.1uF
m
C C
e
+V3.3 13,14,15,17,25,27,32,33,34,35,38,45,46,55,56
h
R8V12
10K
c
EMA_DISP_UP 32
+V3.3 13,14,15,17,25,27,32,33,34,35,38,45,46,55,56
s
R8W4
J9G1 10K
-
6
5 EMA_DISP_DOWN 32
4 +V3.3 13,14,15,17,25,27,32,33,34,35,38,45,46,55,56
3
2
p
1
R8V7
6Pin_HDR 10K
o
EMA_DISP_SEL 32
+V3.3 13,14,15,17,25,27,32,33,34,35,38,45,46,55,56
B B
t
R8V8
10K
p
EMA_DISP_ESC 32
+V3.3 13,14,15,17,25,27,32,33,34,35,38,45,46,55,56
la
R8G10
10K
.
EMA_DISP_GESC 32
ww Capell Valley
Title
Intel Confidential
A
w
EMA

A D15378
1.501
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
it c
a
m
XDP
3 XDP_BPM#5 For Intel XDP (Stuff RP1D1 and
C J1E1 R1D1, NO_STUFF RP1E1 and R1T1) C
e
3 XDP_BPM#4
1 GND0 GND1 2 For Arium XDP (NO_Stuff RP1D1
3 OBSFN_A0 OBSFN_C0 4 XDP_OBS16 and R1D1, STUFF RP1E1 and R1T1)
5 OBSFN_A1 OBSFN_C1 6 XDP_OBS17
7 GND2 GND3 8
9 10
h
30 XDP_OBS0 OBSDATA_A0 OBSDATA_C0 XDP_OBS8
30 XDP_OBS1 11 OBSDATA_A1 OBSDATA_C1 12 XDP_OBS9
13 GND4 GND5 14
R1T1 0 15 16
30 XDP_OBS2 OBSDATA_A2 OBSDATA_C2 XDP_OBS10
NO_STUFF XDP_OBS3_R 17 18
XDP_OBS3 OBSDATA_A3 OBSDATA_C3 XDP_OBS11
c
19 GND6 GND7 20
R1D1 0 21 22
3 XDP_BPM#0 OBSFN_B0 OBSFN_D0
23 OBSFN_B1 OBSFN_D1 24
25 GND8 GND9 26
XDP_OBS4 27 OBSDATA_B0 OBSDATA_D0 28 XDP_OBS12
s
29 30 Layout note: R3T9 should
XDP_OBS5 OBSDATA_B1 OBSDATA_D1 XDP_OBS13
31 GND10 GND11 32 connect to H_CPURST# with
XDP_OBS6 33 OBSDATA_B2 OBSDATA_D2 34 XDP_OBS14 no stub.
-
3,4,6,9,10,14,17,30,45,48,53,56,58 +V1.05S 35 36
XDP_OBS7 OBSDATA_B3 OBSDATA_D3 XDP_OBS15
3 H_PWRGD_XDP 37 GND12 GND13 38
R1R2 54.9 1% 39 40 +V1.05S 3,4,6,9,10,14,17,30,45,48,53,56,58
PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_XDP 30
41 42 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,39,42,43,44,45,47,48,49,51,54,55,56,57,58
XDP_OBS20 HOOK1 ITPCLK#/HOOK5 CLK_XDP# 30
43 44 +V3.3S
VCC_OBS_AB VCC_OBS_CD RST_SNS1
p
45 46 R3T9 1K 1%
30 CLK_PCIE_XDP_3GPLL HOOK2 RESET#/HOOK6 H_CPURST# 3,6
47 48 R6Y1 1K 3,4,6,9,10,14,17,30,45,48,53,56,58 +V1.05S
30 CLK_PCIE_XDP_3GPLL# HOOK3 DBR#/HOOK7
49 GND14 GND15 50 XDP_DBRESET# 3,54,58
51 52 R1R1 54.9 1%
7,19 L_CLKCTLB SDA TDO
7,19 L_CLKCTLA 53 SCL TRSTn 54 XDP_TRST# 3
o
55 TCK1 TDI 56 XDP_TDI 3 XDP_TDO 3
57 58 C1R1 C1R2
3 XDP_TCK TCK0 TMS XDP_TMS 3
59 60 0.1uF 0.1uF
B GND16 GND17 B
t
CONN60_ITP-XDP
CAD NOTE: R2R5
p
54.9
Place the XDP connector on the 1%
primary side of the CRB and place
all components near the
connector.
. la
A
ww Capell Valley
Title
Intel Confidential
A
w
XDP

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
+V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,40,42,45,46,47,48,49,50,54,55,57
+V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,40,42,45,46,47,48,49,50,54,55,57
m
+V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,40,42,45,46,47,48,49,50,54,55,57
14 14 14 14 R9G12
+V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,40,42,45,46,47,48,49,50,54,55,57 100K
R9J2 J9G3
o
C9V1 1M SMC_INIT_CLK1 1 2 SMC_INIT_CLK2 3 4 SMC_INIT_CLK3 5 6 11 10 SMC_INITCLK_J
SMC_INITCLK 32
0.1uF U9G1A U9G1B C9G1 U9G1C U9G1E
3
U9V1 14 74HC04 74HC04 74HC04 74HC04
Q9J2 7 7 4.7uF 7 7
VCC
c
R9V2
BSS138 SMC_INITCLK#
D RST# 2 SMC_RST#_D 9 8 SMC_RST 1 SMC_INIT_CLK4 D
GND
.
4.7K U9G1D R9V1
3
74HC04 100K
2
MAX809 7 Q9W2 Boot Block
J9H1 1Hz Clock J9H1 NMI Jumper J9G3
1
Programming
s
BSS138
SMC_RST# 32 32 NMI_GATE 1 Disable Shunt NOTE: Shunt J9H1 for NORMAL SHUNT (DEFAULT)
Enable No Shunt (Default) SMC Programming
Program NO SHUNT
2
it c
+V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,40,42,45,46,47,48,49,50,54,55,57
Circuitry provides an interrupt to the SMC every 14
1s while in suspend (this allows the SMC to
complete housekeeping functions while R9F3 100 INVD2 13 12 TP_INVD2
suspended)
U9G1F
74HC04
a
7
Spare gates
m
C KBC_SCANOUT[15:0] 32
C
e
J9E1
KBC_SCANOUT1 2 1 KBC_SCANOUT0
h
KBC_SCANOUT15 KBC_SCANOUT14
c
13,14,15,17,25,27,32,33,34,35,36,45,46,55,56 +V3.3 16 15 +V3.3 13,14,15,17,25,27,32,33,34,35,36,45,46,55,56
18 17
20 19
22 21
KBC_SCANIN1 24 23 KBC_SCANIN0
-s
+V5 25,26,27,35,47,54,55,56,58 KBC_SCANIN7 30 29 KBC_SCANIN6
2x15-SHD-HDR
+V5 25,26,27,35,47,54,55,56,58
+V5 25,26,27,35,47,54,55,56,58 Scan Matrix Key Board
KBC_SCANIN[7:0] 32
p
F1B1
1
1.1A
3
RP1B1A 25,26,27,35,47,54,55,56,58 +V5

4.7K RP1B1C
4.7K
PS2_PWR_L +
FB1A2
o
CBTD has integrated
60ohm@100MHz FB1A4
8
diode for 5V to 3.3V

KBD_CLK 60ohm@100MHz
6
B voltage translation B
t
1 KBD_DATA C7B1
0.1uF
CP1B1A C7M15
47PF 47pF U7B1
8 FB1A6 5%
32 KBC_GP_DATA 3 1A1 VCC 24
p
31Ohm@100MHz +V5 25,26,27,35,47,54,55,56,58 4
32 KBC_GP_CLK 1A2
7 2 GP_DATA
32 KBC_MOUSE_DATA 1A3 1B1
+V5 25,26,27,35,47,54,55,56,58 8 5 GP_CLK
32 KBC_MOUSE_CLK 1A4 1B2
2
11 6 MOUSE_DATA
32 KBC_KB_DATA 1A5 1B3
RP1B1B 9 MOUSE_CLK
1B4
L_KBD_DATA
L_PS2_PWR 4.7K KBD_DATA
la
32 KBC_KB_CLK 14 2A1 1B5 10
17 2A2
4
FB1A5 18 15 KBD_CLK
2A3 2B1
L_KBD_CLK
RP1B1D 60ohm@100MHz
7
21 2A4 2B2 16
4.7K J1A1 GP_DATA 22 19
2A5 2B3
.
FB1A7 20
60ohm@100MHz 6 4 2 C1A6 2B4
2B5 23
GP_CLK 47pF OE#_PS2
5
5 1 1 1OE#
13 2OE# GND 12
+V5 25,26,27,35,47,54,55,56,58
13 3 SN74CBTD3384
2 14
CP1B1B R7A21
w
15 16
2
100
47PF 17 RP1B2B
7 10 4.7K
L_GP_CLK L_GP_DATA
12 8
L_MOUSE_CLK L_MOUSE_DATA MOUSE_DATA
7
11 7
w
9 4
+V5 25,26,27,35,47,54,55,56,58 60ohm@100MHz
DUAL_PS2 FB1A3 CP1B1D
47PF
A A
1
5
RP1B2A Capell Valley Intel Confidential
4.7K 25,26,27,35,47,54,55,56,58 +V5
FB1A8 Title
w
60ohm@100MHz
MOUSE_CLK PS2
8
3 RP1B2C 6 C1B1
3 4.7K C1A5
CP1B1C 4 RP1B2D 5 Spare 22uF 0.1uF
4.7K Size Document Number Rev
47PF
6 A D15378 1.501
5 4 3 2 1
5 4 3 2 1
o m
c
D D
.
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,42,43,44,45,47,48,49,51,54,55,56,57,58
J7J1
+V5S_PATA IDE_D_PRST#_R 1 2
s
14 IDE_PDD[15:0] IDE_PDD7 IDE_PDD8 IDE_PDD[15:0] 14
5,10,17,18,19,20,25,26,41,43,44,45,47,51,52,54,55,56 +V5S 3 4
IDE_PDD6 5 6 IDE_PDD9
IDE_PDD5 7 8 IDE_PDD10
R4J2 IDE_PDD4 IDE_PDD11
14
14
9 10
100K IDE_PDD3 11 12 IDE_PDD12
it c
U4H1A U4H1B R7J2 IDE_PDD2 13 14 IDE_PDD13
PATA_PWR_EN_2# 1 2 PATA_PWR_EN_2 3 4 IDE_D_PRST# IDE_D_PRST#_R R7W9 R7H2 IDE_PDD1 15 16 IDE_PDD14
8.2K 4.7K IDE_PDD0 17 18 IDE_PDD15
R4Y6 C4H7 74HC14 74HC14 47 19
1M 0.1uF 21 22
20% 14 IDE_PDDREQ
7
14 IDE_PDIOW# 23 24
25 26 R6J2
14 IDE_PDIOR#
27 28 IDE_PD_CSEL
14 IDE_PDIORDY
14 IDE_PDDACK# 29 30
31 32 470
3
14 INT_IRQ14
a
14 IDE_PDA1 33 34 IDE_PATADET 16,35
Q4H15 35 36
14 IDE_PDA0
BSS138 37 38 R6J1
PATA_PWR_EN#_J 1 14 IDE_PDCS1# 10K
39 40
14 IDE_PDACTIVE#
20x2-HDR
2
14 IDE_PDCS3#
m
14 IDE_PDA2
C C
5,10,17,18,19,20,25,26,41,43,44,45,47,51,52,54,55,56 +V5S
25,26,28,35,43,44,55,56,58 +V12S
h e
c
R4W7 C4W2
1M 1000pF
4
R4W6 10%
100K
-s
PATA_12V_EN_1 R4W9 PATA_12V_EN_2 3
1M Q4H13
3
SI3433DV
Q4H12
BSS138 +V12S_PATA
PATA_PWR_EN_1# 1
1
2
5
6
J4J2
2
p
C4J4 C4J2 + C4J3
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,42,43,44,45,47,48,49,51,54,55,56,57,58 +V5S 5,10,17,18,19,20,25,26,41,43,44,45,47,51,52,54,55,56 15uF 1 12V
0.1uF 0.1uF
2 GND1
C4J1
0.1uF C5J1 3
o
GND2
10% R5J6 1000pF
1M 10%
14
1 4 5V
U4H1C
t
R5J7
B PATA_PWR_EN_1# 5 6 PATA_5V_EN_1 PATA_5V_EN_2 2 4Pin_HD_PWR-CON B
R7J11 3 Q5J1A
10K 1M
74HC14 SI4925DY
p
7
4
3
Q5J1B
Q4H14
J7J3 BSS138 SI4925DY 7 8 +V5S_PATA
PATA_PWR_EN#_J 1
16,35 PATA_PWR_EN#
la
5 6
2
Hotswap Status J7J3

R7J12
Enabled Shunt (Default) 1M C4J6 C4J5 C4J7 + C5J2
.
Disabled No Shunt
0.1uF 0.1uF 22uF 100uF
w
+V5S 5,10,17,18,19,20,25,26,41,43,44,45,47,51,52,54,55,56
+V5S 5,10,17,18,19,20,25,26,41,43,44,45,47,51,52,54,55,56
R4Y3
w
100K
U4H1D
14
74HC14_SP9 9 8
A A
74HC14
w
7
Title
IDE
Spare 74HC14 Inverter
D15378 1.501
5 4 3 2 1
5 4 3 2 1
m
13,14,16,17,24,25,26,27,28,29,32,35,38,42,45,46,47,48,49,50,54,55,57 +V3.3A
USB_OC#0 15
2
RP3B1A RP3B1B
o
+V5A 17,29,46,47,48,49,54,55,57 U3B1 10K 10K FB3B3
50OHM
7
1 8
c
GND OC1# USBPWR_CONNA
2 IN OUT1 7
R3N1 1K EN1_A 3 6 USBPWR_CONNB
D C3N1 R3N2 1K EN2_A 4
EN1 OUT2
5 D
.
EN2 OC2# USB_OC#1 15
1
FB3B4 C3M1 + C3A2 C3M3 + C3A3
0.1uF TPS2052 50OHM 220uF 220uF
470PF 10% 470PF 10%
2
L3B2
s
15 USB_PN0 1 4
USBA-
2 3 USBA+
15 USB_PP0
Triple USB
1
90@100MHz
it c
CR3A5 CR3A6 Connector
J3A1
USBA_VCC
2
1 VCC1
2 TOP
P#0
3 P0
PORT
Clamping-Diode 4
L3B1 Clamping-Diode GND1 RP3B1D
1 4 USBB_VCC 5 13 4 5 Spare
15 USB_PN1 VCC2 MIDDLE GND4
USBB- 6 14
USBB+ P#1 GND5
a
15 USB_PP1 2 3 7 P1
PORT
GND6 15
8 16 10K
GND2 GND7
90@100MHz
1
USBC_VCC 9
CR3A3 CR3A4 VCC3 BOTTOM
10 P#2
11 P2
PORT
12 GND3
2
3_stack_USB
m
Clamping-Diode
L3B3 Clamping-Diode
15 USB_PN3 1 4
USBC-
C USBC+ C
e
15 USB_PP3 2 3
1
90@100MHz
CR3A1 CR3A2
h
2 Table: USB Port Routing Locations
2
Clamping-Diode
Clamping-Diode USB Port Location
c
13,14,16,17,24,25,26,27,28,29,32,35,38,42,45,46,47,48,49,50,54,55,57 +V3.3A
USB Port 0 Back of Chassis
USB_OC#3 15 USB Port 1 Back of Chassis
3
RP3B1C
USB Port 2 FPIO/Duckbay
s
USB Port 3 Back of Chassis
+V5A 17,29,46,47,48,49,54,55,57 U4M2 FB4A3 USB Port 4 FPIO/Duckbay
-
10K
50OHM USB Port 5 Back of Chassis
6
1 GND OC1# 8
2 7 USBPWR_CONNC
R4A4 1K EN1_B 3
IN OUT1
6 USB Port 6 FPIO/Duckbay
C4A4 R4A3 1K EN2_B EN1 OUT2
4 EN2 OC2# 5 USB Port 7 Back of Chassis
1
C3M2 + C4B2
p
0.1uF TPS2052 220uF
470PF 10%
2
t o
B B
p
13,14,16,17,24,25,26,27,28,29,32,35,38,42,45,46,47,48,49,50,54,55,57 +V3.3A
R4A1 R4A2
10K 10K
la
+V5A 17,29,46,47,48,49,54,55,57
USB_OC#5 15
U4A2 FB4A1
1 8 50OHM
.
GND OC1# USBPWR_CONND
2 IN OUT1 7
R4M5 1K EN1_E 3 6 USBPWR_CONNE
C4M5 R4M4 1K EN2_E EN1 OUT2
4 EN2 OC2# 5 USB_OC#7 15 RJ45 10/100 with Dual
1
C4A2 + C4A1
0.1uF TPS2052 220uF USB Connector
470PF 10%
J5A1B
2
w
L5A2 USBD_VCC 1 VCC1
1 4 USBD- 2
15 USB_PN5 P0#
USBD+ 3 P0
15 USB_PP5 2 3 4 GND1
FB4A2
90@100MHz 50OHM
1
USBE_VCC 5 VCC2
w
CR5A3 CR5A4 USBE- 6 P1#
1
C4A3 + C4A5 USBE+ 7

220uF P1
10% 8 GND2
470PF
2
RJ45 1000 WITH DUAL USB

2
Clamping-Diode
A Clamping-Diode A
L5A1
w
1 4 Capell Valley Intel Confidential
15 USB_PN7
15 USB_PP7 2 3 Title
90@100MHz USB 2.0
1
CR5A1 CR5A2
D15378
2
Clamping-Diode
1.501
Clamping-Diode
5 4 3 2 1
5 4 3 2 1
m
PORT 80-83 DISPLAY
o
5,10,17,18,19,20,25,26,39,43,44,45,47,51,52,54,55,56 +V5S One 0.1uf cap per Display Segment CR6A1 CR6A2
c
D LED_SEGA LED_SEGDP LED_SEGA LED_SEGDP D
LED_SEGB
1 A AN_DP 6
LED_SEGB
1 A AN_DP 6 PORT 80, 82
.
10 B 10 B
C6M1 C6M2 C6M4 C6M3 LED_SEGC 8 LED_SEGC 8
0.1uF 0.1uF 0.1uF 0.1uF LED_SEGD C LED_SEGD C
5 D CT_DP 7 5 D CT_DP 7
20% LED_SEGE 4 LED_SEGE 4
20% 20% 20% LED_SEGF E LED_SEGF E
2 2
s
LED_SEGG F LED_SEGG F
3 G CT_COM 9 3 G CT_COM 9
5,10,17,18,19,20,25,26,39,43,44,45,47,51,52,54,55,56 +V5S
RP6A1A
1 330 8 LED_SEGA 7-SEG-LED-DISPLAY 7-SEG-LED-DISPLAY
it c
RP6A1B
2 330 7 LED_SEGB
RP6A1C 330 LED_SEGC
3 6
LED_SEGD
High Nibble (Left) Low Nibble (Right)
RP6A1D
4 330 5
RP7A1A
1 330 8 LED_SEGE
RP7A1B
2 330 7 LED_SEGF
RP7A1C
3 330 6 LED_SEGG
RP7A1D
4 330 5 LED_SEGDP
CR6A3 CR6A4
LED_SEGA LED_SEGDP LED_SEGA LED_SEGDP

PORT 81, 83
a
1 A AN_DP 6 1 A AN_DP 6
LED_SEGB 10 LED_SEGB 10
LED_SEGC B LED_SEGC B
8 C 8 C
LED_SEGD 5 7 LED_SEGD 5 7
LED_SEGE D CT_DP LED_SEGE D CT_DP
4 E 4 E
7SEG_LED_CT1
LED_SEGF 2 LED_SEGF 2
LED_SEGG F LED_SEGG F
3 G CT_COM 9 3 G CT_COM 9
7SEG_LED_CT3
7-SEG-LED-DISPLAY 7-SEG-LED-DISPLAY
High Nibble (Left) Low Nibble (Right)
C C
7SEG_LED_CT4
7SEG_LED_CT2
h
3 3 3 3
1 Q6A3 1 Q6A1 1 Q6A4 1 Q6A2
c
2N3904 2N3904 2N3904 2N3904
2 2 2 2
LED_MUX_HI81 RP6A2A 1 150 8 LED_MUX_HI81_D
-s
LED_MUX_HI80 RP6A2B 2 150 7 LED_MUX_HI80_D
LED_MUX_LO81 RP6A2C 3 150 6 LED_MUX_LO81_D
LED_MUX_LO80 RP6A2D 4 150 5 LED_MUX_LO80_D
p
5,10,17,18,19,20,25,26,39,43,44,45,47,51,52,54,55,56 +V5S
C7R6
5,10,17,18,19,20,25,26,39,43,44,45,47,51,52,54,55,56 +V5S 0.1uF
o
20%
U7D5
B B
t
C7R10 C7H8 OE#_PORT80 1 8
0.1uF 10uF LPC_AD0_D 1OE# VCC OE#_PORT80
2 1A 2OE# 7
20% 20% 3 6
14,24,32,35,42 LPC_AD0 1B 2B LPC_AD1_D LPC_AD1 14,24,32,35,42
4 GND 2A 5
p
SN74CBTD3306
U7D10
LPC_FRAME# 14,24,32,35,42
9 VCC1 IO32 44
17 43 PORT82_EN# Port J7E1
VCC2 IO31 5,10,17,18,19,20,25,26,39,43,44,45,47,51,52,54,55,56 +V5S
la
29 VCC3 IO30 42 82 - 83 Shunt
41 35 J7E1
VCC4 IO29 80 - 81 No Shunt (Default) C7R8
IO28 34
33 PLD_PD R7T2 10K 0.1uF
IO27 20%
TDO/IO26 32
.
31 LED_MUX_HI81 U7D4
IO25 LED_MUX_LO81 OE#_PORT80
IO24 30 1 1OE# VCC 8
37 28 LED_MUX_HI80 LPC_AD2_D 2 7 OE#_PORT80
31 CLK_PCIF_PORT80 GCLK1 IO23 LED_MUX_LO80 1A 2OE#
7,13,15,24,28,32,42,57 PLT_RST# 39 GCLR# IO22 27 14,24,32,35,42 LPC_AD2 3 1B 2B 6 LPC_AD3 14,24,32,35,42
26 4 5 LPC_AD3_D
TCK/IO21 GND 2A
IO20 25
OE#_PORT80 38 23 SN74CBTD3306
w
OE1 IO19
40 OE2/GCLK2IO18 22
5,10,17,18,19,20,25,26,39,43,44,45,47,51,52,54,55,56 +V5S 21 LED_SEGA
R7T1 IO17 LED_SEGB
20
SUS_CLK_Q
100 IO16 LED_SEGC

IO15 19
R7T5 18 LED_SEGD
1K IO14 LED_SEGE
IO13 15
14 LED_SEGF
w
IO12 LED_SEGG
IO11 13
12 LED_SEGDP
IO10
11
A IO9 A
3
Q7E1 IO8 10
8 Capell Valley Intel Confidential
BSS138 IO7
TMS/IO6 7
LPC_AD3_D Title
w
16,35 SUS_CLK 1 IO5 6
4 5 LPC_AD2_D
16
GND1
GND2
IO4
IO3 3 LPC_AD1_D PORT 80-83
LPC_AD0_D
2
24 GND3 IO2 2
36 GND4 TDI/IO1 1
EPM7064STC Size Document Number Rev

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
m
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,43,44,45,47,48,49,51,54,55,56,57,58
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,43,44,45,47,48,49,51,54,55,56,57,58
o
+V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,38,40,45,46,47,48,49,50,54,55,57
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,43,44,45,47,48,49,51,54,55,56,57,58
c
R8T6 R8E4 C7T10 C7V17
D 10K 10K R8T5 0.1uF R7T9 0.1uF D
U7E4 SMSC PORT-SWITCH 10K 10K
.
5 VCC1 LAD(0) 64 LPC_AD0 14,24,32,35,41
5
17 2 U8F1
VCC2 LAD(1) LPC_AD1 14,24,32,35,41
5
31 4 U8E4 1
POWER & GROUND

VCC3 LAD(2) LPC_AD2 14,24,32,35,41 35 LPC_DRQ#0
42 LAD(3) 7 LPC_AD3 14,24,32,35,41 35 TPM_DRQ#0 1 4 ICH_DRQ#0 14
s
VCC4 AND_DRQ#0
60 VCC5 LFRAME 14 LPC_FRAME# 14,24,32,35,41 4 2
24 SIO_DRQ#0 2
LDRQ0 SIO_DRQ#1
LPC INTERFACE
48 12 74AHC1G08
VTR LDRQ1 SIO_RST# 74AHC1G08
3
PCI_RESET 22
C7T6 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
3
8 25
it c
0.1uF VSS1 LPCPD PM_SUS_STAT# 16,32,35,57
20 VSS2 CLKRUN 16 PM_CLKRUN# 16,25,26,32,35
29 VSS3 SER_IRQ 19 INT_SERIRQ 16,25,32,35
37 47 C7T7
VSS4 IO_PME PM_RI# 16,35
R7T7 45 21 R8E3 0.1uF
VSS5 PCI_CLK CLK_PCI_SIO 31 10K
8.2K 62 10
VSS6 LPC_CLK_33 CLK_PCI_SIODOCK 31
SIO_14M 23 CLK_REF_SIO 31
5
U8E3
45 RS232_EN 27 GPIO10 35 LPC_DRQ#1 1
45 IRDA_CIR_SLT 28 GPIO11 4 ICH_DRQ#1 14
D_LAD_0
a
16,32,35,57 SMC_EXTSMI# 30 GPIO12/IO_SMI# DLAD(0) 63 2
TP_SIO_GPIO13 32 1 D_LAD_1
LPCD_OPNREQ_OUT# GPIO13/IRQIN1 DLAD(1) D_LAD_2 74AHC1G08
33 GPIO14/IRQIN2 DLAD(2) 3
D_LAD_3
3
45 RS232_RI# 34 GPIO15 DLAD(3) 6
35 13 D_LFRAME
35 LPCS_PME# GPIO16 GENERAL PURPOSE I/O DLFRAME D_LDRQ1
57 LPCD_RI# 36 GPIO17 DLDRQ1 11
DOCKING LPC
38 15 D_CLKRUN
57 LPCD_PWRGD GPIO30 DCLKRUN D_SER_IRQ
INTERFACE
39 GPIO31 DSER_IRQ 18
19,35 L_BKLTSEL1# TP_GPIO32 D_CLK_33
m
40 GPIO32 DLPC_CLK_33 9
TP_GPIO33 41 26 D_CLK_14
GPIO33 DSIO_14M
57 LPCD_LPCPD# 43 GPIO34
57 LPCD_LPCRST# 44 GPIO35
C LPCD_PWREN# 46
GPIO36
C
e
61 GPIO37 RXD1 52 SER_SINA 45
19,35 L_BKLTSEL0#
TXD1 53 SER_SOUTA 45
DSR1 54 SER_DSRA# 45
CTS1 56 SER_CTSA# 45
RI1 58 SER_RIA# 45
IR
UART2
R9E2 49 59
h
UART1
45 IR_TXD IRTX2 DCD1 SER_DCDA# 45

100K
45 IR_RXD 50
51
IRRX2 RTS1#/SYSOPT0 55
57
SER_RTSA# 45 LPC HOT DOCKING
45 IR_MODE IRMODE/IRRX3 DTR1#/SYSOPT1 SER_DTRA# 45
13,14,16,17,24,25,26,27,28,29,32,35,38,40,45,46,47,48,49,50,54,55,57 +V3.3A J9E2
LPC47N207-JN_Follow-On SER_DTRA# D_LAD_0 1 2 D_LAD_2
SER_RTSA# D_LAD_1 D_LAD_3
c
3 4
57 LPCD_PWRGD 5 6 LPCD_PWREN#
R9G1 7 8
100K D_LFRAME D_LDRQ1 LPCD_PCI_PME# 57
9 10
57 LPCD_SMC_EXTSMI# 11 12 LPCD_PD# 57
-s
D_CLKRUN 13 14 D_SER_IRQ
32 KSC_LPC_DOCK# 15 16 LPCD_RST# 57
17 18
19 20 LPCD_OPNREQ#
21 22
D_CLK_33 23 24 D_CLK_14
2X12-HDR_SHRD
p
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,43,44,45,47,48,49,51,54,55,56,57,58
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,43,44,45,47,48,49,51,54,55,56,57,58
R7E6 10K SER_RTSA# R7E8 10K
C9F1
Base Address:
o
NO_STUFF
00 = 0x002E
B B
t
01 = 0x004E 0.1uF
10 = 0x162E R9F12
U9F1
R7E5 10K SER_DTRA# R7E7 10K 11 = 0x164E 100K
1 GND VCC 4
NO_STUFF Default:
11= 0x164E
p
LPCD_OPNREQ# 2 3 LPCD_OPNREQ_OUT#
IN OUT
MAX6816
. la
w
Default:
1-2
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,43,44,45,47,48,49,51,54,55,56,57,58
J7E3
1
w
7,13,15,24,28,32,41,57 PLT_RST# SIO_RST#
2
RST_PD 3
A C7E2 C7U1 C7U3 C7T8 C7T9 C7T5 CON3_HDR A
22UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R7F1 Capell Valley Intel Confidential
10K
Title
w
SIO

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
it c
a
Q6H2 +V3.3S_SATA_P0 J7H1
SI3433DV 14 SATA_TXP0 2 TX GND1 1
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,44,45,47,48,49,51,54,55,56,57,58 +V3.3S 6 3 4
m
14 SATA_TXN0 TX# GND4
4 5
2 C6J1 C6H9 5 7
C7H9 0.1uF 22uF 14 SATA_RXN0 RX# GND7
1 6 RX
5,10,17,18,19,20,25,26,39,41,44,45,47,51,52,54,55,56 +V5S R7H16 1000pF 14 SATA_RXP0
1M
C SATA_Signal_Plug C
e
3
R4W4 SATA_3.3V_EN0_1R7H17 SATA_3.3V_EN0_2
100K 1M
3
Q7H1
h
SATA_PWR_EN#0_5V
SATA Port 0,
1 BSS138
Cable Connect_Power
J6H3
c
1 V_3.3_1 GND_1 6
2 V_3.3_2 GND_2 7
5,10,17,18,19,20,25,26,39,41,44,45,47,51,52,54,55,56 +V5S
3 V_5_1 GND_3 8
C8W4 4 9
V_5_2 GND_4
-s
0.1uF
5 V_12_1 GND_5 10
R8J7 C8J2
1M 1000pF
14
1
U4H1E SATA_POWER_CONNECTOR
SATA_PWR_EN#0_5V 11 10 SATA_5V_EN0_1 R8J5 SATA_5V_EN0_2 2

3 Q8H3A
1M
p
74HC14
Q8H3B SI4925DY
4
7
SI4925DY 7 8
+V5S_SATA_P0
o
3
Q4H7
BSS138 5 6
t
16 SATA_PWR_EN#0 1
B C7J3 C7J4 C7J1 + C7H7 B
0.1uF 0.1uF
22uF 100uF
2
la p
25,26,28,35,39,44,55,56,58 +V12S
R6H4
.
1M C6H3
2
1000pF
Q6H1
SATA_12V_EN0_1 R6H2 SATA_12V_EN0_2 1 SI2307DS
1M
3
+V12S_SATA_P0
3
w
Q7H2
SATA_PWR_EN#0_5V 1 2N7002 C7J5 C7J2 + C8H1
15uF
0.1uF 0.1uF
2
w
A A
w
Title
SATA (1 of 2)

D15378 1.501
5 4 3 2 1
5 4 3 2 1
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,45,47,48,49,51,54,55,56,57,58
m
Hot plug implemented on Port 2 only
R9H20
43K
o
16,32 SATA_DET#2
J9J3
c
D SATA Device Status J9J3 D
.
Presence Shunt (Default)
Removed No Shunt
s
This jumper simulates the drive status. For proper function
of the hot plug, this jumper must be "No Shunt" when drive
is removed and "Shunt" after the drive is plugged in.
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,45,47,48,49,51,54,55,56,57,58
it c
Q9Y1 +V3.3S_SATA_P2
SI3433DV
6
4 5
5,10,17,18,19,20,25,26,39,41,43,45,47,51,52,54,55,56 +V5S 2 C8J8 C8J5
1
R8J6 C8Y1 0.1uF 22uF
R4W5 1M 1000pF
100K
3
SATA_3.3V_EN2_2 R8J4 SATA_3.3V_EN2_3
1M
a
3
SATA Port 2,
Q8J1
BSS138 Direct
1 Connect
J8J2
2
2 1
m
14 SATA_TXP2 TX GND_2m_S_1
14 SATA_TXN2 3 TX# GND_2m_S_4 4
5 RX# GND_2m_S_7 7
14 SATA_RXN2
6 RX
14 SATA_RXP2
8 11
C V_3.3_1 GND_1m_P_4 C
e
9 V_3.3_2 GND_2m_P_5 12
+V5S 5,10,17,18,19,20,25,26,39,41,43,45,47,51,52,54,55,56 R8J9 4.3 V_3.3_3_PC 10 13
V_3.3_3_PC GND_2m_P_6
R8Y3 1 V_5.0_7_PC 14 V_5.0_7_PC
15 V_5.0_8
16 V_5.0_9 GND_2m_P_10 17
h
R8J2 C8J1 TP_SATA_RESEV 18
1M 1000pF P_Reserve_11
14
1
U4H1F TP9H1 V_12_13_PC 20 19
NO_STUFF V_12_13_PC GND_1m_P_12
21 V_12_14
SATA_PWR_EN#2_5V 13 12 SATA_5V_EN2_1 R8J1 SATA_5V_EN2_2 2 R9Y2 22 V_12_15
c
1M Q8H4A 5.1
3 5%
74HC14 Serial ATA Recepticle
7 4 SI4925DY
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,45,47,48,49,51,54,55,56,57,58 Q8H4B
s
7 8 CAD Note: Place this
SI4925DY connector on the edge of
+V5S_SATA_P2
-
CRB for hot plug support
R5H43 5 6
10K
C8J10 C8J9 C8Y2 + C8J4
3
p
0.1uF 0.1uF 22uF 100uF
Q4H10
J5H2 BSS138
SATA_PWR_EN#2_J 1
16 SATA_PWR_EN#2
o
2
Hotswap Status J5H2

R5H44
t
Enabled Shunt (Default) 1M 25,26,28,35,39,43,55,56,58 +V12S
B Disabled No Shunt B
R9J5 C9J1
p
1M 1000pF
2
Q9J3
SATA_12V_EN2_1 R8J3 SATA_12V_EN2_2 1 SI2307DS
1M +V12S_SATA_P2
3
la
Q9J1
3
2N7002
SATA_PWR_EN#2_5V 1 C9J4 C9J3 + C9J2
15uF
0.1uF 0.1uF
.
2
+V12S is only for desktop type SATA devices
ww A
w
Title
SATA (2 of 2)

D15378 1.501
5 4 3 2 1
5 4 3 2 1
In Ckt H8 Programming J7A3 and J7A4
+V3.3 13,14,15,17,25,27,32,33,34,35,36,38,46,55,56 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,46,47,48,49,50,54,55,57 +V3.3A
Disable 1-2 (Default)
Enable 2-3 (In Ckt Programming)
RS-232 TRANSCEIVER
m
C6N7 C7M3
0.1uF C6B2 0.1uF C7M9
22UF +V3.3A 22UF J7A4
13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,46,47,48,49,50,54,55,57 U7A1 SERBUF_SOUTA# 1
o
C7A3 0.1uF C1+1 1 2 TX_OUT
26
C1+ VCC 16
U6B2 SER_TX_OUT 3
C1-3 3 2 V_C_2 C7M6 0.1uF
VCC
SERBUF_C1+ SERBUF_V+ R7M5 C1- V+ CON3_HDR
28 C1+ V+ 27
C6B1 C6B3 10K C7A4 0.1uF C2+4 4 6 V_C_6 C7A2 0.1uF
c
0.1uF 0.1uF C2+ V- J7A3
D SERBUF_C1- 24 C2-5 5 SERBUF_SINA# 1 D
C1- C2-
2 RX_IN
.
12 13 SER_KBCPROG_RX_IN SER_KBCPROG_RX_IN 3
42 RS232_RI# SERBUF_C2+ R1OUT R1IN
1 3 SERBUF_V- 9 8
C6N6 C2+ V- R2OUT R2IN SER_TX_OUT CON3_HDR
19,32 KBC_PROG_TX# 11 T1IN T1OUT 14
3
Q7C1 0.1uF C6B5 10 7
s
SERBUF_C2- 0.1uF T2IN T2OUT
2 C2- GND 15
SER_RIA 32 KBCPROG_RX# MAX3232_RS232_TRNCVR
1 20
19
R2OUTB
4 SERBUF_CTSA SERIAL PORT CONNECTOR
42 SER_CTSA# R1OUT R1IN SERBUF_RIA
BSS138 18 5
it c
42 SER_RIA# R2OUT R2IN SERBUF_SINA#
+V3.3 J2A2A
2
42 SER_SINA 17 R3OUT R3IN 6

13,14,15,17,25,27,32,33,34,35,36,38,46,55,56 16 7 SERBUF_DSRA 60OHM-100MHZ GND 5
42 SER_DSRA# R4OUT R4IN SERBUF_DCDA SERBUF_RIA SERPRT_RIA RI
42 SER_DCDA# 15 R5OUT R5IN 8 1 8 FB2A4A 9
SERBUF_DTRA 2 7 FB2A4B SERPRT_DTRA DTR 4
R6N8 14 9 SERBUF_DTRA SERBUF_CTSA 3 6 FB2A4C SERPRT_CTSA CTS 8
42 SER_DTRA# T1IN T1OUT SERBUF_SOUTA# TX_OUT SERPRT_TX_OUT TXD
1K 13 10 4 5 FB2A4D 3
42 SER_SOUTA T2IN T2OUT SERBUF_RTSA SERBUF_RTSA SERPRT_RTSA RTS
42 SER_RTSA# 12 T3IN T3OUT 11 1 8 FB2B1A 7
RX_IN 2 7 FB2B1B SERPRT_RX_IN RXD 2
SER_ON 23 SERBUF_DSRA 3 6 FB2B1C SERPRT_DSRA DSR 6
FORCEON SERBUF_DCDA SERPRT_DCDA DCD
5 FB2B1D
a
42 RS232_EN 22 FORCEOFF# 4 1
21 INVALID# GND 25
60OHM-100MHZ 2IN1
R7C2
1K MAX3243
IR
m
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,47,48,49,51,54,55,56,57,58
U4A1
R4M3 LED_A 1 9
LED_A MNT
C 5,10,17,18,19,20,25,26,39,41,43,44,47,51,52,54,55,56 +V5S 2.74 1% 2 NC
C
IRDA_TXD
e
3 TXD_IRDA
3 C4M3 + C4M2 + C4M4 4
6.8uF 6.8uF 42 IR_RXD RXD_IRDA
U1B3D 0.47uF 5
42 IR_MODE SD
6 VCC
R1P5 U1C1D_SPARE
10K 11 CIR_TXD 7
+ TXD_RC
13 8
h
GND
SIO VID VOLTAGE TRANSLATION 10 -
Spare R4M1 R4M2 HSDL-3003#007
10K 10K
LM339
12
c
-s
5,10,17,18,19,20,25,26,39,41,43,44,47,51,52,54,55,56 +V5S 5,10,17,18,19,20,25,26,39,41,43,44,47,51,52,54,55,56 +V5S
U4M1
3 3 42 IRDA_CIR_SLT 1 S Y0 6
U1B1A U1B1D 2 5
GND VCC
SIO_VID0 32 SIO_VID3 32 42 IR_TXD 3 A Y1 4
VID_COMP 5 VID_COMP 11
R1N12 + R1N13 +
2 SIO_VID0 13 SIO_VID3 NON-INV DMUX C4M1
VID_0_D 4 VID_3_D 10 0.1uF
51 VR_VID0 - 51 VR_VID3 -
p
1K 1K 10%
LM339 LM339
12 12
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,47,48,49,51,54,55,56,57,58 +V3.3S
o
R1N7 R1N10 R1N17 R1N21 R1N24 R1N26 R1P3
B B
t
330 330 330 330 330 330 330
5,10,17,18,19,20,25,26,39,41,43,44,47,51,52,54,55,56 +V5S 5,10,17,18,19,20,25,26,39,41,43,44,47,51,52,54,55,56 +V5S
LED_VID0
LED_VID1
LED_VID2
LED_VID3
LED_VID4
LED_VID5
LED_VID6
3 3
U1B1B U1B3A
p
VID_COMP SIO_VID1 32 VID_COMP SIO_VID4 32
7 + 5 +
R1N16 SIO_VID1 R1N28 SIO_VID4
1 2
VID_1_D 6 VID_4_D 4
2
1K 1K
la
LM339 LM339 R1N8 R1N11 R1N18 R1N22 R1N25 R1N27 R1P4
12 12 10K 10K 10K 10K 10K 10K 10K
CR1B1 CR1B2 CR1B3 CR1B4 CR1B5 CR1B6 CR1C1
GREEN GREEN GREEN GREEN GREEN GREEN GREEN
1
.
SIO_VID0
5,10,17,18,19,20,25,26,39,41,43,44,47,51,52,54,55,56 +V5S 5,10,17,18,19,20,25,26,39,41,43,44,47,51,52,54,55,56 +V5S
SIO_VID1
3 3
U1B1C U1B3B SIO_VID2
SIO_VID2 32 SIO_VID5 32
w
VID_COMP 9 VID_COMP 7 SIO_VID3
R1N19 + R1P8 +
14 SIO_VID2 1 SIO_VID5
VID_2_D 8 VID_5_D 6 SIO_VID4
1K 1K
SIO_VID5
LM339 LM339
12 12 SIO_VID6
w
+V5S 5,10,17,18,19,20,25,26,39,41,43,44,47,51,52,54,55,56
A A
5,10,17,18,19,20,25,26,39,41,43,44,47,51,52,54,55,56 +V5S Capell Valley Intel Confidential
+V1.05S 3,4,6,9,10,14,17,30,37,48,53,56,58
C1N1 C1N4 Title
w
3
0.1uF 0.1uF VID_COMP U1B3C
SIO_VID6 32
Legacy Support
VID_COMP 9
R1P7 +
R1P6 14 SIO_VID6
R1P2 VID_6_D 8
1K 1% 1K 1%
51 VR_VID6
1K
- Size Document Number Rev
CAD NOTE: C1P1
A D15378
Place near 0.1uF
12
LM339 1.501
U1B1 &
U1B3 Date: Wednesday, July 20, 2005 Sheet 45 of 60
5 4 3 2 1
5 4 3 2 1
m
13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,47,48,49,50,54,55,57 +V3.3A
R4N6 0
48,49,54,55 +VBATA
o
R5N2 AGND_DDR
1.8_VIN
17,29,40,47,48,49,54,55,57 +V5A 1K R5N1 1.8PWRGD
C5N1 C5B4 C5B2
0.002
c
10uF 10uF 10uF
D 1% 25V 25V 25V D
.
R5B7
10K DDR_DCS2P
DDR_DCS2N
5
6
7
8
DDR_SKIP2
Q5B1
DDR_HDR2 R5B2 0 DDR_HDR2_R 4 IRF7811A NO_STUFF
R5N6 TP5B1
0 7,9,21,22,34,47,56,58 +V1.8
1
2
3
it c
NO_STUFF
DDR_LX2 1 2
L5B1 1.0uH Vout = 1.8V
DDR_VSET2
Q5N1 C5B18 C5B13 C5C3 Iout = 10A
AGND_DDR
IRF7811A R5N3 R5B5 330uF 330uF 330uF
5
6
7
8
1
DDR_SLEW2 51.1_1% 1K 2.5V 2.5V 2.5V
CR5B1
DDR_LDR2 4 MBR0530 R5B3 R5B4 33.2K 1%
a
C5N3 121K2 1%
1
2
3
1
0.1uF
2
10% DDR_DCS2P C5B5 4700pF
16V 1%
DDR_DCS2N
C5B3 202286-393
0.1uF C5N2
m
+VBATA 48,49,54,55 10% 1000pF
33
32
31
30
29
28
27
26
25
AGND_DDR
EU4B1
16V
CS2P
CS2N
GNDA2
VSET2
SKIP2
SLEW2
PWRGD2
LX2
HDR2
+DDR_VREF
C R5B9 DDR_BST2 AGND_DDR
C
1K
e
R5N5 0 ON2 1 24 17,29,40,47,48,49,54,55,57 +V5A
16,26,32,35,55,56 PM_SLP_S4# ON2 BST2 1
2 23 R5M2
DDR_VIN SP1 GNDP2 CR4N1
3 VIN LDR2 22
4 OZ824 21 0.002 1% BAT54A
C5N5 +V5A 17,29,40,47,48,49,54,55,57 VREF VDDP2 DDR_BST_VDD
5 20 3
h
0.01uF DDR_VDDA GNDA1 DC-DC CONTROLLER VDDP1
6 VDDA LDR1 19
10% 7 18
0402 1.8PWRGD CE GNDP1 DDR_BST1
8 ON1 BST1 17
25V
PWRGD1
+VBATA48,49,54,55 2
DDR2 VREG
c
R4B8
SLEW1
VSET1
SKIP1
HDR1
CS1N
AGND_DDR AGND_DDR
0.9_VIN
CS1P
10 R4N4 C4B1
LX1
1uF
0.0021% 10%
C4N1 8 7
10
11
12
13
14
15
16
-s
10uF
9
C4N6 25V
1uF C4B3 Vout = 0.9V
10% 0.1uF
Q4B1A 10%
Iout = 2A
DDR_HDR1 R4B1 DDR_HDR1_R
0 2 Si4966DY
AGND_DDR
16V NO_STUFF +V0.9 23,56,58
TP4B1
p
L4B1 2.2uH
DDR_VSET1 DDR_LX1 1
1 2
6 5
DDR_DCS1P C4B10 C4B5 C4C19 C4C5
DDR_DCS1N
17,29,40,47,48,49,54,55,57 +V5A R4B6 150uF 150uF 150uF 150uF
o
1
51.1_1% 6.3V, 3Arms 6.3V, 3Arms NO_STUFF NO_STUFF
Q4B1B CR4B1 6.3V, 3Arms 6.3V, 3Arms
B B
t
DDR_LDR1 4 Si4966DY
R4B5 MBR0530
0 R4B3 100K R4N2 60.4k_1% R4B18
NO_STUFF 1% 1K
2
3 DDR_DCS1P C4N3 3300pF
DDR_SKIP1
p
DDR_DCS1N
13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,47,48,49,50,54,55,57 +V3.3A
R4N5 DDR_SLEW1 C4N2
10K 1000pF
C4N4
la
0.047UF
16V
AGND_DDR
R4N1
13,14,15,17,25,27,32,33,34,35,36,38,45,55,56 +V3.3
1K C5B6
.
AGND_DDR +V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,47,48,49,50,54,55,57
AGND_DDR
0.1uF
C5B7 0.1uF 16V
10%
5
10V U5N1
5
U5B1 1
0.9PWRGD 47,49 PM_SYS_PWRGD
1 4 PM_PWROK 48
w
4 DDRVR_PWRGD 2
1.8PWRGD 2
74AHC1G08
+DDR_VREF 74AHC1G08
3
7,9,21,22,34,47,56,58 +V1.8
3
w
R4B4 R5B8 R5N7 0
10K 100K NO_STUFF
A 1% 1% A
DDR_VSET1 C4B4 DDR_VSET2 Title
w
1uF R5B6 0
10% NO_STUFF DDR_EVMC_V_CNTL 58 DDR VR (1 of 2)
R4N3 C4N5 R5N4 C5N6
10K 0.01uF 255K 0.01uF
1% 1%
10% 10%
0402 0402 Size Document Number Rev
25V
25V
A D15378 1.501
AGND_DDR

5 4 3 2 1
5 4 3 2 1
13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,48,49,50,54,55,57 +V3.3A
m
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,48,49,51,54,55,56,57,58 +V3.3S
27 +V1.5A_AZ_IO
10,56 +V3.3S_TVDAC
5,10,17,18,19,20,25,26,39,41,43,44,45,51,52,54,55,56 +V5S 17,29,40,46,48,49,54,55,57 +V5A
o
R5H6
R4H3 100K
1K 1%
1%
R5H3 R5V14
24.9K 13K
c
1% 1%
PM_SYS_PWRGD 46,49 10
D VDD+ R6A2 D
.
U5H1 10K
1 OutB OutC 16 2 - U6A1A
32 VRPWRGD_1_5A_R TP5G1 R5H1
2 OutA OutD 15
3 14 PP_HYST NO_STUFF 13K TLV2463 1
V+ Hyst +V2.5S_PWRGD PM_SLP_S3# 10,32,35,48,49,55,56
4 13 1% 5 OPAMP4_SHTDN#
s
+V5S_PWRGD InA- InD+
5 InA+ InD- 12 16 PM_SLP_S3#_UNBUF 3 +
6 11 +V3.3S_PWRGD
+V1.5A_PWRGD InB- InC+
7 InB+ InC- 10
8 9 GND
C5H2 Ref V- R4H1 4
it c
R4H2 R4H4 LTC1444 R5V15 10K
10K 10K 0.1uF 10K 1%
1% 1% PP_REFIN 1%
R5H4
VREF = 1.221V 10K
R5H2
2.4M
a
m
17,29,40,46,48,49,54,55,57 +V5A
25,26,27,35,38,54,55,56,58 +V5
C C
e
C6M6
0.1uF R6M7
7,9,21,22,34,46,56,58 +V1.8 10K
10
VDD+ NO_STUFF
h
R6M3 8 U6A1B
10K - NO_STUFF
1% TLV2463 VREF_MCH_MARG R5A1 0
9
c
6 OPAMP3_SHTDN#
58 M_VREF_MCH_A 7 +
R6A7
R6A3 GND 10K
s
10K C6M5 4
1% 220pF
25,26,27,35,38,54,55,56,58 +V5 10%
-
25,26,27,35,38,54,55,56,58 +V5
p
R6M1 0
M_VREF_MCH 7,58
R6A11
10K
7,9,21,22,34,46,56,58 +V1.8 NO_STUFF
10
VDD+
o
R6M2 2 U6A3A
B - B
t
10K
1% TLV2463 VREF_DIMM1_MARG R6M5 0
1
5 OPAMP2_SHTDN# NO_STUFF
58 M_VREF_DIMM_B 3 +
p
R6M6
R6A6 C6A1 GND 10K
10K 220pF 4
1% 10%
la
25,26,27,35,38,54,55,56,58 +V5
25,26,27,35,38,54,55,56,58 +V5
.
C6M8 R6B2 R6N10 0
0.1uF M_VREF_DIMM1 22,58
10K
7,9,21,22,34,46,56,58 +V1.8
10
w
VDD+
R6M11 8 U6A3B
10K -
1% TLV2463 9
6 OPAMP1_SHTDN#
7
w
58 M_VREF_DIMM_A +
C6M10
R6A13 220pF GND R6A15
A 10K 10% 4 10K A
1% NO_STUFF Capell Valley Intel Confidential
Title
w
M_VREF_DIMM0 21,58
DDR VREF

A D15378 1.501

5 4 3 2 1
5 4 3 2 1
13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,49,50,54,55,57 +V3.3A
m
R5U9 46,49,54,55 +VBATA R4V3 0
1K R5F4 1.5_VIN
17,29,40,46,47,49,54,55,57 +V5A AGND_CAVR
0.002 1%
o
R5U10 0 C5F9 C5F8 C5U3
V1_5PWRGD_R 10uF 10uF 10uF
25V 25V 25V
R5U11
0
c
DCS2P
D DCS2N D
SKIP2
5
6
7
8
Q5F1
R5V3 HDR2 R5F7 0 HDR2_R 4 IRF7811A NO_STUFF
10K TP6G1 +V1.5S 4,10,17,27,56,58
1
2
3
LX2 1 2
L5F2 1.0uH
V1_5PWRGD
C5V4 C5G1 Vout = 1.5V
it c
AGND_CAVR
Q5U1 270uF 270uF
VSET2 IRF7811A R5V4 R3T8 2.0V, 3.3Arms
Iout = 10A
5
6
7
8
1
SLEW2 51.1_1% 1K 2.0V, 3.3Arms
C5U5
4 MBR0530 R5V2 121K1% R5V1 33.2K 1%
C5U6
1
2
3
1 2
0.047UF
2
16V DCS2P C5V2 4700pF
1%
a
DCS2N
LDR2
C5F11 202286-393
0.1uF C5U4
46,49,54,55 +VBATA 10% 1000pF
33
32
31
30
29
28
27
26
25
AGND_CAVR
EU5F1 5%
BST2 16V
CS2P
CS2N
GNDA2
VSET2
SKIP2
SLEW2
PWRGD2
LX2
HDR2
+GMCH_VREF 17,29,40,46,47,49,54,55,57 +V5A
m
AGND_CAVR
R5V8
1K
1 24 R5U8 1
10,32,35,47,49,55,56 PM_SLP_S3# ON2 BST2
2 23 0.002 1%
SP1 GNDP2
C VIN 3 VIN LDR2 22 CR4U1 C
OZ824
e
4 VREF VDDP2 21
C5U7 5 20 CHP_BST_VDD 3
GNDA1 DC-DC CONTROLLER VDDP1
CALISTOGA / ICH7-M
0.01uF VDDA 6 19
10% 17,29,40,46,47,49,54,55,57 +V5A VDDA LDR1 BAT54A
7 CE GNDP1 18
0402 8 17 BST1
ON1 BST1
h
PWRGD1
25V +VBATA 46,49,54,55 2
SLEW1
VSET1
SKIP1
HDR1
CS1N
AGND_CAVR AGND_CAVR 1.05_VIN

CS1P
R5V7 R4V4 C5F10
LX1
VREG
10 1uF
0.002 1% C4U3 C4U2 C4U1 10%
c
10
11
12
13
14
15
16
10uF 10uF 10uF

9
25V 25V 25V

C4F10
5
6
7
8
C4G2 0.47uF
-s
1uF Q4F3 10%
10% HDR1 R4F5 0 HDR1_R 4 IRF7811A 16V NO_STUFF
TP4F1 3,4,6,9,10,14,17,30,37,45,53,56,58 +V1.05S
1
2
3
AGND_CAVR
Vout = 1.05V
VSET1 LX1 1 2
L4F1 1.0uH
Iout = 15A
17,29,40,46,47,49,54,55,57 +V5A
p
C4F9
R4G1 R4U5 270uF
5
6
7
8
1
51.1_1% 1K 2.0V, 3.3Arms
R4V1 DCS1P Q4F2 C4F8 NO_STUFF
0 DCS1N LDR1 4 IRF7822
MBR0530 R4F6 121K1% R4G4 33.2K 1%
o 1
2
3
1 2
SKIP1
2
B B
t
DCS1P C4G1 4700pF
SLEW1
1%
R4G2
10K DCS1N
202286-393
C4U4
p
1000pF
C4U5 5%
0.047UF
16V
AGND_CAVR 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,49,50,54,55,57 +V3.3A AGND_CAVR
la
AGND_CAVR
R5V16 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,49,51,54,55,56,57,58
+V3.3S
1K
.
R4G5 0 +V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,49,50,54,55,57
+GMCH_VREF NO_STUFF V1.05_EVMC_V_CNTL 58 C8V3
C5V6 0.1uF
5
0.1uF U8V1 16V
5
U5G2 16V 1
V1_05PWRGD_R V1_05PWRGD 46 PM_PWROK
R5V13 0 1 74AHC1G08 4
1.5_1.05_PWRGD R5V10 ALL_SYS_PWRGD 16,32,35
74AHC1G08 4 0 2
w
C5V3 R5G1 V1_5PWRGD_R 2
1uF R4G3 10K
1% 1.5_1.05_PWRGD_R
10% 20k_1% This is system power
3
3
VSET1 VSET2 good representing power

Combined 1.5V & 1.05V good for all S rails
w
VR Power Good
C4V1 R4V2 C5V1
A 0.01uF 14.7K 0.01uF R5V5 R5V6 0 A
10%
1%
10% 15K NO_STUFF V1.5_EVMC_V_CNTL 58 Capell Valley Intel Confidential
0402 0402 1%
25V 25V Title
w
PWRGD & DDR2 VREF

AGND_CAVR
NOTE: VREG = 2.525V A D15378 1.501

5 4 3 2 1
5 4 3 2 1
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,51,54,55,56,57,58
54,58 +V5A_MBL C4H3
C4H6 R4H7 V5RC 5600pF V5A_INV
R4H26 V3SRC 5600pF V3S_INV 332
m
332 1% C3H3 V5FBRC V5A_FB
C3H13 V3SFBRC V3S_FB R4H9
R4H29 R4H28 R4H5 3300pF 2.49K
3300pF 2.49K 49.9K
28.7K 1% R4H8
o
R4H27 10K
10K 1%
+VBATA 46,48,54,55
c
5.0_VIN R3V4
D 0.002 1% D
.
54 +V3.3A_MBL C3V2
C4H4 0.1uF 22uF
R4H13 V3ARC 5600pF V3A_INV C3G2
Mobile 5V Rail
5
6
7
8
332
R4H10 C3H6 V3FBRC V3A_FB Q3G6
s
R4H15 5VTG 4 IRF7811A 54,58 +V5A_MBL
3300pF 2.49K L4G1
29.4K 1%
1
2
3
1 2
R4H14 3.3uH
5
6
7
8
1
10K
it c
1
CR3W1 Q3V2 C4G5 + C4G6
2 1 4 IRF7811A CR3G4 220uF 0.1uF
B320A 10%
1
2
3
2
MBR0530
C4H2 46,48,54,55 +VBATA
2
0.1uF
46,48,54,55 +VBATA
+V5REF R3H2
0 R3W4 C3H5
+V5REF 16.9K 1% 0.1uF C2J1
a
1
CR4H1 C3H1 NO_STUFF 22uF
5
6
7
8
0.1uF NO_STUFF
3VTG
BAR43 Q3H2
R4H18 V5BST R3H4 4 IRF7811A
0 R3W3 0 NO_STUFF L3H1
3 R3H3 12.1K NO_STUFF V3SW_L1 TP3G1
1
2
3
1 2
2.2 C3H2 3.3uH NO_STUFF
5
6
7
8
1
m
0.1uF NO_STUFF
1
C3W2 Q3G7 + C3G1 C3V1
0.01uF V3BG 4 IRF7811A CR3G5 220uF 0.1uF
10%
4N1_FLT
R4H17 NO_STUFF B320A NO_STUFF
4N1_LH1
NO_STUFF
C C
V5OCP
V3OCP
0 NO_STUFF
1
2
3
2
AGND_5130
V5SW
V5BG
V5TG
NO_STUFF
2
e
V5A_INV CR3W2
1 2 +VBATA 46,48,54,55
CR3H1 +V5REF
48
47
46
45
44
43
42
41
40
39
38
37
AGND_5130 U3H1 MBR0530 3 1
V3SW
+V5REF 46,48,54,55 +VBATA NO_STUFF R2H3
h
OUT1_D
OUT2_D
INV1
LH1
OUT1_U
LL1
OUTGND1
TRIP1
VIN_SENSE12
TRIP2
OUTGND2
FLT
C3H4 0.1uF BAR43 1.00
V5A_FB 1 36 NO_STUFF NO_STUFF
V5VRON 2 FB1 LL2 V3TG R3H5 V3BST C3H8 C2W11 +V3REF
SS_STBY1 OUT2_U 35
VR_ALW_ENABLE R4H11 V3S_INV 3 34 4N1_LH2 2.2 NO_STUFF +V3REF 0.1uF 22UF +V5REF
INV2 LH2
3
c
10K V3S_FB 4 33 5130VIN +V5REF
Q4H5 V3VRON FB2 VIN 3VREF R3W5 1.00 +V5A 17,29,40,46,47,48,54,55,57
5 SS_STBY2 VREF3.3 32
5130PWMSEL 6 TPS5130PT 31 5VREF R3W7 C3H10 C3H7
4N1_5ON 1 5130CT PWM_SEL VREF5 5130_5VIN 1.00 R3W9 10uF 10uF
7 CT REG5V_IN 30
R4W3 BSS138 8 GND
4 IN 1 LDO_VIN 29 1.00
3
-s
0 5130REF9 28 1000pF C3W7 C3W5 0.22uF
Q4H4 R4H21 10K 5130VREFON REF Controller LDO_CUR
2
10 STBY_VREF5 LDO_GATE 27
BSS138 R4H20 10K 5130VREFON_3 11 26 V2.5SNS-
5ONG AGND_5130 5% STBY_VREF3_3 LDO_OUT V2.5G R2W8 2.2 4N1_2.5G C3W6
1 12 STBY_LDO INV_LDO 25
VIN_SENSE3
C3W4 C3W3 C4H5 C3H9 NO_STUFF
PG_DELAY
SS_STBY3
OUTGND3
33pF R3H7 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,50,54,55,57 +V3.3A
OUT3_U
OUT3_D
R4H6 0.01uF 0.01uF 0.1uF 10K 1000pF
PGOUT
2
2.5V_EV 58
TRIP3
100K R3H8 C3W8 1000pF
INV3
1
2
5
6
FB3
LH3
LL3
p
AGND_5130 5.11K NO_STUFF 0.05 C2W6
46,48,54,55 +VBATA Q2H5R2H2 10uF
R4H24 AGND_5130 100 4_IN1_LDO_EN TPS5130PT 3.3_VIN R4Y1
10,32,35,47,48,55,56 PM_SLP_S3#
13
14
15
16
17
18
19
20
21
22
23
24
C3J1 C3J2 0.002 1% SI3442BDV +V2.5S 10,18,20,56,58
AGND_5130 +V5REF R4H23 V3.3ASS 3
V3A_FB
V3A_INV
5130PGDELAY
4N1_LH3
+V5REF 0 V3.3ABG 22uF 0.1uF R3H9
o V3.3A_OCP
V3.3AVRON V3.3ASW 0.01
5
6
7
8
3.3ATG
C2H5
B
3
t
R4H25 C3H11 Q3J1 C2W10 +
4
R4H19 10K Q4H11 V3.3ATG R3H11 4 IRF7811A V2.5OUT 54 +V3.3A_MBL 0.1uF
3
10K 0.01uF 0 L3J1 100uF

Q4H8 V3.3A_ON_INV R3H10 2 V3.3AOUT
R3J1
1
2
3
1 1
3
1
BSS138 2.2 3.3uH
5
6
7
8
4IN1_3ON 1
p
C3H12 0.1uF CR3H3 0.002 + C3J5 + C3J4 C3J3
BSS138 Q3H3 330uF 330uF
2
AGND_5130
B320A 20% 20%
3
1 Q4H9 4 IRF7822 0.1uF

2.5SV Rail
1
Q4H6 BSS138 V3ABST
2
AGND_5130
BSS138
1
2
3
2
TP4H1 4IN1_3ON_TP
2
la
AGND_5130
1
5130_PWRGD_Q
NO_STUFF C3W10 CR3W4

R4H16
46,47 PM_SYS_PWRGD
0.01uF MBR0530
3.3AV Rail
100K
2
2
AGND_5130
1 R3W6
.
AGND_5130 CR3W5 C3W9 16.9K +V5REF
VR_ALW_ENABLE 1% +VBATA 46,48,54,55
AGND_5130 BAR43 0.1uF 3 1
CR3H2
27,54 VR_ALW_ENABLE
3 BAR43
VR ALW ENABLE goes high with
R4H22 AGND_5130
w
insertion of AC or button press 100K +V3.3A
to turn on +V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,50,54,55,57 Q4H1
2
BSS138
R3W10 1 ATX_PWR_CNTRL 54,55
AGND_5130 10K
5%
w
32 5130_PWRGD
3
Capell Valley
R4W8 Title
w
TPS5130 System Power
0
AGND_5130

A D15378 1.501

5 4 3 2 1
5 4 3 2 1
54 +VBS
J1G3
R3G3 10K 3
L1G1 SHUNT
MAX8724 Set Points Table
m
3 2 VAC_BRCK_IN 2
54 BC_ACOK_BATT +AC_INPUT ACOK# Trip point when AC adpater = ~15.6V
3
Q2G6 4 1 BRCK_IN_GND 1 Battery Charging Current (Vcls) --> 2.1A
BSS138 GND +VAC_IN_L Battery Charging plus System Current
AC_JACK (Victl) --> 11A
1 1k@100MHz CR1V1 RB081L-20 Charging Voltage (Vvctl) -->12.6V
o
4A, 50V, DCresist=12mohm(1 line) 2 1
3,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,54,55,57 CELLS --> Floating = 3 cells
+V3.3A +VAC_IN
2
Discontinuous Mode --> Imin = 0.75A
R2G1 10K Q2G8 Continuous-Conduction Mode
c
SI7458DP 9.3V < Vbatt < 11.088V
D D
32,35 BC_ACOK 3
5 2 REF Voltage = 4.096V
.
Q2G7 1 LDO Voltage = 5.4V
BSS138 R2W1 6.65K 1% R2W2 1K 1%
C1V1 C1V2 C2G2 C2V3 C2G1 C2G3
1 22uF 0.1uF R1V2 C1V3 22uF 22uF 22uF 22uF
25V 10% CR2V1 100K 0.1uF 25V 25V 25V 25V
4
s
1 3 BC_DCIN AGND_BC 1% 10%
+VBC_LDO +VBC_LDO
2
R3W2 10K BAT54 C2G4
R2V10 10K 1uF ACOK#_R
it c
1% NO_STUFF 10%
+VBC_LDO
Q3H1 C2V4 0.1uF
1 BSS138 16V NO_STUFF AGND_BC R1V1
32,35 BC_SHDN
EU2W1 100K
BC_BATT R3H12 R2V11 10K 1 1%
R3G1 100K 1% NO_STUFF BC_CELLS DCIN C2G5 1uF
2
5% 17 CELLS
41.2K 10 BC_ACIN +VBC_LDO 80% BC_ACOK#
1% R2G4 AGND_BC BC_ACOK# ACIN 16V
11 ACOK#
130K 2 R2G2 33
5% BC_SHDN# LDO CR2G4
8 SHDN#
a
CR3G6 22 BC_DLOV 1 3 BAT54WT1
BC_REFIN_D
DLOV
5
BAT54 BC_REFIN 12 D D
+VBC_REF REFIN BC_BST R2V18 0 BC_BST_R
1 3 BST 24
+VBC_REF 4 G G
REF BC_DHI R2G3 0 BC_DHI_R Q2H1 Q2H2
DHI 25 4 4
BC_CLS 3 HAT2168H HAT2168H
+VBC_LDO CLS BC_LX S S NO_STUFF
LX 23
R2V15 10K BC_VCTL
1
2
3
1
2
3
15 VCTL
R3G2 C2H1 R3H1 R2W10 R2V17 21 BC_DLO R2V16 0 BC_DLO_R
m
49.9K 0.1uF 49.9K 45.3K 37.4k_1% BC_ICTL DLO C2H2
1% 1% 1% 13 ICTL
16V 20 0.1uF
BC_ICHG PGND 10%
32,35 BC_ICHG 9 ICHG
C 19 BC_CSIP C
BC_IINP CSIP
28 IINP BC_CSIN
e
AGND_BC AGND_BC AGND_BC
CSIN 18
BC_CCV 7 CCV BC_CSSP
CSSP 27
C3W1 BC_CCI 6
C2W8 R2W9 R3V5 C2V9 R3W1 0.1uF CCI BC_CSSN
CSSN 26
GND2
0.01uF 49.9K 49.9K 0.01uF 20k_1% 10% BC_CCS 5
GND
CCS
h
10% 1% 1% 10% 16V 16 BC_BATT C2W1 C2V8
BATT
1
0402 0402 0.1uF 0.1uF D D BC_CSIP C2V7 0.1uF 16V
R2W3 R2W7 R2W6 MAX8724 10% 10% CR2W1 10%
29
14
25.5K 0 178 G G MBRS130LT3 BC_CSIN C2V6 0.1uF 16V
1% 1% Q2H3 Q2H4 10%
4 4
BC_CSSP
c
AGND_BC AGND_BC HAT2164H HAT2164H C2W3 0.1uF 16V
BC_CCV_C
BC_CCS_C
R2V14 R2W4 R2W5 R2V13 R2V12 NO_STUFF 10%
2
S S
BC_CCI_C
32,35 BC_IINP
1
+VBC_LDO +VBC_REF R3G4 0 10_1% 10_1% 10_1% 10_1% BC_CSSN C2W2 0.1uF 16V
1
2
3
1
2
3
AGND_BC 0 L2H1 10%
3.3uH BC_BATT C2V5 0.1uF 16V
C2H3 C2H4 10%
-s
4.7uF 1uF R2W11 C2W9 C2W7 13A
80% 10% 24.9K 0.1uF 0.1uF C2W5 C2W4
16V 1% 10% 10% 0.022uF 220pF +VCHGR_OUT
2
AGND_BC
16V 10% 10% +V_BC_OUT

16V 0402
AGND_BC AGND_BC
AGND_BC AGND_BC AGND_BC AGND_BC
p
R1H2 0.020 1% R2H4 0.005
1%
C1J1 C1H1
10UF 10UF 54 +VBS
25V 25V
o
B B
t
C2H7 C1H2 C2H11 C2H10 C2H6
+V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,54,55,57 47uF 47uF 47uF 22uF 10UF
+V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,54,55,57 20% 20% 20% 25V 25V
J1H1
p
1 1
2 C1W6 C1Y1 C1W1 C1W2
2 SMB_BS_CLK 24,32,35
3 5 U1H1 R1W4 10K 0.1uF 0.1uF 0.1uF 0.1uF
3 BC_THERMB SMB_BS_DATA 24,32,35
Batt B 4 74AHC1G02 10% 10% 10% 10%
4 16V 16V 16V 16V
5 5 1 BS_CHGB# 32,35
6 CHGB 4 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,54,55,57 +V3.3A
la
6 DISB#
7 7 2
R1W1 100K
R1H1 10K R1W7
3 C1W5 C1W4 24.3K
R1W8 0.1uF 0.1uF R1H3 1%
MAX809 Trip
.
+V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,54,55,57 1K 10% 10% R1H4 10K
16V 16V 10K 5% Point = 2.93V VBS_DIV
R1W2 0 BC_THERMB R1W3 6.81K VBS Trip Point
BS_DISB# 32,35 PRE_L
NO_STUFF 1% U1H2 C1W3
5
R1Y1 0 BC_THERMA R1Y2 1.74K 74AHC1G08 = 8.7V U1H3 R1W6 0.1uF

32,35 SMB_BS_ALRT#
3
NO_STUFF 1% 12.4K 10%
1 1%
4 R1W5 100K U1H4 16V
VCC
3
w
2 8 1 VBS_TRIP Q1H1
VCC CLK
7 PRE# D 2 BSS138 1 VBS_TRIP# 2 RST#
Battery Address Key 6 3
GND
FLIPFLOP_Q CLR# Q# Q1H2
3
5 Q GND 4 1
SMBUS Address for Battery B = 1E Host Total BSS138
2
Address Resistor (Host + 200) 1G D-FLIP FLOP
SMBUS Address for Battery A = 16 14 820 1020 FLIPFLOP_Q# MAX809
1
16 1800 2000 U1H5 R1W9 10K
w
5
18 2700 2900 74AHC1G02
1A 3900 4100 BS_CLR_LTCH# 32,35
1 BS_CHGA# 32,35
1C 4700 4900 4
A 1E 6800 7000 2 A
J1J1
20
22
9100
11000
9300
11200
3
w
1 1
2
Title
2 SMB_BS_CLK 24,32,35
3 3
BC_THERMA SMB_BS_DATA 24,32,35
U1H6
BS_DISA# 32,35 System Charger VR (1 of 2)
Batt A 4 4
5
5 74AHC1G08
5 CHGA
6 6 1
7 7 DISA#
R1Y3 100K
4
2
R1W10 100K Size Document Number Rev
R1J1 10K A D15378 1.501
3

5 4 3 2 1
5 4 3 2 1
CPU VCC_Core VR and MUX Buffer
m
5,10,17,18,19,20,25,26,39,41,43,44,45,47,52,54,55,56
Q2C5 +V5S
1 GND1 TOVER# 5 H_PROCHOT# 3
2
o
52 +VDC_PHASE GND2
3 HYST VCC 4
52+V5S_IMVP6
MAX6501 C2C12 C2C13
2.2uF 0.1uF
c
C2B13 10% 10%
D
25V Temperature Monitor D
1.0uF R2B14 10V
.
AGND_VCORE
10% 10_1%
C2B12
s
1.0uF
10%
25V
3,14,35 H_DPRSTP# IMVP6 PWM1
AGND_VCORE
it c
45
45
VR_VID6
VR_VID5
CPU Core PHASE_1
45
45
VR_VID4
VR_VID3 VR PWM2
45
45
VR_VID2
VR_VID1 Controller PHASE_2
45 VR_VID0
FCCM
R1C1 499 1%
a
DPRSLPVR
7,16,35 PM_DPRSLPVR
3 PSI# PWM3
48 1.5_1.05_PWRGD_R PHASE_3
30,31 VR_PWRGD_CK410#
32,35 IMVP_VR_ON
7,16 DELAY_VR_PWRGOOD VSUM
4 VCCSENSE
m
4 VSSSENSE
VCC_PRM
C C
C2C5
e
0.1uF
10%
10V
h
AGND_VCORE
c
R2N13 0
AGND_VCORE
- s
5,10,17,18,19,20,25,26,39,41,43,44,45,47,52,54,55,56
+V5S
Input Output S2 S1 S0
A C 1 1 0
p
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,54,55,56,57,58
+V3.3S
B C 1 1 1
R1N4
A D 1 1 1
o
8.2K R1N14
R1N9
R1N6
R1N5
R1N3
R1N2
R1N1
B D 1 1 0
B B
t
8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K U1B2
IMVP-4STRAP_VID0 2 A0 46
C0 VR_VID0 45
p
IMVP-4STRAP_VID2 C1 VR_VID1 45
8 A2 C2 41 VR_VID2 45
13 A4 C4 36 VR_VID4 45
la
18 A6 C6 31 VR_VID6 45
21 A7 C7 28
15
13
11
23 A8 C8 26
9
7
5
3
1
.
J2B1 3 45
4 H_VID0 B0 D0
4 H_VID1 6 B1 D1 43
2X8_HDR 9 40
4 H_VID2
16
14
12
10
B2 D2
8
6
4
2
4 H_VID3 12 B3 D3 37
4 H_VID4 14 B4 D4 35
4 H_VID5 17 B5 D5 32
w
19 30
V5_S0 4 H_VID6
22
B6 D6
27 5,10,17,18,19,20,25,26,39,41,43,44,45,47,52,54,55,56
B7 D7 +V5S
24 B8 D8 25
5,10,17,18,19,20,25,26,39,41,43,44,45,47,52,54,55,56 +V5S
1 S0 VCC 7
R1N15
48 S1 GND0 4
S2_S1
w
47 S2 GND1 10
34 15 C1N2
10K GND5 GND2 .01uF
39 GND6 GND3 20
A 42 GND7 GND4 29 A
74CBT16209A Capell Valley Intel Confidential
w
Title
IMVP-6

A D13073 1.501

5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
it c
a
5,10,17,18,19,20,25,26,39,41,43,44,45,47,51,54,55,56
m
+V5S
51 +VDC_PHASE +VBAT 19,54,55,56 +V5S_IMVP6 51
C C
R1B3 .002 R1B2 .002
e
1W 1W
+V5S_IMVP6 51 4,53,56,58 +VCC_CORE
c h
FCCM
IMVP6
- s VCC_PRM 51
p
PWM1 VSUM
CPU Core
FCCM VR
o
B PWM3
Controller PHASE_1 B
t
FCCM PHASE_2
PWM2 PHASE_3
la p
w .
w
A A
w
Title
IMVP-6 Core VR

A D13073 1.501

5 4 3 2 1
5 4 3 2 1
Vccp Core Decoupling
m
3,4,6,9,10,14,17,30,37,45,48,56,58 +V1.05S
Place these inside socket
o
C3T2 C2T10 C2T12 C2T13 C2T11 C2T9
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF cavity on L8 ( North side
10% 10% 10% 10% 10% 10% Secondary)
c
D D
Vcc Core Decoupling
s.
4,56,58 +VCC_CORE
it c
Place these inside socket C2R5 C2T8 C2T7 C2T6 C2T5 C2T4 C2T3 C2T2 C2T1 C2R4
22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
cavity on L8 ( North side 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
Secondary)
Place these inside socket C2T23 C2T21 C2T20 C2T19 C2T18 C2T17 C2T16 C2T15 C2T14 C2T22
a
22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
cavity on L8 ( South side 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
Secondary)
m
Place these inside socket C2E1 C2E2 C2E3 C2E4 C2E5 C2E6
22uF 22uF 22uF 22uF 22uF 22uF
cavity on L1 ( North side 20% 20% 20% 20% 20% 20%
C Primary) NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF C
e
Place these inside socket C2E7 C2E8 C2E9 C2E10 C2E11 C2E12
h
22uF 22uF 22uF 22uF 22uF 22uF
cavity on L1 ( South side 20% 20% 20% 20% 20% 20%
Primary) NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF
s c
1
1
South Side Secondary + C2U1 + C2U3 + C2U2 + C2R1 + C2R2 + C2R3 North Side Secondary
-
3 330uF 3 330uF 3 330uF 3 330uF 3 330uF 3 330uF
20% 20% 20% 20% 20% 20%
2
o p B
pt
. la
A
ww Capell Valley
Title
Intel Confidential
A
w
CPU Decoupling

A D15378 1.501

5 4 3 2 1
5 4 3 2 1
Q4G2
IRF7811A 8
3 7 50 +VBS Q2J1 46,48,49,55 +VBATA
2 6 SI7453DP
1 5 3
m
+V5A 17,29,40,46,47,48,49,55,57 5 2
49,58 +V5A_MBL 1
C2Y10.1uF C2H9 Q2W2 19,52,55,56 +VBAT
R2Y2 + R2V3
4
100K 390K SI4425DY 46,48,49,55 +VBATA
o
15uF
4
8 3 8
3 7 C2V2 0.33uF 2 7
2 6 VBSGT 1 6
1 5 5 C5B11 C2W12 C2H8 R2V6
1
46,48,49,55 +VBATA + C4H1 + C4G8 + + + 100K
c
Q4V3 220uF 220uF R2Y1
10% 10%
D IRF7811A 10K 15uF 15uF 15uF D
4
PWRONLATCHG
.
R3F1 R2V7
2
+V5SB_ATXA 100K 1M
3
C3F1 V12ATXSW
3
Q4H2 0.1uF
R4W2 BSS138 10% Q2W1 R2V9
s
ATXPWR 1 BSS138 100K
3
1
0 PS_ON_SW# Q2G5
R4W1 CR2G3 BSS138
2
1K
2
3 1 1
it c
BAR43
2
49 +V3.3A_MBL +V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,55,57 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,55,57 +V3.3A
3
4
ATX_PWR_CNTRL 49,55
SW1C1
Q3G1
Push_Button
IRF7811A 8 POWER ON
3 7 R2V4
and S5
1
1
+ C4G4 + C4G3 100K 46,48,49,55 +VBATA
1
2
a
2 6
1 5 220uF 220uF ENTER/EXIT
10% 10% R2V8
Button SMC_ONOFF# 32,35
100K
2
3PS_PWRBTN
3
R2V5
Q2V1 PS_LATCH# 100K
4
BSS138
R2W13 0 ADAPT_PRES_R 1
50 BC_ACOK_BATT
m
8 SHUTDWN#
3 7
R2W14 Q2G2
2
2 6
3
1 5 100K R2W12 2 BSS138
3
C NO_STUFF
100K
CR3W3 1 Q2G1 C
Q3G2 BAT54C Q2G4 BSS138
e
IRF7811A BSS138 BSS138 1
4
2
32,35 SMC_SHUTDOWN 1
3 PS_ACENABLE 3 2 VR_ALW_ENABLE 27,49
R2V2
Active high C2V1
2
Q3W1 1000PF 43K
2
h
means AC present Either insertion of AC 46,48,49,55 +VBATA
from the Battery or button press latch
1
1 CR2G2
charger will assert enable of
c
2
1.5A & V3.3A 3 +V3.3A
SHUTDWN# R3H6 0 1 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,55,57
NO_STUFF R2H1
-s
100K J3H1
BAR43S
Stuff R3H6 only
Active high means for G3 Mobile
button press detect and power cycling
Force Shutdown
latch from start up
p
circuit 100K pull up to
MOBILE OPTION
+VBATA on this page 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,55,56,57,58 +V3.3S
R6J4 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,55,57
RESET 10K C6J3 +V3.3A
o
SW1C2 U6J3
PS_LATCH# BUTTON
ATX Spec dictates ATX 1 4 0.01uF C6J2
B GND VCC B
t
1 3 0.1uF
supply has internal pull
5
1 2 4 U6J2
up to 3.3V RSTBTNDB 2 3 MASTER_RESET#
1
Push_Button IN OUT
4 PM_SYSRST# 16
MAX6816 2
p
CR4Y1 3 PS_ON# 5,10,17,18,19,20,25,26,39,41,43,44,45,47,51,52,55,56 +V5S R6J5 100K
BAT54A +V5SB_ATXA 1 74AHC1G08
46,48,49,55 +VBATA 5,10,17,18,19,20,25,26,39,41,43,44,45,47,51,52,55,56 +V5S
3
CR5J1
3,37,58 XDP_DBRESET#
BAT54
2 R7J1 R7J4
la
PS_ON_SW# +V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,55,57 330
+V5 25,26,27,35,38,47,55,56,58 330
+V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,55,57 3 J8J1
55 -V12A ATX POWER FRONT1 1 2 FRONT2
14 ATA_LED# 3 4
.
J4J1 17,29,40,46,47,48,49,55,57 +V5A 5 6 PWR_CONN_D C7J7
R4Y5 RST_PUSH#_D 7 8 470pF
ATX ALWAYS ON 1K 5% 11 1 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,55,57 +V3.3A
12 2 9 10
DT OPTION NO_STUFF 11 12
13 3 Shunt pins 13 & 15
14 4 13
R9W13 for SV forcing ATX PS_LATCH# 15 16
15 5 10K CR8J1
on and VBAT on for
w
17,29,40,46,47,48,49,55,57 +V5A 16 6 R9W14 PS_ON_SW#
17 7 power cycling 3 1
10K
18 8 ATX_PWROK 32
C8J6 BAT54
19 9 ATX_DETECT# 32,35
+V5SB_ATXA C8J3 C7J6 C8J7
20 10
3
TO H8 TO INDICATE 470pF 470pF 470pF 470pF

+5V_DL_R CON20_PWR Q9W1
5SB_ATXA_R
PRESENCE OF ATX SUPPLY.

R5J3 R3Y1 BSS138 VTYP=3.0 WHEN ATX IS
Front Panel Header
w
1
2
5
6
+3.3V_DL
R3Y4 R5W4 3.0 3.0 1

10K Q5H2 3.0 5% 5% PRESENT AND ON.
SI3442BDV 5%
A A
+5V_DL

2
+V5_DL_Q 3
PS_ATXSENS
+V5SB_ATXA +3.3V_DL_R R3J3 R9W10

3.0 10K Title
w
1
2
5
6
Q3J2 5%
R5J2 R3Y5 SI3442BDV Start Up Sequence
4
3.0 10K
5%
3V MIN CURRENT
5V MIN CURRENT +V3.3_DL_Q 3 DUMMY LOAD: Size Document Number Rev
DUMMY LOAD: Gives Gives 0.5A min A D15378 1.501
0.5A min current current load
4
load 60
Date: Wednesday, July 20, 2005 Sheet 54 of
5 4 3 2 1
5 4 3 2 1
+V3.3S 5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,56,57,58
17,29,40,46,47,48,49,54,57 +V5A 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,57 +V3.3A Q4V2 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,57
5,10,17,18,19,20,25,26,39,41,43,44,45,47,51,52,54,56 +V5S IRF7822 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,57 +V3.3A +V3.3A
8 Q4G3 8
m
7 3 7 3
2
6 2 6 2 Q2G3 Q3G5
5 1 5 1
46,48,49,54 +VBATA IRF7811A 1 SI2307DS 1 SI2307DS
16 PM_SLP_S5# 16,26,32,35,46,56 PM_SLP_S4#
o
R4G7 SLPS3#_CONTROL PP_S5LED PP_S4LEDSW1
3
3
100K
R4G6 Q4G5
100K BSS138 C4G7 R2V1 R3V2
c
1 0.01UF 75 75
D 10% D
.
PS_S3CNTRL 25,26,27,35,38,47,54,56,58 +V5
+V3.3 13,14,15,17,25,27,32,33,34,35,36,38,45,46,56 PP_S5LEDSW
2
3
PP_S4LED
2
Q4G4 8 Q4V4 +V3.3A 13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,57
BSS138 7 3 S5 CR2G1 S4 CR3G3
s
1 6 2 8 IRF7822
10,32,35,47,48,49,56 PM_SLP_S3# GREEN GREEN
5 1 7 3 Q4G1
IRF7811A 6 2
1
5 1
PP_S4LEDSW2
it c
3
R4V6
4
100K SLPS4#_CONTROL Q3V1
3
R4V7 C4W1 BSS138
4
100K Q4V5 0.1uF 1
16 PM_SLP_S5#
BSS138
PS_S4CNTRL 1
2
3
Q4W1
2
BSS138
a
16,26,32,35,46,56 PM_SLP_S4# 1
25,26,28,35,39,43,44,56,58 +V12S
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,56,57,58 +V3.3S
2
+V3.3A Q5H1 13,14,15,17,25,27,32,33,34,35,36,38,45,46,56 +V3.3

13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,57 46,48,49,54 +VBATA 3 8
2 7
2
m
1 6 Q3G4
R4H12 5 C5W9 R3V1
SI4425DY 0.33uF 1 SI2307DS 75
10,32,35,47,48,49,56 PM_SLP_S3#
10K C5H3
C 0.1uF C
4
ATX_PWR_CTRL_1 R5H32 PP_S3CLED PP_S0LED
3
e
100K GREEN
3
2
Q4H3 R3V3 SO CR3G1
BSS138 PS_12SSW 75
1
h
49,54 ATX_PWR_CNTRL
R5H34
C7P1 0.1uF 100K PP_S3CLEDSW PP_S0LEDSW
31
10%
2
2
U5G1 Q3G3
c
1 S3 CR3G2 BSS138
4 PS_12SG 1
GREEN 10,32,35,47,48,49,56 PM_SLP_S3#
10,32,35,47,48,49,56 PM_SLP_S3# 2
3
74AHC1G08 Q5H3
2
-s
BSS138
3
PM_S3#_AND 1
2
Q6B2 13,18,19,27,56 +VBATS Q6B1 13,56 +VBAT_S4
19,52,54,56 +VBAT 3 8 19,52,54,56 +VBAT 3 8
p
2 7 2 7
1 6 1 6
5 5
SI4425DY C6N2 C6N5
C6N3 R6N4 0.33uF C6N4 R6N3 SI4425DY 0.33uF 75 ohms chosen for
~16mA of LED current
PS_VBATSG
PS_VBAT_S4_G
0.33uF 100K 0.1uF 100K

4
o
B B
t
R6N1 R6N2
100K 100K
p
PS_VBATSW PS_VBAT_S4_D
3
Q6B3 Q6N1
BSS138 BSS138
la
10,32,35,47,48,49,56 PM_SLP_S3# 1 16,26,32,35,46,56 PM_SLP_S4# 1
2
.
54 -V12A
w
C9B1
R9B4 0.1uF
10K
w
1
2
3
U9B1 PS_-12SSW 4
Q9A1
Capell Valley
SI4420DY
C9B2 Title
w
1 4
0.1uF
5,10,17,18,19,20,25,26,39,41,43,44,45,47,51,52,54,56 +V5S Sleep control
R9B1 25,26 -V12S
PS_-12OPTSW
5
6
7
8
2 3
330 TLP280
A D15378 1.501

5 4 3 2 1
5 4 3 2 1
SLP_S4# DISCHARGE CKT
SLP_S3# DISCHARGE CKT DESIGNED FOR ~100ms
DESIGNED FOR ~100ms DISCHARGE ON ALL S4
m
DISCHARGE ON ALL S3 RAILS.
RAILS.
13,14,15,17,25,27,32,33,34,35,36,38,45,46,55 +V3.3
o
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,57,58 +V3.3S
25,26,28,35,39,43,44,55,58 +V12S
1
R7B13 R4V5
c
180 R5G4 97.6
D 97.6 D
.
19,52,54,55 +VBAT
PP_V12SDIS PP_V3SDIS PP_V3DIS
32
3
1 Q7B1 Q5G1 Q4V1
BSS138 BSS138 BSS138
s
CR3U1 1 1 1
BAT54
2
3
it c
VBATA_DISCHARGE
5,10,17,18,19,20,25,26,39,41,43,44,45,47,51,52,54,55 +V5S 10,18,20,49,58 +V2.5S +V5 25,26,27,35,38,47,54,55,58 13,55 +VBAT_S4
C3U1
1
R3U5 R6N5
22UF 100K R3Y2 180
R5G7 470 R5W2
a
97.6 97.6
PM_SLP_S3 PP_V5SDIS PP_V2.5SDIS PP_V5DIS PP_BATS4DIS
32
3
3
Q5G4 Q3Y2 R3U6 Q5V1 Q7N1
3
BSS138 BSS138 100K BSS138 BSS138

Q4C1 1 1 1 1
m
BSS138 R3U4
1 1M
10,32,35,47,48,49,55 PM_SLP_S3#
2
C C
2
PP_S4GT
e
23,46,58 +V0.9 7,9,21,22,34,46,47,58 +V1.8
4,53,58 +VCC_CORE 4,10,17,27,48,58 +V1.5S 13,18,19,27,55 +VBATS R9A9
1M
h
R4C26
1
68
R3D1 R3J2 R5G3 R4B7
c
47 47 180 220
PP_V0.9DIS PP_V1.8DIS
3
PP_VIMVPDIS PP_V1.5SDIS PP_12DIS
32
3
3
Q4B2 Q4D1
-s
Q3D1 Q3Y1 Q5G3 BSS138 BSS138
BSS138 BSS138 BSS138 1 1
1 1 1
2
2
3
p
Q4U2
BSS138
16,26,32,35,46,55 PM_SLP_S4# 1
10,47 +V3.3S_TVDAC
2
o
3,4,6,9,10,14,17,30,37,45,48,53,58 +V1.05S
B B
t
R4F1
4.87K
R3U3 1%
470
p
PP_V3STVDIS
PP_VGMCHDIS
3
3
Q3U1 Q4F1
BSS138
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BSS138
1 1
2
w .
w
ATX Mounting Holes
A A
MT1B1 MT1J1 MT1G1 MT5A1 MT9A1 MT9G1 MT9J1 MT5J1
Title
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2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6
3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
4 8 4 8 4 8 4 8 4 8 4 8 4 8 4 8 DISCHARGE CIRCUITS
5 9 5 9 5 9 5 9 5 9 5 9 5 9 5 9
MT156 MT156 MT156 MT156 MT156 MT156 MT156 MT156

A D15378 1.501

5 4 3 2 1
5 4 3 2 1
LPC Docking Logic
o m
c
D D
.
17,29,40,46,47,48,49,54,55 +V5A
s
C7F1
0.1uF
it c
U7F1
LPCD_QSEN# 1 8
OE1# VCC LPCD_QSEN#
42 LPCD_PCI_PME# 2 1A OE2# 7
42 LPCD_RI# 3 1B 2B 6 SMC_EXTSMI# 16,32,35,42
4 GND 2A 5 LPCD_SMC_EXTSMI# 42
74CBT3306
a
m
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,58 +V3.3S
C8F2
C 0.1uF C
e
5
U8F2
42 LPCD_LPCPD# 1
4 LPCD_PD# 42
16,32,35,42 PM_SUS_STAT# 2
h
74AHC1G08
3
c
5,7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,58 +V3.3S
C7T3
-s
0.1uF
5
U7E3
42 LPCD_LPCRST# 1
4 LPCD_RST# 42
7,13,15,24,28,32,41,42 PLT_RST# 2
p
74AHC1G08
3
R7E4 0
NO-STUFF
o
B B
t
13,14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55 +V3.3A
R8E6
p
10K
LPCD_QSEN#
la
3
Q8E2
BSS138
42 LPCD_PWRGD 1
.
2
ww Capell Valley
Title
Intel Confidential
A
w
LPC Docking

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
Steps 1AC(leads to step 1), 5AC (leads to step CAPPELL VALLEY Mobile
5) for AC Only case (i.e. AC case detects Power On Sequence
m
Battery case
brick and requires button press) waits here for
o
+VBATA step 1BAT
Step 1BAT (leads to step1) for 1 before step 1
battery only case (i.e. BATT case Charger 5AC 1BAT
c
D D
requires button press to begin Circuit 1AC
.
BS_ACAD_PRES Startup PS_ON_SW# PG 50
power up) 6
SLP_S3# Circuit
s
7 +VBATS +VBAT
7
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+V3S_TVDAC SLP_S3 +V5A
+V5S +V3.3A
7 SWITCHES
SMCONOFF#
LDO +VBATA
+V3S +V3.3A
5AC
7 SYSTEM 2 MAX-809
a
+V2.5S +V3S VR_ALW_ENABLE
7 3 +V5A VR
+VBAT_S4 SLP_S4# +VBAT +V3.3A H8 SMC SMCRES#
7 3 AC case waits
m
SLP_S4 4 here for step ICH
C 7 +V5 SWITCHES +V5A +V1.5A_AZ_IO +V3.3A 5AC C
e
PM_PWRBTN#
7 +V3 +V3.3A 3 LDO
VRMPWRGD
5b
h
PM_RSMRST#
SLP_S4# +VBAT 11 16 H_PWRGD
5a
c
IMVP_VR_ON 99ms DELAY
7 +V1.8 DDR VR PWROK
-s
7 +V0.9 15 17
PLT_RST#
+V1.5A_AZ_IO
p
SYSTEM
DDR_VR_PWRGD
VR POWER +V3S_TVDAC SLP_S3#

6 SLP_S3#
o
GOOD 8 SLP_S4#
SLP_S4#
B B
t
+V3S +VCC_GMCH_CORE,
MONITOR +V1.05S_VRPWRGD 8 6 +VCCP
+VCC_CORE,
+VCCP
+V2.5S
p
+V1.5S_VRPWRGD
9 8
7
+V1.05S CALISTOGA
+V1.5S +V1.05S CPU
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9 +V1.5S
VR 18 H_CPURST#
8 PM_SYS_PWRGD 7
VR
.
ICH VCCP ,
11
ALL_SYS_VRPWRGD
LOGIC VCC MCH,
+VCC_CORE IMVP_VR_ON VCC ICH,
PWROK
MCH GFX,
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12
System VR_PWRGD_CK111# IMVP
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Clock CORE
A 13 VR
V1.05_V1.5_PWRGD
10 Capell Valley Intel Confidential
A
PM_PWROK Title
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POWER SEQUENCING TIMING BLOCK DIAGRAM
14 DELAY_VR_PWRGD Size Document Number Rev
VR_PWRGD_CK410 A D15378 1.501
5 4 3 2 1
5 4 3 2 1
PG33. Remove U8,C6M4,C9063 and updated whole ckt. P8 REMOVED # FROM M_A_BS#[2:0] P33 Implemented SPI shared topology
Deleted PE_PWRGD off page that goes to pin C3 of P8 REMOVED # FROM M_B_BS#[2:0] P15 Implemented SPI shared topology PG33: Replaced the SPI socket XU8A1
P10 CHANGED +V3.3S_ATVBG TO +VCCA_TVDAC P32 Moved BT_DETACH, BS_DISA# to new pins (IC,SPI_FLASH_SKT,C79969-001) by the SPI solder down
U8A3A symbol. Kept the No-stuff 3.3K pull down as P10 CHANGED VCCA_TVBG TO +V3.3S_ATVBG P27 Changed R8T2 to stuff
P12 UPDATED MCH_CFG_10,18,20 P10 Swapped C4E6 with C4E8 part SIOC8 (IC,SST25LF080A,FLASH,SKT-PT, and IPN is
m
it is right now.
P38 CONNECTED PIN19,20 J9E2 TO +V3.3 P10 Swapped C4E3 with C4E5 C81985-001).: Changed ICH7 LAN power rail change
PG34.Please delete U7D9 and its associate P50 CHANGED R2H3 TO 41.3K P32: Rename off page connector
P50 CHANGED R2H2 TO 49.9K from +V3.3A to +V3.3.
components, off pages around it in the current TV_DCON_DETECT# to TV_DCON_MODE and change to
P50 CHANGED R9946 TO 130K PG14: No_Stuff U8F3.
circle. output.
o
P50 CHANGED R9947 TO 49.9K P49 Added CR4H1.
PG32: Removed LAN_VGA_OVERRIDE and left it as an TP P50 CHANGED R3W4 TO 20K P20: Deleted TV_DCON_DETECT# and its PU R1A1. No P34 Changed Q7M1 to BSS138, Added R7A23.
P50 CHANGED R3W8 TO 24.9K Connect pin 14 of J2A1. Connect pin 8 of U2M1A, P33-34 Changed stuffing notes for R7A20, R7M11.
PG38: Changed the power rail on the two inverters P50 CHANGED R2W13 TO 45.3K P32 Changed ref des in mode note.
to +V3.3A. P50 CHANGED R2W4 TO 37.4K U2M1B, U2A1A, and U2A1B to +V5S from VBAT. Added P10 Changed C4T10 to .47uF, C4E2 to .22uF.
c
P50 STUFFED C2H9, C2H12, C2H8, C2H7, C2H11 two decoupling caps to U2M1 and U2A1. Added a P15,29 Added GNT5_SPI net.
D Update the note table for CFG20 on page 12 P50 CHANGED C2W5, C2W4 TO .022UF D
BSS138 FET to TV_DCON_MODE and DL1 net on U2M1A.
.
Low = Only SDVO or PCIE x1 is operational P5-10 UPdated Calistoga symbol PG55: C4G7 change from 0.1uF to 0.01uF (603269-020
(defaults) P17 Removed C7U5, C7V7, C8484-7, C8492-6, C9005, Updated the table. CAPC,X7R,0603,50V,10%,.01UF.Normal).
High = SDVO and PCIE x1 are operating C8512, C8525, C8527
P17 CHANGED C8482 to 1uF P23 Changed V rail in note to +V0.9 P2 Changed Voltage rail table.
s
simultaneously via the PEG port P17 Removed PD BOM notes P26 Added warning about stuffing R9C1,R9C2 at the P34 Stuffed R7A23
P16 Removed ICHGPIO_25 off-page connection P17 Moved R2460 same time P33 Updated IPN for new Tekoa rev.
P21 Added PM_EXTTS#0 P10 Replaced C4T2, C4T4 with C25529-001
P22 Added PM_EXTTS#0 P14 Removed notes P33,34 Placed E and T marks for stuffing options P14 and P16: Updated symbol name for DPRSLPVR, STP_PCI#,
P40 Added new page with triple stack USB P15 Added 100k PD to BUF_PLT_RST# P4,9,48 Unstuffed C4F7, Swapped C3T1 and C4T3,
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STP_CPU#, CLKRUN#, BATLOW#, DPSLP# and DPRSTP#.
P34 Changed R7A4 to stuff P17 moved R6G10
R2463 Added C3T5
P34 Added notes for stuffing options P31. Changed R7P3 from 33 ohm to 15ohm.
P32,51 Removed R9955
Page 18: Removed docking functionality for CRT, P32 Changed Stuffing notes for MD0-2 P30: Updated FSB Frequency Select table for the 667 MHz
P32,35 Removed BS_VBS_TRIP# and add RSMRST#_PWRD P33 Deleted R8M6,R8A4,R8A5,R8M5
test pointed docking signals, removed Q7D1, added option.
P54 change R4j2 to 1k 5% P33 Removed _R from nets SPI_SI,SPI_SO, SPICE#,
stuffing option for turning on/off docking P7: Disclosed RSVD signals K30 and J29 as TV_DCONSEL0 and
P41 port 80 notes changed SPIS_CLK
switches. P33 Removed CE#_R TV_DCONSEL1
P32,35,50 change +V3REF to +3.3A, delete U3 and P11 Moved FB5D1, C6D1
Page 20: Removed the docking functionality for P31 Changed R7C27 to PD PG14: No_Stuff U8F3.
a
two FETs, renamed BS_CLR_LTCH#, add 10k 5%
TV_Out, test pointed docking signals, removed Q97, P31 Removed # from DB800_SRC_STOP#, DB800_PD#
pulldown to J1H1 and J1J1 P48 Changed C5G1 to Stuffed PG55: C4G7 change from 0.1uF to 0.01uF (603269-020
C4U4, CR591, added stuffing option for turning
P50 notes changed on C2E1 and C2E7 P31 Added 10PU (+V3.3S) to CLK_MCH_OE# CAPC,X7R,0603,50V,10%,.01UF.Normal).
on/off docking switches. P52 Renamed R1B3-R2P16 P49 Added CR4H1
Page 27: Removed the docking circuitry for P20 Cleaned up resistor properties, P46 Renamed C5N4-C5B18 P34 Changed Q7M1 to BSS138, Added R7A23
added table ALL UPDATED CACHE P33-34 Changed stuffing notes for R7A20, R7M11
HD_Audio. This includes removing U11, U12, R9787, Changed R3Y3 to R3J1 P32 Changed ref des in mode note
P7,15 Added # to net MCH_ICH_SYNC
m
R2604, R2606, R2605, R2607, R9788, R9785, J25, and P32 added 0 ohm res to PM_THERM# Changed C1U1 to C1F2 P10 Changed C4T10 to .47uF, C4E2 to .22uF
shorting R9786 and R9789. P5 removed R2437, modified no_stuff note P15,29 Added GNT5_SPI net
P32,35,38 Changed KBC_A20GATE to H_A20GATE Changed R2Y3 to R3Y6 P24 Changed the fab ID to fab 3
C P16 Changed R9E1 to 8.2K P56 Changed R3J1 to R3J2 P2 Changed Voltage rail table C
P32 Changed R9881-6 to 10K and pulled up P33 Updated IPN for new Tekoa rev
e
P5 Removed J103,R9708,R9710
to +V3.3A P15 Added note for SPI flash sharing Rev 0.93 P39 Added PATA Hotswap note
P32 Added 10kPU to pins 49 and 69 U9H1 P14 Changed R2380 to 332K ALL Updated IRF7822 symbol. P44 Added SATA Hotswap note
P32 NO_STUFFED C9058 P3 Changed R3R1 to 75 ohm. P30 Moved SRC6, SRC6# to SRC5, SRC5#
P32 Changed net connected to R7A2 to P35 Updated Symbol J5 P32,24 Changed R9W2-3, R9G6 to 1.4k. P2 Added J9G3 to jumper table
h
KBC_PROG_TX# P20 Changed U2M1, U2A1 to TLV2462. P51 Changed C2B8 to 0.01uF
P Replaced C9046 with 470uF P18 Changed video bandwidth stuffing note. P30 Added J1F9
P47 Moved R9922 to P32 P14 Removed R6V10, changed R6V9 to 56, R6V7 to P9 Changed connection for C4D1-3, C5D2-3. P31 Changed R7P3 to 15 ohm
P10 Added BSS138 to V3S_TVDAC_LDO P17 Moved C7H2 to other side of L6H1. P15 Changed R7U9 pu to +V1.5S_PCIE_ICH
P32 Added diode to ARX_PWROK 24.9 P16 Changed R9E1 to 8.2k. P5 Changed R3N3, R3N8 TO 499 OHM
c
P3,37 changed CPU PWRGD topology
P54 Pulled Q100pin3 up to +V5SB_ATXA P3,37 Moved R33 and note to Page 3 P44 NO_STUFFED TP9H1 ECO 214 ALL Removed the X designation for sockets
P54 Pulled R9W8 up to +V5SB_ATXA P3 Swapped connections on pins A21,A22 P15,28,33 Renamed PCIE nets. ALL Replaced 679195-003 with 108426-131, 10UF caps
P29 Fixed shorts on U6, U3A1 P32 Changed R14-5 to caps P32 REfreshed U9H1 symbol. P54 Changed C2V2 to .33UF
ALL PAGES Named all unnamed nets P32,50 Removed extra PU for SMB_BS_ALERT# P18 Changed stuffing in Video bandwidth table. P5 Changed R9H9 to R9G18 in note
s
P58 Removed R2996,3001, and 3007 P48 Implemented changed to U5F1 power P33 Removed probing notes
P63 Updated MCH_RSVD 12-15 circuit and P48 Implemented changed to U4B1 power P33 Replaced U8A1 with C79969-001. P33 Changed R8M6 to 3k and pulled up to +V3.3
P46 changed loadline on 1.8 VR P31 Updated U7D1 symbol. P52 Added R2C6, R2P17 for Phase2 operation
-
notes
P45 Removed R7 and shorted pins 10,11 P48 Changed R5U9 to 14.7k P54 Added R5W4, R3J3. P52 Changed R2C6 to R2C7
(spare gate) P3 Added header for ACLKPH and DCLKPH P21 Swapped C4B14, C4B16, C5R1 with C4C11, C5C9, P7 Added R6E4, R8E5
P33 Updated stuffing table C5B17. P51 Added R1C1
P32-33 Updated LAN symbol to 0.25 P3,37 Updated H_PWRGD circuit P49 Changed R4H10 to 29.4K. IPN= C63246-124. P51 Added J2B2
P45 removed off page con VID_COMP P30,31,33 Changed the conection of CLK_REQ#_LAN, CLK_PCIE_LAN,
p
P51 Conected R2B9 to +VDC_PHASE
P10 Delete FB4F1, FB5F1, FB5F2 P30 Updated FSB Freq table P46 Changed R5N1 and R4N1 from 10K to 1K. IPN= CLK_PCIE_LAN#
P10 connect all four lines on that P30 Updated FSA table 202285-049. P7 Removed R4R3, R5R2 created TP's
+V3.3S_TVDAC together, then add 10uF P17 Connected pin E3 to +V3.3A P48 Changed R5U9 and R5V16 from 10K to 1K. IPN= P52 Changed note to 2-phase from phase2
P21-2, Changed conection of PM_EXTTS#[0:1] from 202285-049. P20 Inplemented new DCON curcuit
cap for the shared rail
o
P20 Add R2A6 (IPN A36093-027, 0402 5% ,100K) P32 Inplemented new DCON curcuit
PG 31: Update DB800 pinout to rev 2 & fixed pin 120 to pin 50 P39 Implemented changes to PATA_PWR_EN#
pulldown on TV_DCONSEL0. ADD R2M9(IPN A36093-027
B P34 Changed note by R9756, Moved R9756 to right P44 Implemented changes to SATA_PWR_EN# B
t
all connections ,0402, 5%, 100K)) ON TV_DCONSEL1.
PG 49 & 54: Replaced 3456 FETs with 3442BDV P51 Changed values of C2N3,C2B6,C2N4,R2N9,R2N3,C2C3
side of R7A16 P33 and 34 Updated stuffing optoin to support P31 Changed ref desig R5H14 = R6D30, R5H15 = R6D31, R5H27 =
FETs
PG 50: Changed battery charger output caps P50 Changed the value of R1Y2, R2Y2 Tekoa. R6D32, R5H28 = R6D33
from ceramic to poscaps P48 DELETED R5U8, R4U9 P54 Changed C2V2 to .33UF
p
PG 50: Changed OCP resistors in battery P46 DELETED R5N1, R4N1 P3 Added no stuff TPs for impedance coupons P7 Removed R4R3, R5R2 created TP's
charger to correct values (R2W4 & R2W13) p128 Added 0 OHM RES TO P9 J1F3 P49 Renamed +VBS, +VBATA. P24 Changed the fab ID to fab 3
P10 Stuffed R4F2 P49 Moved Q4H1 to connect to U3H1p16, Added CR3W5 ALL Reved to 1.301
PG 50: Changed C2H1 from 2220 to 1210 footprint P10 Replaced C6D1, C6F1, C542 WITH 724613-036 P21 Removed C4B14, C4B16, C5B16, C5R2.
. P30 Moved SRC6, SRC6# to SRC5, SRC5#
PG 50: Added off page connector for BS_VBS_TRIP# P50 Change C2W4 to 603275-124 P30 Added J1F9
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PG 52: Changed IMVP-6 input decoupling to P37 Change R3T9 to 1K P33 Changed U8A1 to XU8A1. P44 Added SATA Hotswap note
correct poscaps P30,37 Added note for XDP stuffing P50 Added 100k PD (R3H12) to BC_SHDN. P39 Added PATA Hotswap note
PG 46: Added 0O from 0.9PWRGD to DDRVR_PWRGD P10 Moved C4E5 to pin U5E1-A6 P10 Changed R6D8 to STUFF. Changes from R1.301 to 1.401
for stuffing option P10 Moved C4E6 to pin U5E1-D2 P24 Changed R9G11 (stuff) and R9G16 (no_stuff) P24 Changed R9G11 to STUFF, Changed R9G16 to NO_STUFF
P50 Changed VBS_TRIP# to BS_VBS_TRIP# P10 Moved C4E8 to pin U5E1-AB1
.
P16 Changed R3P1 to 2K 1%
P51 Changed DPRSTP# to H_DPRSTP# P38 Removed R9G5, Added J1,R2, note P50 Changed R1W5, R1W10 to 100K. P20 Changed the note for the d-connector
P30 Changed +V3.3S_CLKRC to +V3.3S P30 Updated FSB freq notes P30 Changed BSEL notes. P20 Swapped location of Dline1/Dline3, Dline1_IO/Dline3_IO
PG09: Moved C3T1 Vccp Bulk Cap to Page 10 P3,37 Updated H_PWRGD topology P50 Moved R1V1 to other side of FET.
P50 Changed R2G2 to a 0402 P50 Changed notes for MAX8724. Changes from 1.401 to 1.501
near Vccp rail P31 Changed R7C17-18 to 0402 P50 Changed R2W1 to 6.65k. P51 Changed R2B15 to 121K, added J? and 200k res R?
PG15: Changed stuffing option so PCIE lanes P29 Moved USB_PN6, PP6 to rt side off J7E2 P50 Changed R2W2 to 1k. P35 Added PPV EEPROM Circuit
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P32 Changed BS_CHGA#, CHGB# to outputs P50 Added C1V3. P51 Implemented DLL curcuit
4
P42& 5Added
can be routed
8.2k toRS232_RI#
PU to PCIE slots 0 & 2 P37 Changed R3T9 to 1% P33,34 Stuffed R7B1,R8M1, removed NO_STUFF boxes. P33 Added R7B21, R7B22, U7B11
P42 Updated SIO symbol P29 Removed notes from rt corner P13 Connected MCH_CFG_20 to J6C1.B48. P24 Changed Fab ID to 5
P45 Changed note P14-17 Updated ICH symbol to rev 1P02 P32 Added R9A10.
P35 removed L_BKLTSEL on LPC slot P16 Connected R8B4 to +V3.3A. 5/24: PG51: Changed R2N8 from 13.7kOhm to 15.4kOhm
P35 Added L_BKLTSEL to LPC sideband header Page 9: Replace C5T2 0805 @ 10uFwith a 0603 @ 1uF P2 Corrected SMBUS address for Batt B.
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P2 added port expander info to charts P3-4,14,21-2,24,26 Added X prefix to BT5H1, U8G1, (iPN:Updated
P31 202286-685
DB800,rev
RESD, 0603, 1%, 1/16W, 15.4K)
note
cap. Part name of the 1uF cap is
P30 Added PD option for p6 U7D2 J5P1, J5N1, U2E1.
(CAPC,X5R,0603,6.3V,20%,1UF).
A A
P31 Removed CLK going to dock
P46 Put Power measurement res back on
Replace C5T4, C5T5 and C5T3 (0.1uF caps) with P26 Changed S9C1 to NO_STUFF.
P2 Added J3B1 to jumper list. Capell Valley Intel Confidential
P48 Put Power measurement res back on 0.22uF caps. Part name is
Title
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P49 Put Power measurement res back on (CAPC,X5R,0402,6.3V,_20%,0.22uF). P7 Nostuffed R4R3, R5R2.
P50 Changed PU rail for R1V2 to +VAC_IN_L Page 10: Replace C4D5 and C4D3 (10uF caps) with REV HISTORY
P30 Changed R9700 to a PD PG17: Changed ICH7 LAN power
P30 Added a 56 ohm PU to pin3 J99 22uF caps.
rail change from +V3.3A to +V3.3.
P33-34 Deleated library notes Page 10: Replace L5U1 and L6E1 (10uH inductor)
P33 Changed IPN for J5A1 Size Document Number Rev
P34 Removed T symbol by R2824 with different 10uH inductors.
P34 Removed R9750 A D13073 1.501
P35 Moved layout note closer to TPM header
P7 DELETED NETS L_VREFH, L_VREFL
5 4 3 2 1
R
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Calistoga 1.5V GMCH_CORE NOTE
The following two pages are shown as a reference to configure Calistoga for 1.5V
a
GMCH_CORE. This is only a reference for the Calistoga connections for the Napa
platform and does not detail the full procedure such as current requirements for the VR.
Replacing the Capell Valley pages with the following pages is not sufficient to enable
m
Calistoga for 1.5V operation. For complete details, consult the Napa Design Guide.
h e
s c
p -
t o
l. ap
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5 4 3 2 1
+V1.5S 3,4,6,10,14,17,30,37,45,48,53,56,58
U5E1G
AA33 VCC_0
W33 VCC_1
m
P33 VCC_2
N33 VCC_3
L33 VCC_4 VCC_SM_0 AU41
J33 VCC_5 VCC_SM_1 AT41 VCCSM_LF4
AA32 VCC_6 VCC_SM_2 AM41 VCCSM_LF5 C5D2 +V1.5S 3,4,6,10,14,17,30,37,45,48,53,56,58
o
Y32 VCC_7 AU40 C5D4
VCC_SM_3 0.47uF
W32 VCC_8 VCC_SM_4 BA34
V32 VCC_9 AY34 0.47uF
VCC_SM_5
P32 VCC_10 VCC_SM_6 AW34
N32 VCC_11 AV34 U5E1F
c
VCC_SM_7 C4T7 C4T6 C5T6 C5T2 C5T7 C5T4 C5T5 C5T3
M32 VCC_12 VCC_SM_8 AU34 AD27 VCC_NCTF0
D L32 VCC_13 AT34 270uF 270uF 10uF 1uF 10uF 0.22uF 0.22uF 0.22uF AC27 AE27 D
VCC_SM_9 20% VCC_NCTF1 VSS_NCTF0
.
J32 VCC_14 AR34 2.0V, 3.3Arms 20% AB27 AE26
AA31 VCC_15 VCC_SM_11 BA30 AA27 VCC_NCTF3 VSS_NCTF2 AE25
W31 VCC_16 VCC_SM_12 AY30 Y27 VCC_NCTF4 VSS_NCTF3 AE24
V31 VCC_17 VCC_SM_13 AW30 W27 VCC_NCTF5 VSS_NCTF4 AE23
T31 VCC_18 VCC_SM_14 AV30 V27 VSS_NCTF5 AE22
s
VCC_NCTF6
R31 VCC_19 VCC_SM_15 AU30 U27 VCC_NCTF7 VSS_NCTF6 AE21
P31 VCC_20 VCC_SM_16 AT30 T27 VCC_NCTF8 VSS_NCTF7 AE20
N31 VCC_21 VCC_SM_17 AR30 R27 VCC_NCTF9 VSS_NCTF8 AE19
M31 VCC_22 VCC_SM_18 AP30 AD26 VCC_NCTF10 VSS_NCTF9 AE18
AA30 VCC_23 AN30 AC26 AC17
it c
Y30 VCC_24 VCC_SM_20 AM30 AB26 VCC_NCTF12 VSS_NCTF11 Y17
W30 VCC_25 VCC_SM_21 AM29 AA26 VCC_NCTF13 VSS_NCTF12 U17
V30 VCC_26 VCC_SM_22 AL29 Y26 VCC_NCTF14
U30 VCC_27 VCC_SM_23 AK29 W26 VCC_NCTF15
T30 VCC_28 VCC_SM_24 AJ29 V26 VCC_NCTF16
R30 VCC_29 AH29 U26 10,58 +V1.5S_AUX
VCC_SM_25 VCC_NCTF17
P30 VCC_30 VCC_SM_26 AJ28 T26 VCC_NCTF18
N30 VCC_31 VCC_SM_27 AH28 R26 VCC_NCTF19 VCCAUX_NCTF0 AG27
M30 VCC_32 VCC_SM_28 AJ27 AD25 VCC_NCTF20 VCCAUX_NCTF1 AF27
a
L30 VCC_33 VCC_SM_29 AH27 AC25 VCC_NCTF21 VCCAUX_NCTF2 AG26
AA29 VCC_34 VCC_SM_30 BA26 AB25 VCC_NCTF22 VCCAUX_NCTF3 AF26
Y29 VCC_35 VCC_SM_31 AY26 AA25 VCC_NCTF23 VCCAUX_NCTF4 AG25
W29 VCC_36 VCC_SM_32 AW26 Y25 VCC_NCTF24 VCCAUX_NCTF5 AF25
V29 VCC_37 VCC_SM_33 AV26 W25 VCC_NCTF25 VCCAUX_NCTF6 AG24
U29 VCC_38 VCC_SM_34 AU26 V25 VCC_NCTF26 VCCAUX_NCTF7 AF24
R29 VCC_39 VCC_SM_35 AT26 U25 VCC_NCTF27 VCCAUX_NCTF8 AG23
P29 VCC_40 VCC_SM_36 AR26 T25 VCC_NCTF28 VCCAUX_NCTF9 AF23
m
M29 VCC_41 VCC_SM_37 AJ26 R25 VCC_NCTF29 VCCAUX_NCTF10 AG22
L29 VCC_42 VCC_SM_38 AH26 AD24 VCC_NCTF30 VCCAUX_NCTF11 AF22
AB28 VCC_43 VCC_SM_39 AJ25 AC24 VCC_NCTF31 VCCAUX_NCTF12 AG21
AA28 VCC_44 VCC_SM_40 AH25 AB24 VCC_NCTF32 VCCAUX_NCTF13 AF21
C Y28 VCC_45 VCC_SM_41 AJ24 AA24 VCC_NCTF33 VCCAUX_NCTF14 AG20 C
e
V28 VCC_46 VCC_SM_42 AH24 Y24 VCC_NCTF34 VCCAUX_NCTF15 AF20
U28 VCC_47 VCC_SM_43 BA23 W24 VCC_NCTF35 VCCAUX_NCTF16 AG19
T28 VCC_48 AJ23 C5D3 V24 AF19
R28 VCC_49 VCC_SM_45 BA22 U24 VCC_NCTF37 VCCAUX_NCTF18 R19
P28 VCC_50 AY22 0.47uF T24 AG18
N28 VCC_51 AW22 R24 AF18
h
M28 VCC_52 VCC_SM_48 AV22 AD23 VCC_NCTF40 VCCAUX_NCTF21 R18
L28 VCC_53 VCC_SM_49 AU22 V23 VCC_NCTF41 VCCAUX_NCTF22 AG17
P27 VCC_54 VCC_SM_50 AT22 U23 VCC_NCTF42 VCCAUX_NCTF23 AF17
N27 VCC_55 VCC_SM_51 AR22 T23 VCC_NCTF43 VCCAUX_NCTF24 AE17
c
M27 VCC_56 VCC_SM_52 AP22 R23 VCC_NCTF44 VCCAUX_NCTF25 AD17
L27 VCC_57 VCC_SM_53 AK22 AD22 VCC_NCTF45 VCCAUX_NCTF26 AB17
P26 VCC_58 VCC_SM_54 AJ22 V22 VCC_NCTF46 VCCAUX_NCTF27 AA17
N26 VCC_59 VCC_SM_55 AK21 U22 VCC_NCTF47 VCCAUX_NCTF28 W17
L26 VCC_60 VCC_SM_56 AK20 T22 VCC_NCTF48 VCCAUX_NCTF29 V17
s
N25 VCC_61 VCC_SM_57 BA19 R22 VCC_NCTF49 VCCAUX_NCTF30 T17
M25 VCC_62 AY19 AD21 R17
L25 VCC_63
VCC_SM_58
VCC_SM_59 AW19 V21
VCC_NCTF50
VCC_NCTF51 NCTF VCCAUX_NCTF31
VCCAUX_NCTF32 AG16
-
P24 VCC_64 VCC_SM_60 AV19 U21 VCC_NCTF52 VCCAUX_NCTF33 AF16
N24 VCC_65 VCC_SM_61 AU19 T21 VCC_NCTF53 VCCAUX_NCTF34 AE16
M24 VCC_66 VCC_SM_62 AT19 R21 VCC_NCTF54 VCCAUX_NCTF35 AD16
AB23 VCC_67 VCC_SM_63 AR19 AD20 VCC_NCTF55 VCCAUX_NCTF36 AC16
AA23 VCC_68 AP19 V20 AB16
VCC VCC_SM_64 VCC_NCTF56 VCCAUX_NCTF37
p
Y23 VCC_69 VCC_SM_65 AK19 U20 VCC_NCTF57 VCCAUX_NCTF38 AA16
P23 VCC_70 VCC_SM_66 AJ19 T20 VCC_NCTF58 VCCAUX_NCTF39 Y16
N23 VCC_71 VCC_SM_67 AJ18 R20 VCC_NCTF59 VCCAUX_NCTF40 W16
M23 VCC_72 VCC_SM_68 AJ17 AD19 VCC_NCTF60 VCCAUX_NCTF41 V16
L23 VCC_73 VCC_SM_69 AH17 V19 VCC_NCTF61 VCCAUX_NCTF42 U16
o
AC22 VCC_74 VCC_SM_70 AJ16 U19 VCC_NCTF62 VCCAUX_NCTF43 T16
AB22 VCC_75 VCC_SM_71 AH16 T19 VCC_NCTF63 VCCAUX_NCTF44 R16
Y22 VCC_76 VCC_SM_72 BA15 AD18 VCC_NCTF64 VCCAUX_NCTF45 AG15
B B
t
W22 VCC_77 VCC_SM_73 AY15 AC18 VCC_NCTF65 VCCAUX_NCTF46 AF15
P22 VCC_78 VCC_SM_74 AW15 AB18 VCC_NCTF66 VCCAUX_NCTF47 AE15
N22 VCC_79 VCC_SM_75 AV15 AA18 VCC_NCTF67 VCCAUX_NCTF48 AD15
M22 VCC_80 VCC_SM_76 AU15 Y18 VCC_NCTF68 VCCAUX_NCTF49 AC15
L22 VCC_81 VCC_SM_77 AT15 W18 VCC_NCTF69 VCCAUX_NCTF50 AB15
p
AC21 VCC_82 VCC_SM_78 AR15 V18 VCC_NCTF70 VCCAUX_NCTF51 AA15
AA21 VCC_83 VCC_SM_79 AJ15 U18 VCC_NCTF71 VCCAUX_NCTF52 Y15
W21 VCC_84 VCC_SM_80 AJ14 T18 VCC_NCTF72 VCCAUX_NCTF53 W15
N21 VCC_85 VCC_SM_81 AJ13 VCCAUX_NCTF54 V15
M21 VCC_86 VCC_SM_82 AH13 VCCAUX_NCTF55 U15
la
L21 VCC_87 VCC_SM_83 AK12 VCCAUX_NCTF56 T15
AC20 VCC_88 VCC_SM_84 AJ12 VCCAUX_NCTF57 R15
AB20 VCC_89 VCC_SM_85 AH12
Y20 VCC_90 VCC_SM_86 AG12 CALISTOGA_1p0
W20 VCC_91 VCC_SM_87 AK11
.
P20 VCC_92 VCC_SM_88 BA8
N20 VCC_93 VCC_SM_89 AY8
M20 VCC_94 VCC_SM_90 AW8
L20 VCC_95 VCC_SM_91 AV8
AB19 VCC_96 VCC_SM_92 AT8
AA19 VCC_97 VCC_SM_93 AR8
Y19 VCC_98 AP8 +V1.8 7,21,22,34,46,47,56,58
VCC_SM_94
w
N19 VCC_99 VCC_SM_95 BA6
M19 VCC_100 VCC_SM_96 AY6
L19 VCC_101 VCC_SM_97 AW6
N18 VCC_102 VCC_SM_98 AV6
M18 VCC_103 VCC_SM_99 AT6
L18 VCC_104 AR6 C5R4 C5R3 C5D1
VCC_SM_100
P17 VCC_105 AP6
w
VCC_SM_101
N17 VCC_106 AN6 10uF 10uF 0.47uF
VCC_SM_102
M17 VCC_107 VCC_SM_103 AL6
N16 VCC_108 AK6 Place C5D1 near
A VCC_SM_104
PLACE IN CAVITY A
M16 VCC_109
L16 VCC_110
VCC_SM_105 AJ6
AV1 VCCSM_LF2
pin BA15 on Capell Valley Intel Confidential
VCC_SM_106 Layer1
VCC_SM_107 AJ1 VCCSM_LF1
C4D1 C4D2 Title
w
CALISTOGA_1p0
0.47uF 0.47uF CALISTOGA (4 OF 6)

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
m
Layout Note:
Location of all MCH_CFG strap resistors
7 MCH_CFG_5
o
needs to be close to trace to minimize stub
5,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
c
D MCH_CFG_5 Low = DMIx2 R1D3 D
2.2K
.
High = DMIx4
NO_STUFF MCH_CFG_18 R6F1
7 MCH_CFG_12 Low = 1.05V
(VCC 1K
Select) High = 1.5V
7 MCH_CFG_13
s
R1E12
2.2K 7 MCH_CFG_18
it c
NO_STUFF
7 MCH_CFG_6 R1E11
NO_STUFF
2.2K
LOW = Moby Dick 5,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

MCH_CFG_6
HIGH = Calistoga R1D4 +V3.3S
(DDR) 2.2K
a
NO_STUFF
MCH_CFG_19 Low = Normal
(DMI LANE REVERSAL) High = LANES REVERSED
R5U3
1K
NO_STUFF
m
7 MCH_CFG_7 7 MCH_CFG_16 7 MCH_CFG_19
C C
e
Low = Dynamic ODT
MCH_CFG_7 Low = RSVD R1E3 MCH_CFG_16 Disabled R1E1
(CPU Strap) High = Mobile CPU 2.2K (FSB Dynamic 2.2K
h
High = Dynamic ODT
NO_STUFF ODT) NO_STUFF
Enabled
5,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
c
MCH_CFG_20 Low = Only SDVO or PCIE x1 is
(PCIe Backward operational (defaults)
Interpoerability High = SDVO and PCIE x1 are operating
R5F1
mode) simultaneously via the PEG port
s
1K
NO_STUFF
-
7 MCH_CFG_9
7,13 MCH_CFG_20
p
MCH_CFG_9 Low = Reverse Lane
PCIE Graphics High = Normal R1E8
2.2K
Lane operation
o
B B
pt
7 MCH_CFG_10
la
MCH_CFG_10
HOST PLL VCO Low = RESERVED R1E2
High = MOBILITY 2.2K
SELECT
.
NO_STUFF
w
7 MCH_CFG_11
w
MHC_CFG_11 Low = Reserved
A R1D5 A
PSB 4x CLK
ENABLE
High = Calistoga
2.2K Capell Valley Intel Confidential
NO_STUFF
Title
w
CALISTOGA STRAPPING

A D15378 1.501
5 4 3 2 1
5 4 3 2 1
m
PBA# C72470-101
UPHAM II
D
. c o D
it c s
802.11 BT Antenna
Antenna
BT/Calexico
a
Coexistence USB Type B
header Header
e m
Bluetooth
C
h
module
c
Side Band
mPCIe Slot 0 mPCIe Slot 2
Header
USB
- s Bluetooth
p
FPIO header
t o
B miniPCIe miniPCIe B
Power and
p
Connector Connector
Reset Logic
l. a
PCI-E Slot 0 PCI-E Slot 2
w w
CRB PCIE Slot 0 CRB PCIE Slot2
w
A A
UPHAM II
INTEL CONFIDENTIAL
PCIe mini card Interposer for Napa/Sonama Platform Title
Block Diagram
Size Project: Document Number Rev
A UPHAM II C72527 1.01
Date: Monday, February 28, 2005 Sheet 1 of 12
5 4 3 2 1
5 4 3 2 1
m
Stuffing options for Sonoma & Napa platform
Default Jumper settings: =======================================
o
=========================================== Sonoma Napa
Default Description Pg ----------------------------------------------------------------
c
----------------------------------------------------------------- R61 No_stuff 0 ohm
J6 1-2 Power to BT LDO from USB 8
.
D R54 No_stuff 0 ohm D
J10 1-X Channel data to Slot2 4 R97 0 ohm No_Stuff
J14 2-3 H/w Shutdown for BT 8
s
R98 0 ohm No_Stuff.
J11 1-X BT clk to Slot2 4
J12 1-X Channel data to slot0 3
it c
J13 1-X BT/Pri_Clk to Slot0 3
J5 1-X Power to BT LDO from V3.3A 8
SW1 1-2 Power to BT 8
SW2 1-2 RF_KILL 7 To Disconnect SMBUS
a
=========================================== ==================
. No_stuff
-------------
m
R44
R45
e
C
R62 C
Stuffing options table based upon SiWave BT spin: R63
======================================= -------------
h
First Spin Second Spin
----------------------------------------------------------------
c
R72 27 ohm 0 ohm
R74 27 ohm 0 ohm
s
R77 1.5K ohm No_Stuff
-
R91 10K ohm 10K ohm
R87 Stuff No_Stuff
p
R88 No_Stuff Stuff
R89 Stuff No_Stuff
o
R84 No_Stuff Stuff
R92 Stuff No_Stuff
t
B R93 No_Stuff Stuff B
R86 No_Stuff Stuff
p
R96 Stuff No_stuff
=======================================
l. a
This schematic is designed with the assumption that the
second SiWave BT spin will be used on first build of
Fishhook. The table above is to be used as a reference
if the first spin of the BT module is to be used.
w w
w
A A
INTEL CONFIDENTIAL
Title
Notes
5 4 3 2 1
5 4 3 2 1
m
PRSNT2#_T1 R97 0 PRSNT1#_T1 6,7,8 V3.3AUX_T1_SLOT V3.3AUX_PCIE_T1
NO_STUFF
5 V3.3_PCIE_T1
c o
1
GPIO1_T1 R50 0 RSVD1_T1 P1 R35 R33 C45 + C40
1
TDI_T1 C49 + C42 10K 0.1uF 22uF
.
D
B1 +12V_1 PRSNT1# A1 D
NO_STUFF B2 A2 0.1uF 22uF 10K NO_STUFF 10%
2
+12V_2 +12V_3 20%
Side B
10%
Side A
B3 A3
2
s
RSVD1 +12V_4 R100
B4 GND1 GND6 A4
SMCLK_PCIE_T1 B5 A5 RCLKREQ_T1 WAKE#_T1
SMDATA_PCIE_T1 SMCLK TCK 0
it c
B6 SMDATA TDI A6
B7 GND2 TDO A7
V3.3AUX_PCIE_T1 B8 A8 NO_STUFF R60 R61 PRSNT2#_T1
+3.3V_1 TMS TDO_T1 0 0
B9 TRST# +3.3V_2 A9 Napa Platform :
B10 A10 NO_STUFF CLKREQ# support,
WAKE#_T1 3.3Vaux +3.3V_3
B11 A11
a
WAKE# PWRGD PERST_PCIE#_T1 6 connected to
PRSNT2#_T1
GPIO2_T1 R49 0 RSVD2_T1 B12 A12 V1.5_T1_SLOT 6
RSVD2 GND7 REFCLK+_T1
B13 GND3 REFCLK+ A13
m
NO_STUFF PET+_T1 B14 A14 REFCLK-_T1
PET-_T1 HSO_P REFCLK- V3.3_T1_SLOT 5,6,7,8
B15 HSO_N GND8 A15
B16 A16 PER+_T1
e
GND4 HSI_P PER-_T1
C B17 PRSNT2# HSI_N A17 C
B18 A18 J3 V3.3AUX_T1_SLOT 6,7,8
GND5 GND9 WAKE#_T1 1 2
h
CH_DATA_T1 WAKE# +3.3V_1
3 RSVD1 GND7 4
Layout Note: BTCLK_IN_T1 5 6
RSVD2 +1.5V_1
c
PCIE x1 Gold Finger RCLKREQ_T1 7 8
Place decoupling caps CLKREQ# RSVD13 RF_KILL# 4,7
close to PCIe gold fingers

PCIe Slot 0 REFCLK-_T1
9
11
GND1 RSVD14 10
12
-s
J12 REFCLK+_T1 REFCLK- RSVD15
13 REFCLK+ RSVD16 14
15 16 R71
TP6 4,9 CHANNEL_DATA GND2 RSVD17 0
KEY
4,9 BT_PRI/CLK
p
5 V3.3_PCIE_T1 GPIO1_T1 17 18
NO_STUFF J13 GPIO2_T1 RSVD3 GND8 RT2_RF_KILL#
19 RSVD4 RSVD18 20
21 GND3 PERST# 22 PERST#_T1 6
o
V3.3_T1_SLOT Default Jumper setting PER-_T1 23 24
R81 .002 PER+_T1 PER_N0 +3.3V_AUX
t
for J12 and J13 is 1-X 25 PER_P0 GND9 26
C58 C56 27 28
GND4 +1.5V_2
1
B B
C21 + C30 20% 20% 29 30 SMB_CLK_T1 R44 0 SMCLK_PCIE_T1
22uF GND5 SMB_CLK
p
0.1uF PET-_T1 31 32 SMB_DATA_T1 R45 0 SMDATA_PCIE_T1
10% 10uF 10uF NO_STUFF PET+_T1 PET_N0 SMB_DATA
33 34
2
NO_STUFF PET_P0 GND10

35 GND6 USB_D- 36 USB_D-_T1 10
l. a
V3.3AUX_PCIE_T1 37 38
RSVD5 USB_D+ USB_D+_T1 10
39 RSVD6 GND11 40
TP10
41 RSVD7 LED_WWAN# 42 LED_WWAN#_T1 7
V3.3AUX_T1_SLOT 43 44
TP25 TP9 TP17 TP2 TP18 TP5 RSVD8 LED_WLAN# LED_WLAN#_T1 7
R80 .002
NO_STUFF
45 46
NO_STUFF
NO_STUFF
NO_STUFF
RSVD9 LED_WPAN# LED_WPAN#_T1 7

C60 C59 NO_STUFF
NO_STUFF
NO_STUFF
47 RSVD10 +1.5V_3 48
1
w
C55 + C28 20% 20% 49 50
0.1uF 22uF NO_STUFF RSVD11 GND12
51 RSVD12 +3.3V_2 52
10% 10uF 10uF 55 56
2
NO_STUFF GNDM1 GNDM2
w
V1.5_T1 5 PCI-e_MINI_CARD
TP15
V1.5_T1_SLOT J17
w
A A
R76 .002
C57 C35 NO_STUFF
1
2
MT1 LATCH MT4 4
5
miniPCIe Slot 0
MT2 MT5
1
C62 + C22 20% 20% 3 (GND ALL) INTEL CONFIDENTIAL

0.1uF 22uF NO_STUFF MT3 Title PCIE to miniPCIe connector
10% 10uF 10uF MINI_CARD_LATCH_ TYCO
2
NO_STUFF Size Project: Document Number Rev

5 4 3 2 1
5 4 3 2 1
V3.3AUX_PCIE_T2
m
PRSNT2#_T2 R98 0 PRSNT1#_T2 6,7,8,9 V3.3AUX_T2_SLOT
NO_STUFF
5 V3.3_PCIE_T2
c o
1
GPIO1_T2 R64 0 RSVD1_T2 P2 TDI_T2 C29 + C53 R53 R51
1
C36 + C50 0.1uF 22uF 10K
.
D
B1 +12V_1 PRSNT1# A1 D
NO_STUFF B2 A2 0.1uF 22uF 10% 10K
2
+12V_2 +12V_3 20%
Side B
10% NO_STUFF
Side A
B3 A3
2
s
RSVD1 +12V_4 R99 R48 0
B4 GND1 GND6 A4
SMCLK_PCIE_T2 B5 A5 0 RCLKREQ_T2
SMDATA_PCIE_T2 SMCLK TCK
it c
B6 SMDATA TDI A6
B7 A7 NO_STUFF NO_STUFF WAKE#_T2
V3.3AUX_PCIE_T2 GND2 TDO
B8 +3.3V_1 TMS A8
B9 A9 TDO_T2 R54 Napa Platform :
TRST# +3.3V_2 0
B10 3.3Vaux +3.3V_3 A10 CLKREQ# support,
WAKE#_T2 B11 A11
a
WAKE# PWRGD PERST_PCIE#_T2 6 connected to
NO_STUFF PRSNT2#_T1
GPIO2_T2 RSVD2_T2 B12 A12
RSVD2 GND7 REFCLK+_T2 6 V1.5_T2_SLOT
B13 GND3 REFCLK+ A13
m
R65 0 PET+_T2 B14 A14 REFCLK-_T2 Default Jumper PRSNT2#_T2
PET-_T2 HSO_P REFCLK-
B15 HSO_N GND8 A15 setting for J7 is
B16 A16 PER+_T2 V3.3_T2_SLOT 5,6,7
e
C B17
GND4 HSI_P
A17 PER-_T2 1-2 Closed C
PRSNT2# HSI_N
B18 GND5 GND9 A18
J4 V3.3AUX_T2_SLOT 6,7,8,9
h
Layout Note: WAKE#_T2 1 2
PCIE x1 Gold Finger CH_DATA_T2 WAKE# +3.3V_1
3 4
Place decoupling caps RSVD1 GND7
c
BTCLK_IN_T2
close to PCIe gold
PCIe Slot 2 RCLKREQ_T2
5
7
RSVD2 +1.5V_1 6
8
CLKREQ# RSVD13
9 10
-s
fingers J10 REFCLK-_T2 11
GND1 RSVD14
12
REFCLK+_T2 REFCLK- RSVD15 R47 0
13 REFCLK+ RSVD16 14
RSVD18_T2
3,9 CHANNEL_DATA
NO_STUFF 15 GND2 RSVD17 16 RF_KILL# 3,7
3,9 BT_PRI/CLK
p
V3.3_PCIE_T2 5 TP14 KEY
J11 GPIO1_T2 17 18
GPIO2_T2 RSVD3 GND8
19 RSVD4 RSVD18 20
o
V3.3_T2_SLOT 21 22
GND3 PERST# PERST#_T2 6
R85 .002 PER-_T2
t
23 PER_N0 +3.3V_AUX 24
C37 C44 PER+_T2 25 26
PER_P0 GND9
1
B B
C52 + C51 20% 20% Default Jumper setting 27 28
22uF GND4 +1.5V_2
p
0.1uF NO_STUFF forJ10 and J11 is 1-X 29 30 SMB_CLK_T2 R62 0 SMCLK_PCIE_T2
10% 10uF 10uF PET-_T2 GND5 SMB_CLK SMB_DATA_T2 R63 0 SMDATA_PCIE_T2
31 32
2
NO_STUFF PET+_T2 PET_N0 SMB_DATA

33 PET_P0 GND10 34
l. a
V3.3AUX_PCIE_T2 35 36
GND6 USB_D- USB_D-_T2 10
J18 37 38
TP19 RSVD5 USB_D+ USB_D+_T2 10
1 MT1 MT4 4 39 RSVD6 GND11 40
V3.3AUX_T2_SLOT 2 LATCH 5 41 42
MT2 (GND ALL) MT5 RSVD7 LED_WWAN# LED_WWAN#_T2 7
R79 .002 C26 3 43 44
MT3 RSVD8 LED_WLAN# LED_WLAN#_T2 7
C32 NO_STUFF 45 46
RSVD9 LED_WPAN# LED_WPAN#_T2 7
1
w
C43 + C41 20% 20% MINI_CARD_LATCH_ TYCO 47 48
0.1uF 22uF NO_STUFF RSVD10 +1.5V_3
49 RSVD11 GND12 50
10% 10uF 51 52
2
10uF NO_STUFF RSVD12 +3.3V_2

55 56
w
V1.5_T2 5 GNDM1 GNDM2
PCI-e_MINI_CARD
TP8
V1.5_T2_SLOT TP13 TP24 TP23 TP7
miniPCIe Slot 2
w
A A
NO_STUFF
R70 .002
NO_STUFF
NO_STUFF
NO_STUFF
C63 C61 NO_STUFF

1
C64 + C20 20% 20% INTEL CONFIDENTIAL

0.1uF 22uF Title PCIE to miniPCIe connector
10% 10uF NO_STUFF
2
10uF NO_STUFF Size Project: Document Number Rev

5 4 3 2 1
5 4 3 2 1
m
V3.3_T1_SLOT 3,6,7,8
3 V3.3_PCIE_T1
o
R82 100K
c
LDO_1.5V_RST#_T1
.
D D
EU1 3 V1.5_T1
1 16 R57 R58 NO_STUFF
s
NC1 NC4
2 IN1 OUT1 15
3 14 10K 10K
C47 IN2 OUT2
it c
4 IN3 OUT3 13
0.1uF C38 5 12 5% 5% NO_STUFF
10% 4.7uF IN4 OUT4
6 RST# SET 11
10% 7 10
SHDN# GND C34 + C27
8 NC2 NC3 9
0.1uF 15uF
a
MAX1793 17 10% 20% V3.3_T2_SLOT 4,6,7
THRMGND
MFG P/N (MAX1793EUE-15)
e m
C R66 R67 C
NO_STUFF
10K 10K
h
5% 5% NO_STUFF
c
4 V3.3_PCIE_T2
-s
R75 100K
LDO_1.5V_RST#_T2
p
EU2 4 V1.5_T2
1 NC1 NC4 16
2 15 R69 R68 R55 R56
IN1 OUT1
o
3 IN2 OUT2 14
C46 C39 0 0 0 0
t
4 IN3 OUT3 13
0.1uF 4.7uF 5 12 NO_STUFF
B
10% 10% IN4 OUT4 NO_STUFF B
6 RST# SET 11
p
7 10 NO_STUFF
SHDN# GND C25 + C33 NO_STUFF
8 NC2 NC3 9
0.1uF 15uF
l. a
MAX1793 17 10% 20%
THRMGND
MFG P/N (MAX1793EUE-15)
No Stuff resistors added for
w
any future signal strapping requirements
w w Title
miniPCIe Card Slot Power Control
Size Project:
A UPHAM II
INTEL CONFIDENTIAL
Document Number
C72527
Rev
1.01
A

5 4 3 2 1
5 4 3 2 1
3,5,7,8 V3.3_T1_SLOT
R41
17.8K
1%
3,7,8 V3.3AUX_T1_SLOT
o m
c
3,7,8 V3.3AUX_T1_SLOT
C15
.
D D
3 V1.5_T1_Slot 0.1uF
10%
s
R31 R25 C9
R40 0.1uF
R43 4.99k_1% 10K 10K 10%
it c
5
22.1K U4 U1
1% MECH_RST_T1#1
MR# VCC 10 3 PERST_PCIE#_T1 1
PG_3.3_T1 2 9VAUX_RST_T1# R19 0 4 AND_PERST_T1
PG_1.5_T1 IN1 RESET# R23 0 PWRGD_T1
3 IN2 PF1# 8 2
4 7
a
IN3 PF2# 74AHC1G08 R24
5 6
3
GND PF3# 0 TP1
R42 MAX6714 R_MECH_RST_T1# 5%
20k_1% TP3
m
0.62 Internal Threshold NO_STUFF NO_STUFF
Setting
R22 0 MECH_RST_T1# PERST_PCIE#_T1 R17 0
e
PERST#_T1 3
C NO_STUFF C
NO_STUFF R16 0
8 PWRGD
NO_STUFF
4,5,7 V3.3_T2_SLOT
c h
-s
4,7,8,9 V3.3AUX_T2_SLOT
R36
17.8K
p
1%
4,7,8,9 V3.3AUX_T2_SLOT
o
4 V1.5_T2_Slot C14
R34 0.1uF
t
10% R30
B
R37 10K C10 B
10K
p
R39 4.99k_1% 0.1uF
5
22.1K U5 U2 10%
1% MECH_RST_T2#1
MR# VCC 10 4 PERST_PCIE#_T2 1
l. a
PG_3.3_T2 2 9VAUX_RST_T2# R29 0 4 AND_PERST_T2
PG_1.5_T2 IN1 RESET# R27 0 PWRGD_T2
3 IN2 PF1# 8 2
4 IN3 PF2# 7
5 6 R_MECH_RST_T2# 74AHC1G08 R15
3
GND PF3# R28 0 MECH_RST_T2# NO_STUFF 0 TP11
R38 MAX6714 5%
w
20k_1% NO_STUFF
0.62 Internal Threshold TP12 NO_STUFF
Setting PERST_PCIE#_T2 R14 0
PERST#_T2 4
w
NO_STUFF
R13 0
8 PWRGD
NO_STUFF
w
A A
Voltage Threshold INTEL CONFIDENTIAL

Vth = 2.9V for 3.3V, 3.3Vaux Title
Slot Power Good Monitor
Vth = 1.3V for 1.5V Size Project:
A UPHAM II
Document Number
C72527
Rev
1.01
5 4 3 2 1
5 4 3 2 1
m
V3.3_T1_SLOT 3,5,6,8 3,6,8 V3.3AUX_T1_SLOT V3.3_T2_SLOT 4,5,6 4,6,8,9 V3.3AUX_T2_SLOT
c o
R1 .002 SEL_AUX_T1 R12 0.002 R18 .002 SEL_AUX_T2 R26 0.002
.
D D
NO_STUFF NO_STUFF
s
BIAS_WAN_T1 BIAS_WAN_T2
it c
2 1 LED_WWAN#_T1 3 2 1 LED_WWAN#_T2 4
CR7 CR10
R4 165 1% GREEN R11 165 1% GREEN
BIAS_LAN_T1 2 1 LED_WLAN#_T1 3
a
BIAS_LAN_T2 2 1 LED_WLAN#_T2 4
m
CR8 CR9
R6 165 1% YELLOW R5 165 1% YELLOW
e
C C
c h
BIAS_PAN_T1 2 1 BIAS_PAN_T2 2 1
LED_WPAN#_T1 3 LED_WPAN#_T2 4
CR3 CR4
R3 165 1% GREEN R2 165 1% GREEN
s
V3.3AUX_T1_SLOT 3,6,8 V3.3AUX_T1_SLOT 3,6,8
-
C23
p
R59
0.1uF 10%
165
o
U6
LED Status
t
1%
1 GND VCC 4 ===================================================================
B CR11 B
Description ON Slow Blink Intermittent Blink
p
BIAS_LED_RF
2 1 SW_RF_KILL# 2 3 ------------------------------------------------------------------------------------------------------
IN OUT RF_KILL# 3,4
CR7 W-WAN T1 Ready to Tx/Rx NA Activity prop to Tx/Rx Speed
l. a
MAX6816 CR10 W-WAN T2 Ready to Tx/Rx NA Activity prop to Tx/Rx Speed
GREEN
CR8 W-LAN T1 Ready to Tx/Rx Not associated Activity prop to Tx/Rx Speed
SW2 CR9 W-LAN T2 Ready to Tx/Rx Not associated Activity prop to Tx/Rx Speed
1 Debounce for RF_KILL Switch C18 CR3 W-PAN T1 Ready to Tx/Rx Not associated Activity prop to Tx/Rx Speed
2 0.1uF CR4 W-PAN T2 Ready to Tx/Rx Not associated Activity prop to Tx/Rx Speed
w
3 10%
CR11 RF_KILL Disable RF Tx
C19 CR12 BT 3.3V 3.3V for BT available
SPDT_SLIDE 0.1uF ===================================================================
w
10%
w
A A
INTEL CONFIDENTIAL
Title Status indicator LEDs for mini cards
5 4 3 2 1
A B C D E
+V5A R94
m
DELAY_RST
WDS_RESET_N 9
8Pin_HDR
J7 4.7K 5%
2
1 TP_BT_WAKE V3.3AUX_T2_SLOT 4,6,7,9 BT3.3V 9 R96
2 BT_ON C12 C13 5.49K
RST#
c
3 TP_BT_DETACH 0.1uF 4.7uF 1%
1
4 CARD_ID#0 10% 10% + C8 C6
.
4
NO_STUFF 4
5 CARD_ID#1 22uF 0.1uF C11 C7 3 1
10% 0.01UF 0.01UF VCC GND
6 PWRGD 6
2
s
7 10% 10% V3.3_T1_SLOT 3,5,6,7
U9
8
it c
MAX809
CARD_ID#0 R7 R9
1K 1K
CARD_ID#1 1% 1%
Bluetooth Sideband NO_STUFF
a
J5: Default setting 1-X
CARD_ID#0
3.3VAUX (3.3Always) connected to
3,6,7 V3.3AUX_T1_SLOT R10 R8
+V5A Pin1 supplied from PCI-e connector Slot1 100 100 CARD_ID#1
1% 1%
m
NO_STUFF
4,6,7,9 V3.3AUX_T2_SLOT J5
R32 100K
e
3 10 USB5V_FPIO BT_VREGRST# BT_VREGOUT 3
USB5V 9 J6 Default jumper setting for
h
1 2 SW1 is:
3 4
2 - 1 Closed by default TP4
c
5 6 U3
7 8 1 16 BT3.3V 9
V3_PWR NC1 NC4
2 15
s
8Pin HDR IN1 OUT1 NO_STUFF
3 IN2 OUT2 14
SPDT_SLIDE
-
Default jumper setting for J6 is: 4 IN3 OUT3 13
1 - 2 Closed by default C3 5 12 1
4.7uF IN4 OUT4
6 RST# SET 11 2
p
+V5A connected to Pin3 comes 10% BT_SHDN# 7 10 + C17 C16 C5 3
SHDN# GND 15uF 2.2uF 4.7uF SW1
from USB FPIO connector 8 NC2 NC3 9
20% 10% 10% SPDT_LOW
to
3.3VAUX (3.3Always) connected to MAX1793 R52
Pin5 comes from PCI-e connector 475
R21 MFG P/N R20 1%
2 2
+V5A connected to Pin7 needs 10K (MAX1793EUE-33) 10K
p
5% 5% LED
Bluetooth Sideband Cable
2
CR12
la
J34_PIN1 BT3.3V 9
GREEN
2
BT_ON
1
J14 C48 C54
CON3_HDR 100uF 0.1uF
20% 10%
1
w
R46
1M
Default jumper setting for
w
J14 is:
2 - 3 Closed by default
w
1 1
INTEL CONFIDENTIAL
Title
BT Voltage Sources
A B C D E
A B C D E
USB5V 8
m
J16 Place the caps and resistors TP20
CLK_32IN AUX_UART_TXD
BT_PRI/CLK
1 2 NOTE: as near to Bluetooth Module NO_STUFF
o
3 4
CHANNEL_DATA 5 6 HCI_UART_TXD USB D+ and D- traces need to Connector as possible. R83 .002
AR_GPIO_2 HCI_UART_RTS USB5V_CONN
7 8 have 90 Ohm differential
c
AR_GPIO_3 9 10 J15
GPIO_4 impedance USB_D+_PULLUP R77 0
.
4
11 12 1 VBUS 4
CODEC_SYNC 13 14 HOST_WAKEUP NO_STUFF 4 GND
CODEC_BCLK 15 16 USB_D- R72 0 D- 2 D-
s
CODEC_PCMIN 17 18 USB_D+ R74 0 D+ 3 D+
19 20 5 CASE1
VBB_RDY C31 C24
it c
21 22 6 CASE2
WDS_RESET_N 23 24 3.3pF 3.3pF
7.50% 7.50% USB_Type_B
Default jumper 2x12-HDR NO_STUFF NO_STUFF NO_STUFF
setting for J16 is:
a
All Open
J9
TP21 BT_PRI/CLK 1
m
CHANNEL_DATA 2
BT3.3V 8 NO_STUFF AR_GPIO_2 3
Calexico/BT sideband AR_GPIO_3 4
e
3 BT3.3V_TEST 5 3
connector
R90 10K
NO_STUFF
h
R95 .002
R91 10K
c
J8
CLK_32IN TP16 R73 0
1
2
s
R87 0 BTSP1_1 3
BT_PRI/CLK_BT NO_STUFF R88 0 NO_STUFF BT3.3V 8
-
4
5 4,6,7,8 V3.3AUX_T2_SLOT
AR_GPIO_3 6 5
p
GPIO_4 7
CODEC_SYNC 8 2 BT_PRI/CLK_BT
CODEC_BCLK 9 4
to
CODEC_PCMIN 3,4 BT_PRI/CLK
10 1
11 U7 OE
R89 0 BTSP1_2 12 NO_STUFF
2 CHANNEL_DATA_BT NO_STUFF R84 1K BTSP2_1 3 2
13
p
1% 14
R92 0 BTSP1_3 15
AR_GPIO_2 NO_STUFF R93 0 BTSP2_2 16
la
BT3.3V 8 TP22
17
VBB_RDY 18 4,6,7,8 V3.3AUX_T2_SLOT
19
.
8 WDS_RESET_N
20 NO_STUFF
AUX_UART_TXD 21 NO_STUFF 5
HCI_UART_TXD 22 3,4 CHANNEL_DATA
w
HCI_UART_RTS 23 2
24 4 CHANNEL_DATA_BT
HOST_WAKEUP 25 1
26 OE U8
w
USB_D+_PULLUP 27
USB_D- 3
28
USB_D+ 29
R78 0
w
1 30 1
MINI_CARD
R86 0
INTEL CONFIDENTIAL
Title
BT Connectors
A B C D E
5 4 3 2 1
o m
. c
D D
8 USB5V_FPIO
it c s
a
J2
1 2
3 USB_D-_T1 3 4 USB_D-_T2 4
m
3 USB_D+_T1 5 6 USB_D+_T2 4
7 8
10
e
1
1
C C
CR5 CR1 USB_2X5-Header CR2 CR6
h
2
2
c
Clamping-Diode Clamping-Diode Clamping-Diode Clamping-Diode
- s
o p
t
B B
USB5V_FPIO 8
p
1
l. a
+ C2 C1
22uF 0.1uF C4
10% 0.01UF
2
10%
NO_STUFF
w w
w
A A
INTEL CONFIDENTIAL
Title
USB FPIO Header
5 4 3 2 1
A B C D E
o m
. c
4 4
Bluetooth Antenna and

BT Antenna Connector
Calexico Antennas
it c s
A3
a
A1
2 GND
A4 2 3
GND GND2
1 ANT_IN 3 GND2 4 GND3
m
2 GND 4 GND3
3 GND2
4 TYCO 100215 ANT.
e
GND3
ANT_CONN
3 TYCO 100215 ANT. 3
BLUETOOTH ANT.
h
A2
c
J1
GND 2 2 GND
1 3
s
ANT GND2
GND2 3 4 GND3
-
BT_ANT_CONN
TYCO 100215 ANT.
o p
t
2 2
l. a p
w w
w
1 1
INTEL CONFIDENTIAL
Title
Calexico and BT Antennas
A B C D E
5 4 3 2 1
m
Revision History from Upham I to Upham II Design Details
o
PCIe to miniPCIe
c
1) Added U9 Debounce circuitry for the RF_KILL# switch and routed to RSVD18 1) Each PCIe connector provide 3.3V (3A) and 3.3VAux (500mA)
.
D of both the miniPCIe connector D
2) Each miniPCIe connector gets 3.3V directly from PCIe connector and 1.5V
2) Changed V3_Always on the sideband header J6 to +V5A in accordance through MAX1793 LDO
s
with the Napa Platform
3) The PERST# signal is provided to each miniPCIe connector using MAX6714 to
3) CLKREQ signal from each minicard routed to respective PRSNT2# signals
it c
validate 3.3V and 1.5V
4) Added J15 so that V3.3Aux from PCIE slot 0 could be routed to BT LDO also 4) The PWRGOOD from the MAX6714 is ANDed with PCIe PERST signal to
generate miniPCIe PERST.
5) Changed the USB connector for the BT so that AMP USB connector can be used
5) LEDs are provided for LAN, WAN and PAN signals from miniPCIe connector
a
6) USB FPIO carries two USB signals connected to the miniPCIe connector
7) RCLKREQ_T1 and RCLKREQ_T2 are connected to PRSNT2#_T1 and PRSNT2#_T2
m
respectively for testability of CLK_REQ function
Bluetooth
e
C C
1) Power to Bluetooth module 3.3V is either of the following
h
a) Default by USB 5V through MAX1793 LDO
c
b) 3.3V Aux from PCIe through MAX1793 LDO
-s
c) 5V by the Vv/CRB sideband cable and through MAX1793 LDO
2) Power shutdown to BT can be done either by jumper or by software
using Sideband cable
p
3) WDS_RESET is provided to BT through MAX809 validating BT power 3.3V
o
4) USB Type B connector is used to provide USB signals to BT module
t
B
5) BT/Calexico signal are used for handshake between Calexico and BT B
p
6) Channel_data connected to RSVD1 pin of miniPCIe connector slot1 and Slot2 is fed to
BT through a OP-AMP Buffer
l. a
7) BT_Clk is connected to RSVD2 pin of miniPCIe connector through a OP-AMP buffer
Handshake signals
1) RSVD1 and RSVD2 of PCIe slot1 connected to miniPCIe slot1 RSVD3 and RSVD4
w
for future enhancement
2) RSVD1 and RSVD2 of PCIe slot2 connected to miniPCIe slot2 RSVD3 and RSVD4
for future enhancement
w w Title
Block Schematic
Size Project:
A UPHAM II
INTEL CONFIDENTIAL
Document Number
C72527
Rev
1.01
A

5 4 3 2 1

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5 4 3 2 1

MDC 1.5 80-83

FWH PG 35 DOCK Title

Wake Events State Supported

SIGNAL SLP SLP +V*A +V* +V*S Clocks

ADSTB[1]# PROCHOT# D[3]# D[35]#

Leave escape routing on TP_A37# RSVD[05] RSVD[13] TP_SPARE1

Size Document Number Rev

Yonah Ball-out Rev 1.0

Size Document Number Rev

Note: No-Stuff R3N5 for normal

C Thermal Diode Conn C

Size Document Number Rev

H_SLPCPU# E3 H_CPUSLP# 3,35

Size Document Number Rev

U5E1C R5E1 24.9 1%

H28 K30 AA40 PEG_TXN13

TP_MCH_NC5 BA39 NC5 DMI_TXN_2 AG37DMI_RXN2 R5T5 150 1%

BA2 C26 P36 PEG_TXP8

R5P2 10K PM_EXTTS#0

Size Document Number Rev

SA_DQ31 SA_MA_0 SB_DQ31 M_B_A[13:0] 22,23

AP9 SA_DQ44 SA_MA_13 AV12 AK13 SB_DQ44 SB_MA_12 AY27

Size Document Number Rev

Size Document Number Rev

BAT54 Q4U1 100

Size Document Number Rev

LOW = Moby Dick 5,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

Size Document Number Rev

Size Document Number Rev

Cap values depend on Xtal

Y5 INTRUDER# LDRQ0# AC3 ICH_DRQ#0 42

0.1uF R7J3 C7H6 3900pF SATA_RXP2_C AE7 AD12 IDE_PDD6

54 ATA_LED# 4 31 CLK_PCIE_SATA AE1 SATA_CLKP DD11 AC14

the ICH-7 M and cap on the "N" DD15 AC15

RSVD9 15 16,33,58 SMB_CLK 3 SCL0 SCL2 8 SMB_CLK_S2 21,22,23

Direct Media Interface

28 PCIE_RXN2_SLOT1 H26 PERn2 DMI1RXN Y26

ICH7 Pullups RP9C1B 2 7 8.2K

13,14,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A SMC_EXTSMI#_R

+V3.3A 13,14,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 R8F11 SMC_WAKE_SCI#_R

Date: Wednesday, July 20, 2005 Sheet 16 of 60

+V5S 5,10,18,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56 Layout Note:

AF10 Vcc1_5_A[15] Vcc1_5_A[23] G17

SMC0402 H7 +V1.5S 4,10,27,48,56,58

ICH7M REV 1.02 EDS

Size Document Number Rev

Date: Wednesday, July 20, 2005 Sheet 17 of 60

U7D11 0.1uF CRT_Q_VSYNC R7E1 39 CRT_R_VSYNC

SN74LVC2G125 Size Document Number Rev

R5V11 100K L_VDDEN_LPP_D# 24 VSS_SHIELD1

+V3.3S 5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 LVDS,CONN44

R6E3 100K L_VDDEN_D#

Size Document Number Rev

VDD IO_0 DLINE2_IO R2A17 10K DLINE2

Size Document Number Rev

Layout Note: Place these Caps near So-Dimm0.

Size Document Number Rev

Size Document Number Rev

DDR2 Thermal Sensor So-Dimm 0 & 1

M_A_A0 M_A_A[13:0] 8,21

Size Document Number Rev

+V5_PCISLT3 Optimize routing 2

SIGNAL SLP SLP +VA +V +V*S Clocks