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Schwartz
Electrical & Computer Engineering Revision 3 8-Oct-04
Page 1/4 Lab 4: 8-Bit Arithmetic Logic Unit (ALU)
PURPOSE figure as a structural file using port map
The purpose of this lab is to study the Arithmetic statements. If this approach is used, create
Logic Unit (ALU) with an Accumulator Register. separate VHDL behavioral descriptions of the
This ALU will be used in later assignments. multiplexers (of 2 different sizes). The
multiplexers should be written using the VHDL
“with...select” statement. These design files will
MATERIALS be used together with the add1 file from Lab 3
• Bin-Tek BT-U Board
to create the structural description of alu1.
• ByteBlaster Cable
• SPDT switch, 2 resistors
Compiling and testing proceeds as for other
• Oscilloscope (in lab) complex projects. Be sure to designate the
• Logic Analyzer (in lab) project correctly -- use “Project | Set as Top
Level Entity” to designate the top-level network
as alu1. (A short-cut key sequence is
PRE-LAB REQUIREMENTS Ctrl+Shift+J.)
1. Prepare a VHDL design file that describes a 1-
bit Arithmetic Logic Unit (ALU). The VHDL architecture body may also be
written in behavioral form using only
The ALU supports the operations shown in the
assignment and with...select statements.
table below. A 3-bit input fsel selects the
Organize the file into sections separated by
function to be performed. The 1-bit output of the
comments. Assume that there is a section for
ALU is f. The adder signals from the previous
each function depicted in Figure 1. Note that the
lab, a, b, cin, blk_g, and blk_p are also needed in
subtract function in Figure 1 is implemented by
the ALU. Some new inputs and outputs to
inverting the a input as it is sent into the adder.
support the shift functions are also needed. Use
The AND, OR, and XOR functions have already
sli and sri as shift-left and shift-right inputs,
been created in implementing the adder
respectively. The shift-left and shift-right
(remember the g, p, and the s outputs). The shift
outputs will be called slo and sro. The entity
left and shift right operations can be
statement for our component should be called
implemented merely by rerouting the bus
alu1. Your VHDL file should always begin with
carrying the b input to the left or right one bit
a comment containing your name and your
position. When all of the equations have been
section number as well as a canonical truth table
written for each section, build the multiplexer as
that specify the values of all of the outputs
shown at the bottom center of Figure 1 to select
relevant to that function as a function of all of
(based on fsel) the desired result. Notice that the
the inputs.
adder and subtracter fit into this model as a
FSel FUNCTION single unit. Whether using the structural or
0 Add with carry input (f = a + b + ci) behavioral VHDL description, name the project
1 Subtract (b-a) with borrow (f = /a + b + ci)* and assign the device appropriately. Compile
2 Bit-wise AND (f = a and b) and remove any errors until a suitable VHDL
3 Bit-wise OR (f = a or b)
file is produced. Prepare suitable test vectors and
4 Bit-wise XOR (f = a xor b)
5 Shift left (f = b << 1) simulate to verify that the output is identical to
6 Shift right (f = b >> 1) the truth table specified in the design. Please
7 Zero (f = 0) capture the test vectors in a .tbl file for use in the
* The ci for subtraction is the borrow input. lab write-up.
The ALU may be conceptually viewed as shown
in Figure 1. It is possible to implement this
University of Florida EEL 4712 - Fall 2004 Dr. Eric M. Schwartz
Electrical & Computer Engineering Revision 3 8-Oct-04
Page 2/4 Lab 4: 8-Bit Arithmetic Logic Unit (ALU)