ESSCIRC 2002
Low-Voltage CMOS Charge-Pump PLL Architecture for Low Jitter Operation
Adrian Maxim
Crystal-Cirrus Logic, Austin TX, USA, Email: adrian@crystal.cirrus.com
Abstract
This paper presents circuit level techniques that
reduce both intrinsic and supply or substrate injected
noise of charge-pump PLLs operating in the noisy
environment of mixed analog-digital ICs. Using a ripple-
pole-less sample-reset loop filter provides a staircase
shaped oscillator control current that reduces the
reference spur, and a nearly 90° phase margin that leads
to a negligible jitter peaking and locking overshoot. A
fully differential loop filter having low-VT devices and
accumulation MOS capacitors in the signal path was
used to minimize the substrate and supply injected noise.
Oscillator’s PSRR is improved using differential
inverters and clamping its amplitude to supply
independent voltage levels. The proposed methods are
validated through measurements on two PLLs: a
reference one using a feed-forward architecture and a
low jitter one using a sample-reset architecture.
1. Introduction
The substrate and supply injected noise has a
significant, and in many cases dominant contribution to
the output jitter of actual PLLs operating in large mixed
analog-digital ICs. Optimising the jitter performance
requires the development of new architectures for the
PLL building blocks that assure a higher noise rejection.
A standard charge-pump PLL consists of: an input
divider (div.N), a phase-frequency detector (PFD), one
or more charge-pumps (CP), a loop filter (LF) with the
phase integration and proportional paths, a voltage or
current controlled oscillator (VCO/ICO), an optional
output comparator (COMP) that sharpens the edges and
minimizes the load on the oscillator, and a feedback
divider (div.M). Since the introduction of charge-pump
PLL numerous architectures were proposed for its
components: single ended [1] or differential [2-6],
voltage [1, 3] or current mode [2, 4-6].
This paper analysis the different existing architectures
of the main PLL building blocks (CP, LF, ICO) from the
low jitter operation perspective and proposes further
enhancements that minimize the PLL output jitter.
2. Charge-pump architectures
In actual high speed PLLs the reference spur and
clock skew are mainly determined by the charge-pump
non-idealities. The major phase error contributors are:
the leakage currents, the mismatch between pump-up and
pump-down currents, and the switching time mismatch
between the Up and Down current pulses. The analytic
expression of the phase error is:
∆Φ = ∆Φleakage + ∆Φcurrent + ∆Φtime =
(1)
 
I ∆I Tswitch ∆T ⋅ Tswitch 
= 2π ⋅  leak + ⋅ + 
 I cp I cp Tupdate Tupdate2 

where Ileak is the leakage current, Icp is the charge-pump
current, Tupdate is the loop update period at the PFD input,
Tswitch is the charge-pump switching time and ∆T, ∆I are
the time and respectively current mismatches. The
resulting reference spur is given by:
 ∆Φ M ⋅ BW   f 
Pspur = 20 ⋅ log ⋅  − 20 ⋅ log update  (2)
 2 f update   f pole 
   
where M is the feedback divider ratio, BW is PLL’s
bandwidth, and fpole is its ripple filtering pole (if present).
The charge-pumps differs by the position of the
switches with respect to the current mirrors. A first
category is the drain-switch [3], their main drawbacks
being the high clock feed-through (the switch is directly
connected to the loop filter capacitor) and the high
amplitude current spikes that appear in the first moments
of pump-up/down due to triode region operation. In high
frequency, high bandwidth PLLs the loop filter
capacitors become comparable with the device parasitic
capacitances, making the charge sharing effect a
significant source of errors. Dummy switches can be
introduced to minimize the charge sharing effect, the
price paid being an increased clock feed-through. The
gate-switch charge-pump eliminates the current spikes by
keeping the current mirrors either in off or saturation
state. Its downside is the low speed due to the high gate
capacitance connected at the switching nodes. A higher
switching speed is achieved with a differential switch
that uses the current steering technique. The inherent
mismatch between the NMOS and PMOS switches can
be eliminated with an all NMOS switches charge-pump
[2]. The drawback of this architecture is the lower speed
due to the turning-off of the PMOS current mirror. Fully
differential charge-pumps are preferred in low-voltage
low-jitter PLLs due to their increased supply and
substrate noise rejection and higher voltage swing [5].
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 Fig.1 Differential source-switch charge-pump
These advantages are obtained at the expense of a higher
power dissipation, larger area of on-chip capacitance
(need two loop filters) and more complex circuitry. The
fastest switching is achieved by using the source-switch
charge-pump in which the switch is connected to a low
impedance node. The devices are either off or in
saturation, eliminating the current spikes. The clock
feed-through is reduced due to the isolation between the
switch and the loop filter capacitors.
Present design uses a differential source-switch
configuration presented in Fig.1. Two source-switch
charge-pumps (M1-M6 and M7-M12) are operated in
opposition of phase (when one is pumping up, the other
one is pumping down) in order to assure a differential
operation of the loop filter, and hence minimizes the
supply and substrate injected noise. Using high swing
cascoded current mirrors on both NMOS and PMOS
sides significantly improves the PSRR, while allowing a
low voltage operation (1.5V). To further reduce the
supply noise the charge-pumps are biased off of the same
high PSRR regulator used to separate the oscillator from
the noisy global supply. A high time constant RC filter is
used to minimize the charge-pump and oscillator noise
coupling. Replica switches (M13-M18) are introduced in
the master side of the current mirrors to balance the VDS
voltages and minimize the current mismatches.
Additional filtering MOS capacitors (M19, M20) are
connected to the gates of the NMOS and PMOS current
mirrors to reduce the charge coupling to the gate and
speed-up the switching process. Timing mismatch
between pump-up and pump-down is minimized by using
dummy charge-pump branches (M21-M26 and M27-
M32), that balance the number of NMOS and PMOS
gates seen by each PFD output.
3. Loop-filter architectures
Active loop-filters [3, 4] are preferred to the passive
ones [2] due to their lower required charge-pump current
(faster operation) and higher flexibility of loop filter time
constant setting. Current-mode loop filters [6] show a
better noise immunity than the voltage-mode ones
[2, 5], being advantageous in large mixed ICs. Most of
the existing loop filters generate a proportional current
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Fig.2 Differential sample-reset loop filter
based on the instantaneous phase difference between the
reference and feedback clocks. Therefore the total
oscillator control signal presents a significant amount of
ripple at the update frequency that degrades the jitter
performance and increases the reference spur. A ripple
pole is usually introduced in the loop to filter the
oscillator control signal. Unfortunately it decreases the
phase margin and leads to locking overshoot and jitter
peaking. Recently the author has proposed a single ended
sample-reset loop filter architecture [6] that averages the
proportional current over the entire update period and
leads to a ripple-free staircase shaped oscillator control
signal. The loop does not need any more a ripple filtering
pole, leading to a nearly 90° phase margin and therefore
negligible jitter peaking and locking overshoot is
achieved. The phase difference is stored on a sampling
capacitance (Cprop) and then hold for the rest of the
update period while generating a constant proportional
current. After each update period a reset must be
performed to eliminate the memory of the proportional
path that would otherwise lead to an additional pole at
the origin, making the loop unstable. To minimize the
ripple due to the sampling process and relax the
constraints on the reset speed, the reset and sampling
phases are separated from the holding phase by using a
double differential capacitance architecture in which
each sampling capacitor is split in even and odd
components (Cprop1e/Cprop1o and Cprop2e/Cprop2o). During the
even update periods the even capacitors are in sample
mode and the odd ones in hold mode, while during the
odd periods a complementary operation is assured.
This paper proposes a fully differential low-voltage
sample-reset loop filter presented in Fig.2. The integral
path uses two charge-pumps (CPint1, CPint2) controlled in
anti-phase and two phase integration capacitors (Cint1,
Cint2) that are charged in opposite directions. The
resulting differential voltage is transformed into a current
with the M1-M2 integral transconductance stage
(gm_int=1/Rint). The proportional path consists of two
charge-pumps controlled in anti-phase (CPprop1, CPprop2),
two phase sampling capacitors (Cprop1, Cprop2), the M3-
M4 proportional transconductance stage (gm_prop), the
switches that connect alternatively the gm_prop stage to the
even and odd phase sampling capacitors, and the
switches that perform the reset (Sreset). The resulting
damping factor is given by:
1 K ico . ⋅ I cp _ i ⋅ Rint ⋅ C int I cp _ p g m _ prop
ξ= ⋅ ⋅ ⋅ (4)
2 4 π ⋅ M ⋅ C prop 2 I cp _ i f update
where Kico is the ICO gain, Cint, Cprop are the phase
integration and sampling capacitances, and Icp_i and Icp_p
are the integral and proportional charge-pump currents.
A virtually process independent damping factor
results if the proportional path transconductance (gm_prop)
is made process independent, while both charge-pump
currents are derived from the bandgap voltage via a V-to-
I convertion that uses a resistor that matches the integral
path degeneration resistance (Rint). Hence Icp_i⋅Rint α
Vbandgap is process independent. The Kico⋅Cint term results
with a low process dependence if Cint is built with MOS
capacitors using the same device type as the ICO delay
cell. Large area Cint and Cprop capacitors make negligible
the KT/C noise, while using NMOS in Nwell MOS
capacitors minimizes the substrate noise injection.
A process independent transconductance (gm_ref) was
achieved using a differential stage (M6-M7) having the
input voltage proportional to the bandgap voltage
(Vbandgap) and the output current given by the bandgap
voltage divided by an external high precision resistance
(Rext). The stage is kept active with a feedback loop (M8-
M9) that regulates the tail current (M10) to provide a
transconductance equal to 1/Rext. A programmable gm_prop
is obtained by summing the currents from several parallel
connected replica stages (M3,M4).Low-VT devices were
used throughout the signal path to minimize the substrate
injected noise and to allow low voltage operation.
The integral and proportional currents provided by the
two differential gm stages are summed at the input of a
self-biased high swing cascoded current mirror (high
PSRR and low voltage operation) that gives the control
currents for the four ring elements of the oscillator.
4. Controlled oscillator architectures
Single ended ring oscillators using current starved or
weighted current adder inverters provide a low intrinsic
phase noise (low device count) and a high signal to noise
ratio due to their rail-to-rail swing. However they are
rarely used in mixed ICs PLL due to their poor PSRR
characteristics. Most of the actual designs are using
differential ring oscillators. The diode clamped
differential delay cell [2] provide a lower oscillation
amplitude allowing a higher operating frequency, but
with a lower signal to noise ratio. Another widely used
differential delay cell is the symmetric PMOS load,
operated either in triode [1] or saturation regime [3]. In
the triode PMOS load the low swing, leads again to a
higher operating frequency, but with a lower signal to
noise ratio. In contrast the saturated PMOS load provides
a higher swing with better jitter performance, but at a
lower maximum operating frequency. Present design uses
an improved saturated PMOS load ICO presented in
Fig.3. Differential stages have poor common-mode
rejection when in unbalanced state. Therefore preventing
the voltage from swinging rail-to-rail significantly
improves oscillator’s jitter performance. This was
achieved by clamping the amplitude of oscillation (M5-
M8) to two well filtered voltage levels (Vlimit+,Vlimit-).
The process variation of ICO’s gain is reduced by using
two bandgap referenced clamping levels generated with
Ibg+,Rbg+ and Ibg-,Rbg-. A high PSRR regulator is used
to isolate the ICO from the noisy global supply. A further
improvement of the PSRR results by filtering the drain of
the serial transistor (M16) with the M17 source follower.
Another major source of phase noise degradation in
ring oscillators is the voltage dependence of the drain
diffusion capacitance that can be modulated by either the
supply or substrate noise. The oscillation frequency is
determined by the total output capacitance of the delay
cell (Ctotal), composed of the gate capacitance of the next
stage, the drain diffusion capacitances of the output
NMOS and PMOS devices and the parasitic capacitances
of the metal traces. Making the gate capacitance to
dominate depresses the substrate noise injection.
The cycle-to-cycle jitter (∆τ) of a ring oscillator due
to its intrinsic device noise, normalized to the oscillation
period (Tosc) is inverse proportional to the on-voltage of
the differential pair transistors, and the tail current, and
direct proportional to the oscillation frequency (fosc):
∆τ 2 KT a v ⋅ χ 2
= f osc ⋅ ⋅ (5)
Tosc 2 I tail Von
where χ is the delay cell noise contribution factor,
dependent on its gain (av) [7]. Better phase noise
performance is obtained by using long narrow low-VT
devices in the differential pair that makes the gate
component to dominate the total capacitance and
maximizes the on-voltage and minimizes the gain. A
higher total capacitance requires a higher tail current for
the same oscillation frequency. A trade-off between
power dissipation and jitter performance was done. The
parasitic capacitance at the common source point of the
differential pair must be minimized as it can seriously
degrade the jitter performance through charge injection
from ground supply and substrate.
Fig.3 Clamped amplitude differential ring oscillator
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 5. Experimental measurements
Two PLL prototypes were built in a 0.15µm CMOS
process: a reference one (type A) using a single ended
drain-switch CP, a single ended current-mode LF and an
unclamped saturated PMOS load ICO, and a low jitter
one (type B) that uses a double balanced source-switch
CP (Fig.1), a fully differential sample-reset LF (Fig.2),
and a clamped saturated PMOS load ICO (Fig.3). In
order to distinguish between the different contributions
to the overall PLL jitter performance several
measurements were performed with a quiet and noisy
supply and substrate, and for low and respectively high
bandwidth settings. The RMS jitter measurements for the
Fig.4 Standard and sample-reset PLL LF currents
two PLLs operating at 1GHz are summarized in Table I:

Table.I.Measured RMS output jitter at fout=1GHz

Measurement conditions \ PLL type Type A Type B
Low BW, quiet supply & substrate
Low BW, noisy supply & substrate
13.2p
21.0p
7.6p
12.1p
Low BW, noisy supply with ICO clamp
High BW, quiet supply and substrate
-
11.3p
9.4p
6.2p
High BW, noisy supply, noisy substrate 18.7p 8.9p
The measurements at low bandwidth with quiet supply
and substrate give the contribution of the oscillator
intrinsic phase-noise to the output jitter. Switching to a
noisy supply and substrate dramatically increases the
jitter proving that the supply injected noise dominates the
oscillator contributed jitter. Enabling the oscillator
amplitude clamp reduces with several picoseconds the
output jitter. Going to high bandwidth settings reduces
the contribution of the oscillator noise and enhances the
noise coming from the PLL input (PFD, CP and LF).
Fig.4 shows the LF currents for standard and low jitter
PLLs. The staircase current provided by the sample-reset
LF significantly reduces the ICO control current ripple
and overshoot. Fig.5 presents the die photo of a hard
drive controller IC that uses the sample-reset PLL.
6. Conclusions
A differential sample-reset PLL was build in a
0.15µm CMOS process, having a 125MHz-1.25GHz
frequency range and providing a sub 1%⋅Tosc jitter, while
taking 75mW from a 1.5V supply. Using the sample-
reset architecture has minimized the oscillator control
current ripple, reducing both the jitter and reference spur.
The absence of a ripple-pole leads to a 90° phase margin
eliminating the locking overshoot and jitter peaking.
Differential wide-swing cascoded source switch
charge-pumps are used to provide both high speed and
low voltage operation. Accumulation mode capacitors
and low-VT devices were used throughout the signal
path to minimize the substrate injected noise. A high
PSRR regulator isolates the oscillator and charge-pump
from the noisy global supply, while amplitude clamping
improves the oscillator PSRR. A process independent
damping factor allows to maximize the PLL’s bandwidth,
PLL Type B
Dividers LF
PFD CP ICO Regulator
Fig.5 HDD read channel IC die photo
improving both jitter performance and settling time.
Combining these low noise circuit techniques with the
sample-reset architecture has lead to a reduction of the
output jitter to less than half the value given by a
standard feed-forward charge-pump PLL.
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