Multiple-Input Modified Inverse Watkins-Johnson

Converter without Coupled Inductors

Seung H. Choung Alexis Kwasinski
Student Member Member

The University of Texas at Austin

1 University station, C0803
Austin, TX, 78712, USA
shc@mail.utexas.edu , akwasins@mail.utexs.edu

Abstract -- A new multiple-input dc-dc converter realized
from a modified inverse Watkins-Johnson topology is presented
and analyzed. Fundamental electrical characteristics are
presented and power budget equations are derived. Small signal
analysis model of the propose converter is presented and studied.
Two possible operation methods to achieve output voltage
regulation are presented here. The analysis is verified with
simulations and experiments on a prototype circuit.
Index Terms— Alternative energy source interface,
distributed generation, Inverse Watkins-Johnson converter,
micro-grid, multiple-input dc-dc converter.
I. INTRODUCTION
Multiple-input (MI) dc-dc converters have been recently
studied and developed to interface diverse distributed power
sources and energy storage devices with a load [1-20]. In
order to provide adequate operational flexibility, it is
desirable that the MI dc-dc converter is able to both step-up
and step-down the input source voltage [1]. Furthermore,
since nowadays there is an increased need to use photovoltaic
(PV) cells and ultracapacitors which yield relatively low
voltage, high step-up voltage conversion ratio is a practical
requirement in order not to compromise source reliability by
connecting many cells in series. From this perspective, the
inverse Watkins-Johnson Converter (IWJC) dc voltage
transfer ratio is attractive for MI converter applications not
topology in [1]. It includes all the aforementioned advantages
without the need of complicated coupled magnetic
components design. Fundamental power stage equations
which needed to understand circuit operation and small signal
analysis are also summarized. The analysis is verified with
simulation and experimental results.
II. MULTIPLE-INPUT INVERSE WATKINS-JOHNS CONVERTER
CHARACTERISTICS
A. Power-Stage Analysis
Figure 2 shows the proposed MIMIWJC circuit diagram.
Each input leg switch can be realized using forward
conducting bi-directional blocking (FCBB) switches [11]. For
the sake of analytical and operational convenience, it is
assumed that all duty cycles are realized from the same
carrier signal so that the leading edges of all switching signals
occur simultaneously, as shown in Fig. 3. Because of the
choice for FCBB switches, current cannot flow
simultaneously on both inputs, creating an effective duty ratio,
5
4.5
4
3.5
Conversion ratio

3
only because the output voltage can be both higher and lower
2.5
than input voltage but also because higher conversion ratio
2
can be achieved with respect to other boosting converters, as
1.5
shown in Fig. 1 [21]. However, conventional IWJC requires a 1
relatively complex magnetic design that may affect MI 0.5
converters modularity and scalability. One possible 0
alternative is the modified IWJC derived from configuration
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
G1(1) in Table II in [19]. The main advantage of this
Duty ratio
topology is that it can achieve same input-to-output
relationship than the conventional IWJC without a coupled Boost IWJC Buck Boost
inductor or a transformer winding. This paper studies a MI Fig. 1 Normalized conversion ratio comparison in Buck, Boost, Buck-
converter based on this modified IWJC (MIMIWJC) Boost and IWJC (polarity inversion is not shown)

978-1-4244-5287-3/10/$26.00 ©2010 IEEE 3253

 With the assumption of V1 > V2 > … > VN and CCM
operation, the double-input MIMIWJC (Fig. 2) state-space
switched dynamic equations including parasitic resistances of
each passive component and with a resistive load, R, are
summarized in (3).
⎧ L1x1 = q1V1 + q2eff V2 − (1 − q2 ) VDON
⎪
⎪ ⎛ RrC 2 ⎞ ⎛ R ⎞
⎪ − x1 ⎜ rL1 + q2 rC1 + (1 − q2 ) ⎟ − q2 x3 + (1 − q2 ) x4 ⎜ ⎟
⎝ R + rC2 ⎠ ⎝ R + rC 2 ⎠
⎪
⎪ L2 x2 = q1V1 + q2eff V2 + (1 − q2 ) VD
⎪⎪ ON

⎨ ⎛ RrC 2 ⎞ ⎛ R ⎞
⎪ − x2 ⎜ rL 2 + q2 + (1 − q2 ) rC1 ⎟ + (1 − q2 ) x3 − q2 ⎜ ⎟ x4
⎪ ⎝ R + rC2 2 ⎠ ⎝ R + rC 2 ⎠
⎪ C x = q x − (1 − q ) x (3)
⎪ 1 3 2 1 2 2

⎪ ⎛ R ⎞ ⎛ R ⎞ 1
Fig. 2 Proposed MIMIWJC circuit diagram ⎪C2 x4 = − (1 − q2 ) ⎜ ⎟ x1 + q2 ⎜ ⎟ x2 − q2 x4
⎪⎩ ⎝ R + rC 2 ⎠ ⎝ R + rC 2 ⎠ R + rC 2
where, (x1, x2, x3, x4) = (iL1, iL2, vC1, vC2)
Although (3) is for two input MIMIWJC, it can be easily
extended for the case with N input sources. In such case, the
average input-to-output voltage relationship can be found to
be
N Deff ( k )
VOUT = −∑ V( k ) × DF
k =1 1- 2 DN
1
DF = 2 2 2
r1 ⎛ 1 − DN ⎞ r2 ⎛ DN ⎞ r3 ⎛ (1 − DN ) DN ⎞
1+ ⎜ ⎟ + ⎜ ⎟ + ⎜ ⎟
R ⎝ 1 − 2 DN ⎠ R ⎝ 1 − 2 DN ⎠ R ⎝ 1 − 2 DN ⎠
r (4)
where r1 = rL1 + rL1rC 2 + C 2 ,
1 − DN
Fig. 3 MIMIWJC Switching strategy r2 = rL 2 + rL 2 rC 2 + rC 2 ,

Deff. This effective duty cycle Deff is the portion of the and r3 = rC1 + rC1rC 2 − 2rC 2
switching period when the switch conducts current [11], The factor DF represents the parasitic components loss found
which does not necessarily coincides with the portion of the in the circuit, Thus, in ideal circuits it equals 1. Also, the
switching period when the switching signal is commanding average output load current is related to each input source
the corresponding switch to be on. current by
From basic circuit analysis, it can be found that the diode’s
current at the end of its conduction time, i.e., just before the 1 − 2 DN (5)
I OUT = Ik k = 1, 2,3,....N
switch begins to conduct, is. Deff ( k )
⎛ 1 V ⎞ In (5), Ik represents the average input currents of the
iQd =⎜ I + OUT Δtoff ⎟⎟
⎜ 2 DN − 1 OUT Leq
@ t →nTs (1) respective sources. If the load resistance R is big enough to
⎝ ⎠
LL ignore all other parasitic resistances, i.e., R rL1, rL2, rC1 and
where, Leq = 1 2 rC2, then the following important relationships can be
L1 + L2
obtained from (3).
To operate in continuous conduction mode (CCM), the diode
current should not fall below zero when all switches are off. I L1 1- DN
= (6)
Let’s consider the critical inductance, Leqcrit, the one that I L2 DN
makes (1) equal to zero exactly at the instant when the diode
conducting period ends. If this condition is related with the
I L 2 − I L1 = I OUT (7)
fact that Δtoff=(1-DN)Ts then the minimum parallel inductance
VC1 = VOUT − 2 (1 − DN )VD ON (8)
from L1 and L2, Leqcrit, for CCM operation is given by
R(1 − 2 DN )(1 − DN ) (2) It is notable that in (6), the biggest duty ratio, DN, can
Leqcrit = Ts
4 determine the relationship between two inductor average

3254
currents. Moreover, it is observed that difference between the
two inductor average currents is the output load current.
Assuming a perfect lossless conversion process, the input-
to-output power balance serves to obtain the power at each
input leg, which are given by
VOUT Deff , k (9)
Pin , k = − Vin , k k = 1, 2,3.......N
R 1 − 2 DN
From Eq. (9), if the output voltage is fixed, then the power (a) Mode 1
drained form each source is not fully independent of each
other. For the two input source case, the power relationship
between P1 and P2 is expressed by
D2e (1 − D1 ) (10)
P2 = P1
D1 (1 − D2e )
The dependence of P2 on P1 may originate some issues when
using PV modules as input sources if the FCBB switches are
controlled to simultaneously achieve the PV of each
respective panel maximum power point [20]. However, the
high conversion ratio of the MIMIWJC provides enough (b) Mode 2
Fig. 4. Feedback loop diagrams (a) Mode 1 (b) Mode 2
control flexibility to overcome this drawback.
B. Operational Strategy and Small signal analysis
perspective and treated them as one equivalent input source,
Even though a multiple-input converter (MIC) is a Veq as
multiple-input single-output system, for a small signal D V + D2 eV2
analysis it can be seen as a single-input single-output (SISO) Veq = 1 1 (17)
system if operation is performed within the proposed schemes. D2
In here, two possible operation schemes, Mode 1 and Mode 2, Thus, in small-signal analysis Mode 1 operation can be
are demonstrated. Figure 4 shows the scheme for each of treated as a single-loop system. That is, d2(t) determines the
these two approaches. The control-to-output voltage function, overall small signal characteristics.
Gvd, can be obtained both mode 1 and mode 2 by examining a It is also possible that if one of the input legs requires
single voltage loop the Gvd. power regulation, then the regulation scheme can be modified
In Mode 1, in Fig. 4 (a), both duty ratios d1 and d2 into Mode 2 as shown in Fig. 4. (b) with input leg #1 as an
contribute to regulate output voltage. This control approach example of the leg regulating its input current. In other words,
can be used when none of the two input sources require in this case, the duty ratio D1 does not contribute to regulate
power or current regulation. If small displacements d̂1 and the output voltage. In this case, d1 and d2e and d2 can be
expressed as
dˆ are considered from the equilibrium duty cycles D1 and
2e d1 ( t ) = H 2 I1 (18)
D2e, respectively, then each duty cycle becomes
d 2 e ( t ) = D2 e + dˆ2 (19)
d1 ( t ) = D1 + dˆ1 (11)
d 2 ( t ) = D1 + D2 e + dˆ2 = D2 + dˆ2 (20)
d 2 e ( t ) = D2 e + dˆ2 e (12)
Thus, from Fig. 4 (a) In (18), H2 can be set to a certain current reference only to
regulate input current and/or input power. If the study is
d 2 ( t ) = D1 + D2e + dˆ1 + dˆ2e = D2 + dˆ2 (13) limited to small signal analysis then the two loops are
independent of each other and separate analysis for each loop
d 2′ = 1 − d 2 ( t ) (14)
is justified.
V2 An averaged circuit model [22] is adopted to make a small
d1 ( t ) = H 2 d 2 ( t ) = d2 ( t ) (15)
V1 + V2 signal model of the proposed converter. To make an averaged
circuit model, first, the switch network is averaged and
V1
d 2e ( t ) = H 3 d 2 ( t ) =
d2 (t ) (16) expressed as shown in Fig. 5 [23]. The averaged circuit
V1 + V2 model of MIMIWJC which contains the averaged switch
If the duty ratios can be determined by (15) and (16), then network and equivalent input source is shown in Fig. 6.
the input voltage sources can be combined from an analytical

3255
 Middlebrook’s extra element theorem (EET) is adopted in V1 ˆ
d2 (t )
order to find a transfer function [22],[23]. When C1 is taken D2 D′2
as the extra element, (21) shows a typical EET form of an
open-loop control to output function, Gvd.
ZN (s)
1+
vˆ ( s ) Z (s)
Gvd ( s ) = out = Gvd 0 ( s )
ˆ
d2 ( s ) Z
1+ D
(s) I2 ˆ
(21) d2 ( t )
Z (s) D2 D′2

1
where, Z ( s ) =
sC1
In (21), Z(s) is the impedance of C1, ZD(s) is the driving point
Fig. 6 A DC and small signal circuit model of the MIIWJC.
impedance seen by C1 and ZN(s) is the driving point N1:N2=D2:1-D2

i1 ( t ) i2 ( t ) V1 ˆ
d2 ( s )
D2 D′2

v1 ( t ) v2 ( t )

V1 ˆ
d2 I2 ˆ
vˆout ( s )
I1 + iˆ1 D2 D′2 1 − D2 : D2 I 2 + iˆ2 d2 ( s )
D2 D′2

I2 ˆ
V1 + vˆ1 d2 V2 + vˆ2
D2 D′2
Fig. 7. Circuit diagram for a transfer function Gvd0(s)
Fig. 5. Switch modeling for averaged circuit. (a)Top: Switch network. (b) N1:N2=D2:1-D2
Bottom: Averaged switch network of an Inverse Watkins-Johnson converter

D2
impedance also seen by C1 which determines the null M =− (23)
1 − 2 D2
condition for vout(s). The left hand side term in (21), Gvd0(s),
is the control-to-output voltage transfer function when C1 is Leq1 = D2′ L1 + D2 L2 (24)
removed from the original circuit and the right hand side term
involving Z(s) is the so called correction factor (CF). Figure 7 (1 − 2 D2 ) R 1 − 2 D2
is the small signal equivalent circuit diagram used to find a ωZ 1 = − , ω1 = (25)
M ⋅ Leq1 Leq1C2
Gvd0(s) in (21). As it can be noticed from Fig. 7, in (22),
Gvd0(s), is same as Gvd that can be found in a conventional
IWJC, because the circuit diagram is the same as in the C2
Q1 = (1 − 2 D2 ) R (26)
conventional IWJC small signal diagram except that there is Leq1
no magnetic coupling between L1 and L2 in Fig. 7. The
overall control-to-output characteristics are determined by In order to find ZN(s) in (21) the circuit in Fig. 8 can be used
Gvd0(s). Equation (23) yields the DC gain and (24) represents in combination with the use of Middlebrook’s EET. ZN(s)
equivalent inductance, Leq1, which influences the angular can be found by adding a test signal i(s) in place of C1 and
corner given in (25) and modified quality factor in (26), i.e., measuring v(s). Thus,
the system characteristics for the first and second order s
network system. 1−
sLeq 2 ωZ 2
s ZN ( s) = (27)
1− VO 1 − 2 D2 1 − s
ωZ 1 ω2
Gvd 0 ( s ) = MVO 2
(22)
s ⎛ s ⎞
1+ +⎜ ⎟ where
Q1ω1 ⎝ ω1 ⎠
Leq 2 = D2′ L2 + D2 L1 (28)

3256
and
V1 ˆ TR
d2 ( s )
1 Leq 2 R (1 − 2 D2 ) R D2 D′2
ωZ 2 =− , ω2 = (29) N1
M L1 L2 M Leq1 L2
TR
v(s) i (s)
Likewise for ZN(s), Fig. 9 is now used to find for ZD(s) in
N2
(21). The circuit is almost same than that in Fig. 8 except for
the output voltage condition. Note that in Fig. 9, the null I2 ˆ
vˆout ( s )
L1 d2 ( s ) c2
condition is made by assuming zero current passing through D2 D′2
the load resistor.
2
s ⎛ s ⎞
1+ +⎜ ⎟
D22 L1 + D ′22L2 Q2ωZ 3 ⎝ ωZ 3 ⎠ Fig. 8. Circuit diagram to determine impedance ZN(s) for EET
ZD ( s ) = s 2
(30)
1 − 2D s⎛ s ⎞ V1 ˆ
d2 ( s )
1+ +⎜ ⎟ D2 D′2
Q3ω3 ⎝ ω3 ⎠

where v (s) i (s)

Leq 3 = D22 L1 D2′2 L 2 , Leq 4 = D2 D2′ L1 + D22 L2 , (31) vˆout ( s ) → 0

I2 ˆ null
d2 ( s )
D2 D′2
D2 D2′ 1 − 2D
ωZ 3 = , ω3 = (32)
Leq 3C2 Leq 4 C2

and Fig. 9. Circuit diagram to determine impedance ZD(s) for EET

C2 C2 under CCM condition.

Q2 = D2 D ′ , Q3 = (1 − 2 D2 ) R
Leq 3 Leq 4
Equation (30) shows the normalized form of ZD(s) in (21).
Further, more detailed analysis of CF in (21) is omitted here,
because it is out of scope this paper. For the interested reader,
more information about Middlebrook’s EET analysis can be
found in [22]-[25]. However, by inspection of (21) one can
notice that at low frequency range—usually an interesting
frequency range—the magnitude of CF in (21) is close to 1
since ||Z(s)||>>||ZD(s)|| and ||Z(s)||>>||ZN(s)||. Also, it can be
easily observed that in high frequency range the magnitude of
CF in (21) approximates ||ZN(s)||/||ZD(s)||. Hence, for high
frequency the effects of poles and zeroes are canceled out and
the magnitude of CF becomes flat.
III. SIMULATED AND EXPERIMENTAL RESULTS
The analysis of the proposed circuit was verified in this
section by means of simulations and experiments in both
open-loop and closed-loop. For the simulation,
MATLAB/SIMULINK and Psim are used to verify the
operational equations and small signal analysis. An
(33)
Figure 10 shows the calculated and measured open-loop
output voltage with a fixed duty ratio D2 at 0.35 and varying
D1. The difference between calculated value and measured
value were most likely caused by semiconductor switch
losses which were (4) used to calculate the theoretical trace of
Vout in Fig. 10.
Figure 11 shows the simulated inductors and output
currents, iL1, iL2 and iout with D1=0.1 and D2=0.35. As shown
in Fig. 11, the difference between two inductor currents are
equal to output current as indicated in (7). The simulated
voltage waveforms for capacitors, vC1 and vC2, are plotted in
Fig. 12 under the same duty ratio condition than in Fig.11. In
Measured Vout Calculated Vout
18
16
[V]

14
experimental prototype was also constructed to verify the
analysis. The system parameters and component values which
are used for both simulation and experiments are 12
L1=L2=300 μH, C1=100 μF, C2=1500 μF, Vin1=15 V, Vin2=8 V
and fS=30 kHz. The FCBB switches used in experiments are
realized by the series combination of IRFP140A MOSFET 0.1 0.15 0.2 0.25 0.3 0.35
and S60SC6M diode. The same S60SC6M is used for the D1
diode Qd. All the simulations and experiments are carried out Fig. 10 Output voltage with the D1 varies at D2=0.35

3257
 iL iL iout
1 2
iL2
4

3 - iout
2

1 - (iL2 - iL1)
[A]

0 iL1
-1

-2 Fig.13Experimentally obtained Inductor current

99.90 99.92 99.94 99.96 99.98 100
[ms] Fig.14 Control to output voltage transfer function, Gvd,function
bode diagram
Open Loop Control to Output transfer G vd
Fig.11 Simulated inductors and output load current waveforms Bode Diagram
50

Magnitude (dB)
30

vC vC 10
1 2
-10
-11.5
-30
-11.55
180
Phase (deg)

-11.6 90

0
[V]

-11.65
-90
-11.7 -180 1 2 3 4 5 6
10 10 10 10 10 10
-11.75 Frequency (Hz)
Fig.14 Control to output voltage transfer function, Gvd, bode diagram

99.90 99.92 99.94 99.96 99.98 100

When the PI controller and loop is added, the new Bode plot
[ms] is shown in Fig. 15. As this figure implies, the PI controller
Fig.12 Simulated capacitors voltage improves stability characteristics by increasing the phase
margin up to 100deg.
Fig 12, it can be observed that the two averaged capacitor Figures 16 and 17 show the simulated time domain output
voltages are same as expected in (8). voltage regulation characteristics when Mode 2 approach is
Figure 13 shows the experimentally obtained inductor and considered. The simulated waveforms verify that the
output current waveforms. Since L1 and L2 are same and the suggested control method can effectively regulate the output
output capacitor is larger enough to ignore the output current voltage when both the load and an input voltage changes as
ripple, the instantaneous output current iout equals the exemplified when the load current varies from 2 to 4A and
difference between two inductor current iL2 and iL1. As
expected, the waveforms are similar to those observed in Fig.
11.
For the close-loop simulation and experiment, Vout is set to
be -5V. A proportional-integral (PI) controller with gains
kp=0.08 and ki=0.008 is used to regulate the output voltage.
Sensing gain H=-0.33, and PWM gain of 0.33 is added to the
closed-loop. Figure 14 shows the bode plot for the control-to-
output voltage transfer function obtained from the open loop
small signal model without considering the PI control. This
obtained transfer function, Gvd is expressed as

3.86⋅10−3 s4 + 216.9s3 −3.97⋅107 s2 + 2.73⋅109 s −1.33⋅1015

Gvd = (34)
s4 +314.8s3 + 2.52⋅107 s2 + 4.84⋅109 s +3.08⋅1013 Fig. 15 Bode diagram of closed-loop of MIMIWJC
(phase margin=100ο , gain margin= 24dB )

3258
 V2

V1

Vout

Fig. 18 MOD 2 voltage regulation when input source voltage V1 changes

from 18 to 12 V while V2 stays at 12 V.
Fig. 16 Voltage regulation in Mode 2 when load current varies from 2 to
4 A.

V2

V1

Vout

Fig. 19 MOD 2 voltage regulation when input source voltage V2 changes

from 15 to 10 V while V1 stays at 18 V.

Iout
Fig. 17 Voltage regulation n Mode 2 when input source V1 varies from
15 to 10 V while V2 stays at 12 V.

the input source V1 voltage changes from 15 to 10V while V2

is kept at 12V. These control characteristics are also
confirmed from experimental results as shown in Figs. 18 to
20. Figures 18 and 19 show output voltage regulation, first
when V1 varies from 18 to 12 V and then when V2 varies from
15 to 10 V. Finally, Fig. 20 confirms the simulated result in
Fig. 16; i.e., successful output voltage regulation when the
load current varies from 2 to 4 A.
IV. CONCLUSION
A new MI MIWJC derived from the topology G1(1) in
[19] has been analyzed. This proposed topology allows
integrating different dc energy sources with a relatively high
flexibility so it may enable the use of renewable and
alternative energy sources in a simpler way. In this paper, its
fundamental operational equations including input power
budget relationships and steady state dynamic equations are
derived. The small signal analysis model has been developed
by circuit averaging and Middlebrook’s EET, proving its
usefulness for stability analysis or filter design. Two possible
operation methods have been introduced in order to achieve
Vout
Fig. 20 MOD 2 voltage regulation when load current varies from 2 to 4
A.
output voltage regulation with a simple PI controller while at
the same time it still allows to analyze the MI MIWJC as a
SISO system.
Future work on MI MIWJC will consider input power
regulation methods such as maximum power point tracking
(MPPT). In order to achieve this goal, the frequency domain
analysis included in this paper will be expanded.
REFERENCES
[1] S. H. Choung and A. Kwasinski, “Multiple-input DC-DC
converter topologies comparison,” in Proc. Ind. Electron. Soc.
Conf., 2008, pp. 2359-2364.
[2] Z. Ruichen and A. Kwasinski, “Multiple-input single ended

3259
 primary inductor converter (SEPIC) converter for distributed Aug. 1989.
generation applications,” in Proc. Rec. ECCE, 2009, pp. 1847- [25] R. W. Erickson and D. Maksimovic, Fundamentals of Power
1854. Electronics, Norwell, MA: Kluwer, 2001.
[3] A. Kwasinski, “Identification of Feasible Topologies for
Multiple-Input DC-DC Converters,” IEEE Trans. Power
Electron., vol. 24, no. 3, pp. 856-861, Mar. 2009.
[4] L. Yuan-Chuan and C. Yaow-Ming, “A Systematic Approach to
Synthesizing Multi-Input DC/DC Converters,” in Proc. Rec.
PESC, 2007, pp. 2626-2632.
[5] A. Kwasinski and P. T. Krein, “Multiple-input dc-dc converters to
enhance local availability in grids using distributed generation
resources,” in Proc. APEC, 2007, pp. 1657-1663.
[6] H. Tao, A. Kotsopoulos, J. L. Duarte, and M. A. M. Hendrix,
‘‘Family of multiport bidirectional dc---dc converters,’’ in Proc.
Electr. Power Appl., vol. 153, no. 3, pp. 451---458, May 2006.
[7] H. Keiichi, K. Hirose, T. Takeda, and S. Muroyama, “Study on
Field Demonstration of Multiple Power Quality Levels System in
Sendai,” in Proc. INTELEC, 2006, pp. 1-6.
[8] K. P. Yalamanchili and M. Ferdowsi, “Review of multiple input
DC-DC converters for electric and hybrid vehicles,” in Proc.
Vehicle Power and Propul., 2005, pp. 160-163.
[9] H. Tao, A. Kotsopoulos, J. L. Duarte, and M. A. M. Hendrix,
“Multi-input bidirectional DC-DC converter combining DC-link
and magnetic-coupling for fuel cell systems,” in Proc. Rec. Ind.
Appli. Conf., 2005, pp. 2021-2028
[10] A. Kwasinski and P. T. Krein, “A Microgrid-based Telecom
Power System using Modular Multiple-Input DC-DC
Converters,” in Proc. INTELEC, 2005, pp. 515-520.
[11] N. D. Benavides and P. L. Chapman, “Power budgeting of a
multiple-input buck-boost converter,” IEEE Trans. Power
Electron., vol. 20, no. 6, pp. 1303-1309, Nov. 2005.
[12] M. Michon, J. Duarte, M. Hendrix, and M. Simoes, “A three-port
bi-directional converter for hybrid fuel cell systems,” in Proc.
Rec. PESC, 2004, pp. 4736-4742.
[13] H. Matsuo,W. Lin, F. Kurokawa, T. Shigemizu, and N.
Watanabe, “Characteristics of the multiple-input DC-DC
converter,” IEEE Trans. Ind. Electron., vol. 51, no. 3, pp. 625-
631, Jun. 2004.
[14] B. Dobbs and P. Chapman, “A multiple-input dc–dc converter
topology,” IEEE Power Electron Lett., vol. 1, no. 1, pp. 6–9, Mar.
2003.
[15] A. Di Napoli, F. Crescimbini, L. Solero, F. Caricchi, and F. G.
Capponi, “Multiple-input DC-DC power converter for power-
flow management in hybrid vehicles,” in Proc. Rec. Ind. Appli.
Conf., 2002, pp. 1578-1585.
[16] J. Sebastian, P. J. Villegas, F. Nuno, and M. M. Hernando, “High-
efficiency and wide-bandwidth performance obtainable from a
two-input buck converter,” IEEE Trans. Power Electron., vol. 13,
no. 4, pp. 706-717, Jul. 1998.
[17] F. D. Rodriguez and W. G. Imes, “Analysis and modeling of a
two-input DC/DC converter with two controlled variables and
four switched networks,” in Proc. Rec. IECEC, 1996, pp. 322-
327.
[18] F. Caricchi, F. Crescimbini, A. D. Napoli, O. Honorati, and E.
Santini, “Testing of a new DC/DC converter topology for
integrated wind-photovoltaic generating systems,” in Proc. Rec.
EUROCON, 1993, vol.8, pp. 83-88.
[19] R. Tymerski and V. Vorperian, “Generation and classification of
PWM dc-to-dc converters,” IEEE Trans. Aerosp. Electron. Syst.,
vol. AES-24, no. 6, pp. 743–754, Nov. 1988.
[20] S. Junseok and A. Kwasinski, “Analysis of the effects of duty
cycle constraints in multiple-input converters for photovoltaic
applications,” in Proc. INTELEC, 2009, pp. 1-5.
[21] D. A. Grant and Y. Darroman, “Inverse Watkins-Johnson
converter - analysis reveals its merits,” Electron. Lett. vol. 39, no.
18, pp. 1342-1343, Oct. 2003.
[22] R. D. Middlebrook, V. Vorperian, and J. Lindal, “The N extra
element theorem,” IEEE Trans. Circuits Syst. I, vol. 45, no. 9, pp.
919–935, Sep. 1998.
[23] R. D. Middlebrook, “The two extra element theorem,” in Proc.
Rec. Frontiers in Edu. Conf., 1991, pp. 702-708.
[24] R. D. Middlebrook, ‘‘Null double injection and the extra element
theorem,’’ IEEE Trans. Education, vol. 32, no. 3, pp. 167---180,

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