Choosing The Right Processor

Choosing the
Right Processor
for your
y
Application
www pantechsolutions net

www.pantechsolutions.net
A
Agenda
d
 Choosing
Ch i the th right
i ht processor ffor your application
li ti
 Hardware design flow
 Software design flow
 Various design phases
 Recap of product life cycle
Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt Ltd.
Choosing
g the right
g Processor
Microprocessor Basic
CO
CONTROL
O
ADDRESS
Keyboard
BOOT Screen
CPU ROM Instruction Data
RAM UART
(program) Transducers
Used at ROM Parallel
startup interface
etc
DATA
Microprocessor, by-itself
Microprocessor by-itself, completely useless – must have external peripherals to
Interact with outside world
Micro controller
CPU
Von Neumann VS Harvard
Memory
CPU (Program Memory CPU Memory
&Data) (Data) 8 12 (Program)
14
16
Von Neumann Harvard
Why do we need DSP
Processor?
CPLD Vs FPGA
CPLD Vs FPGA
CPLDs have the advantage of virtually “instant-on” functionality
CPLDs can be lower cost than FPGAs, especially if a configuration source is

required for the FPGA*
CPLDs typically use the same manufacturer tool suite as FPGA components*
CPLDs tend to have simpler architectures / structures and fewer I/O and
registers than FPGAs*
In some applications CPLDs can have superior performance to FPGAs* (ex:
timing and I/O levels)
CPLD Architecture
Logic blocks
 I/O blocks
Clock routingg
Routing matrix
FPGA Architecture
Logic blocks
I/O blocks
Cl k routing
Clock ti
Routing matrix
Memory
Multipliers /DSP blocks
Processor core
FPGA Technologies
Why HDL?
No need for logic optimization using Karnaugh map.
Design is portable from one vendor application to the another.
Technology
gy Independent.
p
Design cycle time reduces dramatically.
Provides concise representation of the design in contrast to logic diagrams
Verilog Vs VHDL
Verilog
C-like
–Middle
Middl class
l structure
t t llevell
Case sensitive
Differs from C primarily in the representation of literals
and ability to deal with time
VHDL
Ada-like
Ada like
–Highly structured
No case sensitivity
Encapsulation
–Architecture
–Entity
DSP Vs FPGA
When to use DSP in FPGA
 Higher Performance
Parallel algorithm implementation
 Customizable Design
Optimize for speed and cost
 System Integration
Less board real estate
Less chips could mean less system cost
Traditional embedded system
y
design using DSP
Power Supply
Ethernet Audio CLK
CLK
MAC Codec
GP I/O Interrupt
Controller
Timer
Address
Decode
Unit
CPU UART
L
(uP / DSP) Co- C
Memoryy Proc. custom
CLK Controller IF-logic
SRAM SRAM SRAM Display

SDRAM SDRAM Controller
C t ll
Next Step...
Power Supply
Ethernet Audio CLK
CLK
MAC FPGA Codec
GP I/O Interrupt
Controller
Timer
Address
Decode
Unit
CPU UART
L
(uP / DSP) Co- C
Memoryy Proc. custom
CLK Controller IF-logic
SRAM SRAM SRAM Display

SDRAM SDRAM Controller
C t ll
Configurable
g system
y on Chip-
p
CSoC
Audio
Codec EPROM
Power Supply
L
C
SRAM SRAM SRAM SDRAM SDRAM
Multicore Processor
2 or More Independent Processors in 1 Package
Symmetric Multiprocessing
 Number of Identical Processors
 Common Shared Memory
 One Operating System
Asymmetric Multiprocessing
 Different Processors, Instruction Sets
 Different Operating Systems
 Possibly Without Shared Memory
SMP BF561
SMP-BF561
•Identical Cores
•Identical access to all System
y Resources
•Memory, Disk, UARTs, Communication Controllers,
•Examples: Analog Devices Blackfin 561
AMP-TI
AMP TI OMAP
Processors Need Not be Identical

Processor Specialization May Increase Performance.
T.I.’s OMAP•General Purpose Processor+Digital Signal Processor(“DSP”)
A
Agenda
d
 Processor
P selection
l ti C Criteria
it i
 Choosing the right processor for your application
 Recap
R off product
d t life
lif cycle
l
Selection of packages
SOLDERING
IRON
DIP QFP SOIC
SOLDERING
STATION
BGA
PLCC
OVEN
Hardware Design Flow
SCHEMATIC DESIGN LAYOUT DESIGN
ASSEMBLY & TESTING

A
Agenda
d
 Choosing
Ch i the th right
li ti
Software Design Flow
Software Design Flow -FPGA
Hardware Software
*.c *.asm
Platform Definition Gen.
(peripherals, configuration, Libs
connectivity, address space) *.h
*.mhs
Generate Compile &

Netlist Link
ISE
XPS
Platform Ext. *.ucf *.bmm

*.elf
Proj.Nav. / VHDL
Generate *.bit Update

Bitstream Bitstream
*.bit
 EDK: Embedded Development Kit
 XPS: Xilinx Platform Studio
 ISE: Integrated Software Environment
 MHS: Microprocessor Hardware Specification
Integrated HW/SW/FPGA Flows
C Code VHDL or Verilog
Standard Embedded Embedded Standard FPGA

SW Development Flow Development Kit HW Development Flow
Code Entry Board Support HDL Entry

System Netlist
Package Instantiate the
Include
C/C++ the
Cross BSP
Compiler Simulation/Synthesis
‘System Netlist’
and Compile
p the
and
d Implement
I l t
Software
LinkerImage Data2MEM Implementation
the FPGA
? 2 Compiled ELF 3 Compiled BIT 1 ?
Download Combined
Load Software Download Bitstream
Image to FPGA
Into FLASH Into FPGA
Debugger Chipscope
Xili Platform
Xilinx Pl tf Studio
St di RTOS B
RTOS, Board
dSSupportt P
Package
k Xilinx Platform
SDK Studio
FPGA Design
g Flow
FPGA Design Flow
Design Compilation Simulation Verification
Graphical Entry
Timing Diagram Program CPLD
Compiler
HDL Entry Timing Analysis Development Board
Unified Design
g Environment
The Ultimate System Integration Design Tools
....
Verilog VHDL C/C++ MATLAB Simulink 3rd
Party
a y
Unified Tool Releases

Releases, All Tools Available for Evaluations
Design Decision in Choosing an FPGA
Programmable
technology Gate count
I/O’S
Number of I/O S
Power Consumption
P C ti
Manufacturer
Speed,voltage
Family Packaging
D i
Device
Processor selection Criteria
 Development tools
 Performance
 Cost
 Operating systems
 Hardware tools
 Peripherals
 Power consumption
 Supplier reputation
Embedded Development
p using
g FPGA
Networking
Protocols Graphics Memory
Java Project
RTOSs Support Leak
Compiler Support & Code Rapid Real-time Post-
Detection
Mgmt. RTOS Prototyping
yp g Data CPU mortem
Simulation Visualization Profiling Debug
SW SELECTION SW DEVELOPMENT
INTEGRATION TESTING & TUNING DEPLOYMENT
HW SELECTION HW DEVELOPMENT
Real-time Execution In-field
Tracing Code
Source- System Debugging
Board Coverage
level Analysis &
Diagnostics & Analysis
Board Debugging Ti
Triggering
i
Bring-Up Manufacturing
Semiconductor Test
Co-funded
Development Hardware
Coverage
© 2008 P
Pantech
t hS Solutions™
l ti ™ | All rights
i ht reserved
d
A
Agenda
d
 Choosing
Ch i the th right
li ti
Simulation Evaluation
Emulation
A
Agenda
d
 Choosing
Ch i the th right
li ti
Recap of Designing an Embedded System
Website and Resources
http://nptel.iitm.ac.in/videocourselist.php
http://youtube com/iit
http://youtube.com/iit
8051
http://www.esacademy.com/ (Philips Flash ISP software)
htt //
http://www.keil.com/demo/
k il /d / E l i version
Evaluation i for
f 8051 and
d ARM
PIC
http://www.microchip.com
FPGA
http://www.xilinx.com/support/download/index.htm
https://www altera com/support/software/download/sof
https://www.altera.com/support/software/download/sof-
download_center.html
DSP
http://www.analog.com/en/embedded-processing-
dsp/content/blackfin bold training/fca.html
dsp/content/blackfin_bold_training/fca.html
www.ti.com/
Questions ?

Choosing The Right Processor

Încărcat de

Informații document

Descriere originală:

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

Choosing The Right Processor

Încărcat de

Drepturi de autor:

Formate disponibile

Choosing the

www pantechsolutions net

Von Neumann Harvard

CPLDs have the advantage of virtually “instant-on” functionality

CPLDs can be lower cost than FPGAs, especially if a configuration source is

No need for logic optimization using Karnaugh map.

Design is portable from one vendor application to the another.

Design cycle time reduces dramatically.

Provides concise representation of the design in contrast to logic diagrams

SRAM SRAM SRAM Display

SRAM SRAM SRAM Display

SRAM SRAM SRAM SDRAM SDRAM

2 or More Independent Processors in 1 Package

Processors Need Not be Identical

DIP QFP SOIC

SCHEMATIC DESIGN LAYOUT DESIGN

ASSEMBLY & TESTING

Generate Compile &

Platform Ext. *.ucf *.bmm

Generate *.bit Update

Standard Embedded Embedded Standard FPGA

Code Entry Board Support HDL Entry

? 2 Compiled ELF 3 Compiled BIT 1 ?

HDL Entry Timing Analysis Development Board

Unified Tool Releases

S-ar putea să vă placă și

Platform Ext. .ucf .bmm