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Data Manual
Contents
1 MAIN FEATURES ................................................................................................................ 5
1.1 TUSB9260 Features ........................................................................................................ 5
1.2 Target Applications ......................................................................................................... 5
2 INTRODUCTION .................................................................................................................. 6
2.1 System Overview ........................................................................................................... 6
2.2 Device Block Diagram ...................................................................................................... 6
3 OPERATION ....................................................................................................................... 8
3.1 General Functionality ....................................................................................................... 8
3.2 Firmware Support ........................................................................................................... 9
3.3 GPIO/PWM LED Designations ............................................................................................ 9
3.4 Power Up and Reset Sequence ......................................................................................... 10
4 SIGNAL DESCRIPTIONS ..................................................................................................... 11
5 CLOCK CONNECTIONS ...................................................................................................... 15
5.1 Clock Source Requirements ............................................................................................. 15
5.2 Clock Source Selection Guide ........................................................................................... 15
5.3 Oscillator .................................................................................................................... 16
5.4 Crystal ....................................................................................................................... 16
6 ELECTRICAL SPECIFICATIONS .......................................................................................... 17
6.1 Absolute Maximum Ratings .............................................................................................. 17
6.2 Recommended Operating Conditions .................................................................................. 17
6.3 DC Electrical Characteristics for 3.3-V Digital I/O ..................................................................... 17
7 POWER CONSUMPTION ..................................................................................................... 18
List of Figures
2-1 Device Block Diagram ............................................................................................................. 7
5-1 Typical Crystal Connections .................................................................................................... 15
List of Tables
3-1 GPIO/PWM LED Designations ................................................................................................... 9
4-1 I/O Definitions ..................................................................................................................... 11
4-2 Clock and Reset Signals ........................................................................................................ 11
4-3 SATA Interface Signals .......................................................................................................... 11
4-4 USB Interface Signals ........................................................................................................... 12
4-5 Serial Peripheral Interface (SPI) Signals ...................................................................................... 12
4-6 JTAG, GPIO, and PWM Signals ............................................................................................... 13
4-7 Power and Ground Signals ..................................................................................................... 14
5-1 Oscillator Specification .......................................................................................................... 16
5-2 Crystal Specification ............................................................................................................. 16
7-1 SuperSpeed USB Power Consumption ....................................................................................... 18
7-2 High Speed USB Power Consumption ........................................................................................ 18
1 MAIN FEATURES
1.1 TUSB9260 Features
• Universal Serial Bus (USB)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TUSB9260
SLLS962D – DECEMBER 2009 – REVISED MAY 2011 www.ti.com
2 INTRODUCTION
USB 3.0
(1)
SuperSpeed
PC
with
USB 3.0 SATA
Gen1/2 HDD
Support
USB 2.0
(1)
High-speed
TUSB9260
(1) USB connection is made at either SuperSpeed or High-Speed depending on the upstream connection support.
ROM GRSTz
ARM Power TCK
Cortex M3 VDD3.3
and TMS
VDD1.8 Reset TDO
RAM JTAG
Distribution TDI
VDD1.1 TRST
Data Path
XI RAM USB 3.0
Clock
XO 80 kB Device
Generation
Controller
SATA
Timer AHCI
Watchdog
Timer
VBUS
USB_R1RTN
PWM[1:0]
GPIO[11:0]
USB_R1
DATA_IN
SATATX+
SATARX+
DP/DM
SCLK
SATATX-
SATARX-
CS[2:0]
UartRX
UarTX
SSRX+
SSTX+
SSRX-
SSTX-
Figure 2-1. Device Block Diagram
3 OPERATION
GPIO0 SW heartbeat
00: U3 state or default
01: U2 state
GPIO1/GPIO5 USB3 power state (U0-U3)
10: U1 state
11: U0 state
GPIO2 HS/FS suspend
GPIO3 Push button input on customer board
GPIO4 Not used
GPIO6 FS/HS connected
GPIO7 SS connected
PWM0 Disk activity
PWM1 U3 or HS/FS suspend state (fades high and low)
GPIO10
Not used
(SPICS1)
GPIO11
Not used
(SPICS2)
The LED’s on the TUSB9260 Product Development Kit (PDK) board are connected as in the table above.
Please see the TUSB9260 PDK Guide (SLLA303) for more information on GPIO LED connection and
usage. This EVM is available for purchase, contact TI for ordering information.
4 SIGNAL DESCRIPTIONS
TERMINAL
PIN I/O DESCRIPTION
NAME
NO.
I Global power reset. This reset brings all of the TUSB9260 internal registers to their default
GRSTz 4
PU states. When GRSTz is asserted, the device is completely nonfunctional.
Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately
XI 52 I be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback resistor
is required between X1 and XO.
Crystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an
XO 54 O external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback
resistor is required between X1 and XO.
Frequency select. These terminals indicate the oscillator input frequency and are used to
configure the correct PLL multiplier. The field encoding is as follows:
FREQSEL[1] FREQSEL[0] INPUT CLOCK FREQUENCY
I 0 0 Reserved
FREQSEL[1:0] 31, 30
PU
0 1 Reserved
1 0 Reserved
1 1 40 MHz
TERMINAL
PIN I/O DESCRIPTION
NAME
NO.
SATA_TXP 57 O Serial ATA transmitter differential pair (positive)
SATA_TXM 56 O Serial ATA transmitter differential pair (negative)
SATA_RXP 60 I Serial ATA receiver differential pair (positive)
SATA_RXM 59 I Serial ATA receiver differential pair (negative)
(1) Note that the default firmware and reference design for the TUSB9260 have the SATA TXP/TXM swapped for ease of routing in the
reference design. If you plan to use the TI default firmware please review the reference design in the TUSB9260 DEMO User’s Guide
(SLLU131) for proper SATA connection.
TERMINAL
PIN I/O DESCRIPTION
NAME
NO.
USB_SSTXP 43 O USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM 42 O USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP 46 I USB SuperSpeed receiver differential pair (positive)
USB_SSRXM 45 I USB SuperSpeed receiver differential pair (negative)
USB_DP 36 I/O USB High-speed differential transceiver (positive)
USB_DM 35 I/O USB High-speed differential transceiver (negative)
USB_VBUS 33 I USB bus power
USB_R1 39 O Precision resistor reference. A 10-kΩ ±1% resistor should be connected between R1 and R1RTN.
USB_R1RTN 40 I Precision resistor reference return
TERMINAL
PIN I/O DESCRIPTION
NAME
NO.
O
SPI_SCLK 17 SPI clock
PU
I
SPI_DATA_IN 18 SPI master data in
PU
O
SPI_DATA_OUT 20 SPI master data out
PU
O
SPI_CS0 21 Primary SPI chip select for Flash RAM
PU
SPI_CS2/ I/O SPCI chip select for additional peripherals. When not used for SPI chip select this pin may be
23
GPIO11 PU used as general purpose I/O.
SPI_CS1/ I/O SPCI chip select for additional peripherals. When not used for SPI chip select this pin may be
22
GPIO10 PU used as general purpose I/O.
TERMINAL
PIN I/O DESCRIPTION
NAME
NO.
I
JTAG_TCK 25 JTAG test clock
PD
I
JTAG_TDI 26 JTAG test data in
PU
O
JTAG_TDO 27 JTAG test data out
PD
I
JTAG_TMS 28 JTAG test mode select
PU
I
JTAG_TRSTz 29 JTAG test reset
PD
I/O GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a
GPIO9/UART_TX 6
PU UART channel. This pin defaults to a general purpose output.
I/O GPIO/UART receiver. This terminal can be configured as a GPIO or as the receiver for a UART
GPIO8/UART_RX 5
PU channel. This pin defaults to a general purpose output.
I/O
GPIO7 16
PD
I/O
GPIO6 15
PD
I/O
GPIO5 14
PD
I/O
GPIO4 13
PD
Configurable as general purpose input/outputs
I/O
GPIO3 11
PD
I/O
GPIO2 10
PD
I/O
GPIO1 9
PD
I/O
GPIO0 8
PD
O
PWM0 2
PD (1)
Pulse Width Modulation (PWM). Can be used to drive status LED's.
O
PWM1 3
PD (1)
(1) PWM pull down resistors are disabled by default. A firmware modification is required to turn them on. All other internal pull up/down
resistors are enabled by default.
TERMINAL
PIN I/O DESCRIPTION
NAME
NO.
VDDR18 48, 62 PWR 1.8-V power rail
VDDA18 37 PWR 1.8-V analog power rail
1, 12,
19, 32,
38, 41,
VDD 44, 47, PWR 1.1-V power rail
49, 55,
58, 61,
63, 64
7, 24,
VDD33 PWR 3.3-V power rail
50, 51
VDDA33 34 PWR 3.3-V analog power rail
Oscillator ground. If using a crystal, this should not be connected to PCB ground plane. If
VSSOSC 53 PWR using an oscillator, this should be connected to PCB ground. See the Clock Source
Requirements section for more details.
VSS 65 PWR Ground - Thermal Pad
5 CLOCK CONNECTIONS
5.3 Oscillator
XI should be tied to the 1.8-V clock source and XO should be left floating.
VSSOSC should be connected to the PCB ground plane.
A 40-MHz clock can be used.
5.4 Crystal
A parallel, 20-pF load capacitor should be used if a crystal source is used.
VSSOSC should not be connected to the PCB ground plane.
A 40-MHz crystal can be used.
6 ELECTRICAL SPECIFICATIONS
7 POWER CONSUMPTION
All transfers are to a SATA Gen II SSD. A SATA Gen I target yields an approximate 10-mA power savings
on the 1.1-V rail.
www.ti.com 7-May-2011
PACKAGING INFORMATION
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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Addendum-Page 1
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