Ch.13 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R.

Kime Page 1/11

Chapter 13 Input-Output and Communication

Outline:
- Computer I/O
- Communication between the CPU and I/O

13-1) Computer I/O

13-2) Sample Peripherals

- Keyboard

Keyboard Scan Matrix

- Hard Disk

Hard Disk Format

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.13 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 2/11

- Graphics Display

CRT Display

- I/O Transfer Rates

13-3) I/O Interfaces

- I/O Bus and Interface Unit

Connection of I/O Devices to CPU

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.13 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 3/11

- Example of I/O Interface

Example of I/O Interface Unit

- Strobing

Asynchronous Transfer Using Strobing

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

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- Handshaking

Asynchronous Transfer Using Handshaking

13-4) Serial Communication

- Asynchronous Transmission

Format of Asynchronous Serial Transfer of Data

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.13 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 5/11

- Synchronous Transmission
- The Keyboard Revisited

Keyboard Controller and Interface

- A Packet-Based Serial I/O Bus

I/O Device Connection Using the Universal Serial Bus (USB)

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.13 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 6/11

Non-Return-to-Zero Inverted Data Representation

USB Packet Format

13-5) Modes of Transfer

Program control, Interrupt-initiated, Direct Memory Access, an I/O
processor

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.13 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 7/11

- Example of Program-Controlled Transfer

Data Transfer from I/O Device to CPU

Flowchart for CPU Program to Input Data

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

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- Interrupted-Initiated Transfer

13-6) Priority Interrupt

- Daisy Chain Priority

Daisy Chain Priority Interrupt

One Stage of the Daisy Chain Priority Arrangement

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

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- Parallel Priority Hardware

Parallel Priority Interrupt Hardware

13-7) Direct Memory Access

CPU Bus Control Signals

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.13 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 10/11

- DMA Controller

Block Diagram of a DMA Controller

- DMA Transfer

DMA Transfer in a Computer System

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

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13-8) I/O Processors

Block Diagram of a Computer with I/O Processor

CPU-IOP Communication

13-9) Chapter Summary

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH