MICHAEL DAVID TOMME

114 PEBBLE BROOK CIRCLE

MADISON, AL 35758
CELL: 256-694-0976
EMAIL: mt66d692@westpost.net
EDUCATION:
Bachelors of Science in Electrical Engineering (BSEE) University of
Alabama in Huntsville 1985.
Also core courses for Management Degree, and partial completion of
Masters with emphasis on control theory.
SUMMARY:
Design of boards and systems, and ASICs and FPGAs in VHDL and
SystemVerilog 2005 and Verilog, and software definition and
development. Embedded system development Design entry, synthesis,
simulation, and physical ASIC and FPGA design and verification.
Technology areas include commercial and defense work with
communications, networking, server design, aircraft and ground
vehicle electronics, high performance power design. Extensive
microprocessor and DSP design experience. Design of subsystem
components for Infrared ( IR ) and optical sensor systems, including
interface electronics for Staring Focal Plane Arrays (SFPA),
prescreener and postprocessing elements including array computer
board design that allows scalable processing architectures.
Detailed design experience in latest technologies in DSPs, SONET,
design of high speed SONET framers - OC-48 and OC-192 (2.5GHz and
10GHz, full duplex), 1Gigabit and 10Gigabit Ethernet (copper and
optical), WIS standard ANSI T1.416-2000 (simplified Ethernet to SONET
OC-192), and Firewire 800 (1394b with TI PHY and LLC ). Experience
includes detailed RTL and physical design and layout of ASICs and
FPGAs in VHDL, Verilog, and other HDLs, Gigabit Ethernet over optical
and existing CAT5 copper cable, architectural design and analysis,
Firewire 400/800 ( 1394b ), Digital and Mixed Signal Processing,
embedded microprocessor design, micro-coded controllers, Direct
Digital Synthesis, high speed system backplanes, clock trees,
transmission line analysis, military aircraft interface, active and
passive filter design, digital and analog phase lock loop design,
I/O, global and distributed memory design. DMA, L1 L2, L3 and L4
systems with DDR SDRAM, Flash and CACHE design, analog, controller
and microprocessor based guidance control, Power PC and Intel
processor board design, and networking. Brushless DC motor control
logic and high current driver control circuits. C++ certified and
familiar with popular operating systems and development systems as
well as Visual Basic and Visual C++. Designed the first Text to
Speech high speed communication electronics for an aircraft. Signal
integrity lead for IBM PC mainframe server, and designer of the
electronics. Optical and Infrared sensor interface electronics.
Video. CODEC. Design of first Text to Speech Communication for
aircraft. Adherence to DO-254. Design of high fidelity, high power
supplies using DSP algorithms implemented in FPGAs and/or DSP chips.
 TOOL PLATFORMS:
Synopsis, Mentor Graphics, Cadence, DAZIX, VeriBest, Altera Quartus
in Cyclone and MAXPLUS, Actel and Actel Fusion, Xilinx (Virtex,
Virtex-II and Virtex Pro and others) ISE, EDK, Synplicity Synplify,
ModelSim and Matlab. Visual C++, Visual Basic.
Some tool components:
Cadence SpectraQuest transmission line simulation and lead on IBM
signal integrity team. ViewLogic, Orcad, Autologic, HDL Designer,
Leonardo, FPGA express and Physical Compiler and Design Compiler.
Cadence Dracula, POMPEII. Cadence Orcad schematic capture and PSPICE.
Mentor Expedition PCB. Cadence Allegro.
OPERATING SYSTEMS:
Linux, uCLinux, RedHawk, Unix, VxWorks
MICROPROCESSORS AND DIGITAL SIGNAL PROCESSING (DSP):
Analog Devices Blackfin ( 21535 or BF535, BF533, BF561 dual core DSP
) and 2188 micro, various ARM architectures, Intel Xeon, Motorola
68000/68010/68020/68030, Power PC 850, Intel 80960, AMD 29000, PACE
1750, proprietary array processor, ZIP3232 array processor, various
2901, 2910, 8031.
BUS:
Proprietary high-speed bus designs, PC133 P6 Intel processor bus,
Power PC, PC104/ISA, PCI, PCI Express, cPCI (Compact PCI), Micro-Vax
Q Bus, VME/VSB and VXI Busses, PCI, IBM Channel and Micro-Channel,
POS PHY Levels 2-3, Utopia, and USB (Universal Serial Bus).
NETWORK CIRCUIT DESIGN:
SONET OC-192, OC-48 POS, - Packet Over SONET PHY 3,4 (2.5 to 10
Gigabit optical), T1, T3, 10/100/1000Base-T - optical and copper,
Open Transport Network (OTN).
ANALOG:
Digitally controlled analog circuitry with analog feedback loops
with OP Amp filter and level translators, isolation circuits, mixed
signal, passive filtering, transistors, relays, Voltage Regulators,
A/D, D/A, frequency synthesizers. 3 axis gyros, audio,
communications, and control panel applications for military aircraft
and ground vehicles.
EXPERIENCE:
UNITED TECHNOLOGIES CORPORATION, PRATT & WHITNEY, MARSHALL SPACE
FLIGHT CENTER
March 2009 a" Present
Constellation Space Program Ares I Rocket
*
 Constellation program has been terminated
Detailed Design Engineer responsible for design and development of
Ares I control loop hardware and software communications designs and
architectures, and printed circuit boards, including cPCI/PCIExpress
(PCI-E) communications and DO-254 VHDL implementations of DSP
Algorithms on a Quad-Processor based system running Linux RedHawk.
*
PCI development of high performance software architecture using
complex Bridge chips between GigaHertz North Bridge Processors Quad,
PCI Express GigaHertz extension to 28 circuit boards across 4
CompactPCI (cPCI) chassis
*
Detailed design, simulation and development of Cyclone II FPGA in
D0-254 VHDL, schematic and printed circuit board (PCB) on Mentor
Graphics Expedition, 28 instantiations of which reside in the PCI
architecture.
REDSTONE TEST CENTER, REDSTONE ARSENAL
March 2008 a" March 2009
HELLFIRE Missile Program
Detailed Design Engineer responsible for design and development of
Apache HELLFIRE FLIR test electronics. Specifically in emulating and
testing of HELLFIRE missile targeting in the Staring Focal Plane
Array (FLIR) Infrared imaging and acquisition.
*
design and development of circuit boards in PCI and PC104
architectures including the Printed Circuit Board (PCB) design and
schematic design on Altium integrated FPGA/Schematic/PCB design and
simulation flow.
*
Hi-Fidelity power supply design using high frequency switchers
*
DO-254 VHDL and Verilog FPGA designs, simulation and development on
Altium FPGA integrated design flow.
*
closed loop control circuits
TOMME ENGINEERING
2004 a" 2008
Avionics and other Defense and Space Communications and Guidance and
Control in high profile fighter jets, rockets, missiles, commercial
aircraft and helicopters
 Project Engineer responsible for negotiating contracts to design and
develop system and sub-system projects and performing detailed design
and overseeing design and support functions performed by other team
members in a well equipped laboratory in Research Park, Huntsville,
AL, along with integration and development labs across the country.
*
Multi-Axis Gyro Control Circuits for high speed navigation and
target acquisition systems
*
closed loop control circuits in aircraft and missiles using DSP type
functions implemented in FPGAs
*
high fidelity, high performance power supply control circuits
implementing DSP
*
closed loop control circuits in aircraft and missiles using DSP
functions implemented in FPGAs
*
high fidelity, high performance power supply control circuits
implementing DSP functions in FPGAs and/or DSP silicon
*
ASIC emulation using FPGAs
*
Software Radio implemented in VHDL in a Xilinx FPGA (4 channel,
AM/FM stereo)
*
VHDL (VHDL IEEE 9-State and 3-State) and Verilog (with Verilog-A
modeling) test benches for ASIC and FPGA verification
*
DO-254 adherence
*
Sliding time and automated, batch mode results analysis
*
aircraft fire and safety circuits
*
PC Mainframe design
 *
Design and bring-up of uCLinux on Blackfin DSP processor boards
*
Communications Electronics (OC-3, OC-12, OC-48, OC-192, GigE,
10GigE)
Projects and Capabilities
Future Combat Systems ( FCS )
Lead Architect responsible for the integration and qualification of
subsystems from FCS contracting agencies into the FCS system variants
Designed communications systems, laser range finder, and target
recognition and acquisition systems for variants of the FCS system of
systems
cPCI, PC104 and PCIExpress bus based systems with GigE and 10GigE
interconnect between sub-systems and SERIAL Rapid I/O used for
embedded system point to point interconnect on Xilinx Vitex FPGA's
(low voltage, differential)
Interconnect design and verification, including signal connectivity,
signal integrity and transmission line analysis and simulation for
critical paths between subsystems and system. CADENCE SPECTRAQUEST -
MULTI-GIGABIT
EMI design, planning, and debug
LED, LCD Displays with improved color rendering and high pixel
resolution
Optical and Electro-Optical design components, and the design of
electronic control sub-elements for control of these sub-systems
NASA -- ARES Project
Lead Hardware Architect responsible for design of prototype
electronics subsystems for demonstration and validation of Ares I
Upper Stage processing and communications systems with an isochronos,
1394b based, 20msec outer control loop and 500usec inner loop, with
1553 LRU interfaces and 485 status and control.
FPGA (Altera Cyclone/Mentor/FPGA Advantage/Synplify/ModelSim SE)
cPCI bus interface with sensor/actuator interface and emulation) and
board design for LRU emulators, providing a capability to test Flight
Hardware and Flight Software in integration labs
Interconnect design and verification, including signal connectivity,
signal integrity and transmission line analysis and simulation for
critical paths between subsystems and systems. MENTOR GRAPHICS
HYPERLYNX
Responsible for the port of Green Hills Integrity onto the PowerPC
platform
 High Speed communications performance testing in the lab
Patriot III and FK-90
Designed various processor and control circuits for guideance and
control of these derivatives of the Pershing Missile
Boeing Plastic Plane
Designed A/C motor control circuit and safety processing circuits
VHDL implementations in Actel FPGAs
SONET (OC-192) and Gigabit Ethernet and 10GigE
Physical layer expertise, including techniques for clock recovery,
echo cancellation, etc
FPGA controlled circuits with safety and feedback
Matlab used for full system simulation, allowing for processor code
(C++) to run in the same simulation run with the VHDL for FPGAs
Detailed and exhaustive Static Analysis of timing in complex FPGA
and ASIC circuits (Static Timing Analysis)
uCLinux and RTLinux
Port of and high performance programming of RTLinux and uCLinux to
Blackfin Platforms
Embedded System/Software Development
uCLinux bring-up on Blackfin platforms. Designed dual-DSP Blackfin
board for communications on the Apache helicopter.
VxWorks used in real time emulation of IBM mainframe for mainframe
extension product
UML 2.0 adherence to constructing, and documenting the artifacts of
distributed object systems.
Very High Speed layout and Signal Integrity ( SI ) analysis
Extensive use of Mentor's Expedition PCB and HyperLinx and Cadence'
SpectraQuest used in transmission lines up to 10GHz.
Brushless DC motor control and Radar power supply circuits
design of closed loop H-Bridge control electronics
DSP based designs implemented in VHDL in FPGAs
PWM control at 2nd order fidelity
10 times oversampling of current and voltage derivatives and 1st
order positions
2nd order control in output drive
 Infrared and camera design and integration
Staring Focal Plane Array (SFPA) scan control and data acquisition
Prescreener functions implemented in hardware for performance
512x512 Sensor arrays, with 1024 degrees of freedom scanned at 100Hz

Various video, video processor TI DM642

SANMINA-SCI
2002-2004
Responsible for detailed design and programming of ultra-low power
(dynamically variable core and system clocking frequencies,
rapid-recover standby mode) multi-processor DSP card, for the Apache
helicopter, with two Blackfin DSPs with Flash and static RAM and an
Actel Pro ASIC plus FPGA. Defined and developed control and
processing software modules, h/w / s/w interface, and FPGA in DO-254
compliant VHDL with DO-254 test processes. Embedded software
development in C++ using Visual C++. Emplemented Green Hills
Integrity for Security.
Designed memory control and I/O control logic for the Blackfin, as
well as power control logic and PLL control logic to implement a two
step power-up sequence to allow the Blackfin to implement PLL ramp-up
functions. Responsible for DSP design in the message routing system.
Performed detailed design of FPGA in VHDL with Actel ProASIC Plus
with ModelSim and Synplicity.
Responsible for architecture and detailed design of 1394b Firewire
800 using TI PHY and LLC chips with Xilinx FPGA in Multi-Mission
communications networks, and for design of the audio channel
algorithm for application specific requirements, guidance of design
of FPGA providing LLC control and data operations with control of
interrupts generated by Asynchronous Packets, and definition of
algorithms used for coding the DSP functions used in communications.
Responsible for participation in architectural definition for a
sonar system used for submarine detection.
Design engineer responsible for design of F-15 communications
electronics (ICSCP) digital cards using Intel 8031 controller.
L-3 COMM
Short term assignment 2002
Responsible for initial design of Gigabit Bluetooth over Ethernet
Switch (1000Base-T) over existing copper CAT5 cable which provides 8
seconds of stored data to be routed to the switch fabric or the
control processor on the CompactPCI backplane. RF protocol embedded
in Ethernet packets and processed in FPGA, with maintenance functions
done on the supervisory level. Board provides hot-swap capability and
design is implemented in a Xilinx Virtex II 3000 FPGA, implemented in
DO 254 compliant VHDL, using Mentor Graphics and Model Technology
tools (MTI). Design and verification adherent to DO-254 practices.
Design includes 8 Gig of SDRAM, and implements MAC function cores,
with GMII interfaces, and a cPCI core, PHY chips, and magnetics.
NEC ASIC DESIGN CENTER
2001-2002
Responsible for physical design and layout, using NEC tool
processes, Synopsys, and Cadence tools of sub-micron ASICs for OC-48
SONET chip-set providers for systems using Intel processors and PCI
synchronous and asynchronous protocols, 33 and 66MHz operational
busses. Test Bench development and Bourne and C-Shell scripting.
LUCENT TECHNOLOGIES, A BELL LABS COMPANY
2000 - 2001
Responsible for detailed design and leadership of design team
developing a 2.5 Gbit OC-48 to 2xGigabit Ethernet optical switch
transmitting and receiving Ethernet packets / frames inserted /
extracted with an HDLC like Packet Over SONET (POS) proprietary
protocol. Design effort includes detailed design of the SONET framer
function using a Xilinx Virtex E 1000, differential 155MHz PECL
STS-48 card-to-card bussing, 155MHz programmable, differential PECL
system clock tree, and a Power PC interface. Also designed a generic
Motorola Power PC 850 processor board with NAND Flash, SDRAM and a
generic I/O function implemented in a Xilinx Virtex 150, which is
used as a system controller and/or switch controller and resides as a
child card on a parent optical card in each slot of the system. Design
includes 256k of internal RAM blocks, 155MHz differential PECL 16 bit
transmit and receive busses, four parallel 310MHz pipelines, global
clock tree with less than 300psec skew, Utopia interface and uPC
native bus interface.
IBM - HIGH PERFORMANCE SERVERS
1998 a" 2000
Responsible for developing very large, high performance, data
compression ASIC for use as a North Bridge chip in high performance
servers performing video and application data compression, in VHDL
with NEC's CB-11 process. Lead on design of proof of concept system
for the data compression ASIC. Designed multi-phased, multi-frequency
system clock tree for high performance server product with 4 x 766MHz
Xeon processors on 133MHz P6 Bus, 16Gbytes SDR global memory,
40Mbytes Double Data Rate (DDR) SDRAM L3 CACHE running at 266MHz, and
10 PCI synchronous and asynchronous, 33 and 66MHz slots. Performed
various simulation efforts. Designed L3 CACHE interface. Designed one
of the first commercial LED Displays with controller electronics.
Taught VHDL to design engineers. Performed timing and protocol design
debug of system level interfaces. Lead engineer on PCI signal
integrity team.
CHRYSLER AEROSPACE
1996 - 1998
Lead Designer of test set and LCD panel display for Bradley Fighting
Vehicle, a system with two Infrared Sensor based targeting systems,
high performance TI C40 based computer system, and various high-speed
data and video interfaces for use in SFPA sensor based control system.
Designed DSP in VHDL with supporting A/D and D/A circuits and LUT
RAMs, and emulated in Xilinx FPGAs using Xilinx Foundation with
Synopsis FPGA Express. Designed the 20 bit Digital Signal Processor
with 10 x 10 signed, two's complement multiply, divide, add,
subtract, square, square root, sine, cosine, tangent and arctangent
functions with radial trigonometry for control of 1 and 2 axis gyros
and brushless DC motors controlling missile fin operation and turrent
drive control, allowing for Lock-On-Target amidst vehicle motion
transients. DSP also created sine waves using Direct Digital
Synthesis with noise reduction techniques and included a digital
phase lock loop internal to the FPGA and ASIC. Also designed VHDL
Test Bench for Mark XII multi-warhead nuclear missile re-entry stage.
Performed full system simulation using Matlab with processor code
(C++) and VHDL. Nine-state IEEE VHDL modeling included VXI Bus,
various FPGA designs, processor elements, and re-entry vehicle
emulation.
INTERESTS:
Coaching church league softball, weightlifting, boating, outdoor
activities.
References:
Available upon request.