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Registers in the central processor

Registers are widely used in computers, and you will


Lecture 11 have met (or will meet) them in the architecture
course:

Registers Address Register


Data Register
Program Counter
Stack Pointer
&c.

September 2001 Computer Hardware Lecture 11 Slide1 September 2001 Computer Hardware Lecture 11 Slide2

The State Register The state register

We have also used registers in our synchronous The state register had a common clock for all the flip
design method to store the state of a finite state flops:
machine.
b3 b2 b1 b0
A set of n flip-flops can represent 2n states
D Q D Q D Q D Q

Clock

September 2001 Computer Hardware Lecture 11 Slide3 September 2001 Computer Hardware Lecture 11 Slide4

Parallel Data Serial to Parallel Conversion

Inside a computer data is organised in a parallel form. Register are used to convert data from serial form to
parallel form.
Thus a data register containing say 32 flip flops will
have a common clock, and all 32 bits will be set at the Each successive bit is read on a falling clock edge.
same time
Clock

However, for communications, serial data is used in


which the bits of a 32 bit word are sent one after the Serial Data
other. 1 0 0 1

time
September 2001 Computer Hardware Lecture 11 Slide5 September 2001 Computer Hardware Lecture 11 Slide6
A four bit serial to parallel convertor Timing serial Input

Note that the length of time taken to load serial data


will depend on the length of the shift register.
Parallel Out
b3 b2 b1 b0
10 01 01 10 1 In practice serial data is loaded at a much slower rate
than the processor clock, and a separate clock is used
Serial in D Q D Q D Q D Q
for the purpose.

Synchronisation with the main processor is achieved


Clock
using other control lines.

September 2001 Computer Hardware Lecture 11 Slide7 September 2001 Computer Hardware Lecture 11 Slide8

Parallel to Serial Conversion A four bit serial to parallel convertor

This is carried out in two stages:


Parallel Out
b3 b2 b1 b0

1. Load parallel data on to the D-type flip flops


Serial in D Q D Q D Q Serial out
2. Shift the data out in serial form D Q

This means we must somehow switch the input Clock

to the D-types b3 b2 b1 b0

Parallel In

September 2001 Computer Hardware Lecture 11 Slide9 September 2001 Computer Hardware Lecture 11 Slide10

The multiplexer The 2-input multiplexer

An electronic switch for digital circuits is called a Control


multiplexer.

A
It can be made up from AND and OR gates
Out

Like the D-type flip flop it is used extensively in B


hardware design.

Control=0: Out follows B


Control=1: Out follows A

September 2001 Computer Hardware Lecture 11 Slide11 September 2001 Computer Hardware Lecture 11 Slide12
Four bit shift register Multiplying and Dividing by 2

Multiplying by 2 in binary arithmetic is equivalent to


Parallel Output
shifting the bits of a number on place to the left and
PO 3 PO 2 PO 1 PO 0
filling the bottom bit with a 0
Load/ Shift
This can be done with a shift register
Serial In Serial
Mx Mx Mx Mx Out
D3 D2 D1 D0
Similarly, divide by 2 can be done by shifting right
PI 3 PI 2 PI 1 PI 0 one space and discarding the bottom bit.
Parallel Input

September 2001 Computer Hardware Lecture 11 Slide13 September 2001 Computer Hardware Lecture 11 Slide14

Multi Function registers Four function shift register

We saw how to make a register perform two Our next example will be a shift register with the
functions: following four functions:

Parallel Load 00 Hold


Serial Input or Output 01 Shift Right
10 Shift Left
We can extend this concept to registers that 11 Parallel Load
perform the arithmetic shifts
It will be controlled by a two bit binary number

September 2001 Computer Hardware Lecture 11 Slide15 September 2001 Computer Hardware Lecture 11 Slide16

Four Way Multiplexer Binary to Unary Convertor

We can give a shift register four functions by using a A binary to unary convertor simply calculats all
four way multiplexor (switch) to select the D input to minterms of the inputs. For one input, only one output
the flip-flops is non zero.
B1 U3
B0
Designing a four way multiplexer is similar to the two
way multiplexer, but we will do it in two stages to U2
generalise the design
U1

U0

September 2001 Computer Hardware Lecture 11 Slide17 September 2001 Computer Hardware Lecture 11 Slide18
Four way multiplexer Connecting up the shift register
Given a binary to unary convertor, the multiplexer
can be built trivially by providing a gating circuit. We can make the shift register as long as we like.
S1 S0
Binary to Unary Convertor
Multiplexer Control
B1 B0 S1
Gating circuit S0
U3 U2 U1 U0
MUX D Q MUX D Q MUX D Q
&c. &c.
A

B
Out Clock
Stage i+1 Stage i Stage i-1
C

D
September 2001 Computer Hardware Lecture 11 Slide19 September 2001 Computer Hardware Lecture 11 Slide20

We connect individual stages as follows Clock Dividers


POi
Clock dividers form an interesting useage of registers
Qi-1
Ci+1
Synchronous divide by 2 is easy:
Ai
Qi+1 Bi
O Di Qi Bi-1
Ci
Di D Q Clock
Mpx
Q'
Q

Clock
PIi

September 2001 Computer Hardware Lecture 11 Slide21 September 2001 Computer Hardware Lecture 11 Slide22

Divide by an integer Clocks and Watches

A synchronous divide In practice we may need to divide by much larger


by integer can be 0 numbers. Consider a wrist watch:
0
easily specified using 6
1 1
a Moore machine, and 0 A regulating crystal produces a steady waveform of 1MHz.
designed using our (That is 106 falling edges per second)
standard method. 5
1 2
0 A watch stepper motor requires 1 pulse per second to drive
it.
eg divide by 7 4 3
1 0
Hence we need to divide by 1,000,000

September 2001 Computer Hardware Lecture 11 Slide23 September 2001 Computer Hardware Lecture 11 Slide24
Clocks and Watches 2 Divide by 256

We could use a synchronous circuit to do this, but, it Dividing by 16 can be easily designed synchronously.
would require a synchronous counter with 106 states, Cascading two dividors gives us dived by 256
and therefore 20 D-Q flip-flops!

Hence, clock dividing is done in stages


Divide by 16 Divide by 16
Counter Counter Clk out

Clk in

September 2001 Computer Hardware Lecture 11 Slide25 September 2001 Computer Hardware Lecture 11 Slide26

The ripple through counter Using a counter to divide by any number

This delightfully simple counter can be arbitrarily Suppose that we wish to divide a clock by a number
large, but it is not synchronous. which is not a power of two.

The first step is to design a counter to the next higher


power of 2.
D Q D Q D Q
&c
Q' Q' Q'
In a simple example, if we wish to divide by 5, we
clk can design a counter to count to 8
b0 b1 b2

September 2001 Computer Hardware Lecture 11 Slide27 September 2001 Computer Hardware Lecture 11 Slide28

Using a counter to divide by any number Asynchronous Divide by 5


Clear
Recall that when we designed the flip flops we
included a clear input which set the output Q=0. D Q D Q D Q
&c
Q' Q' Q'

clk
We can get out circuit to count to 0,1,2,3,4, but as
soon as we detect 5 on the output we reset all the Q
values to 0.

Out

September 2001 Computer Hardware Lecture 11 Slide29 September 2001 Computer Hardware Lecture 11 Slide30

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