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A Tutorial
VTH
m Coxf t 1 + i f −1
t
L s ox
is the normalization current. 2 L
VDSAT
≅ ( 1 + i f − 1) + 4
ft if << 1 weak inversion,
W
=
gm if >> 1 strong inversion.
L I
2 mC oxft − 1
ft g m n
Normalized Current Transconductance-to-Current Ratio
ID φ t ng m 2
if = =
IS ID 1 + 1 + id
2
ftW
IS ′
= m n Cox φ tgm
2 L 0
I D 10
ID: saturation current
n: slope factor -1
10
( ) theory (n=1.35)
( ) simulation
(o o o o o o) experiment
-2
10
10-2 10 -1 10 0 10 1 10 2 103 10 4
i
WI MI SI
3 3
10 10
fT VDSsat
fo 2 φt
10
2
10
1
10
0
10
1
10
-1
10
-2 0
10 10 -2 -1 0 1 2 3 4
-2 -1 0 1 2 3 4
10 10 10 10 10 10 10 10 10 10 10 10 10 10
id id
WI MI SI WI MI SI
CL GBW
WL ≅ 2
C′ox fT
IBIAS=IC IBIAS=I D
DC Circuit +
CL +
VO
CL +
VO
+
VI - -
VI
- -
Transconductance gm 1 gm 1 2
-to-current-ratio = =
(gm/ID) IC φt ID φ t n(1 + 1 + i d )
DC Gain VA VA 2
A vo = − A vo = −
(Avo) φt φ t n(1 + 1 + i d )
Gain-Bandwidth 1 IC 1 ID 2
GBW = GBW =
Product (GBW) 2π CL φ t 2π CL φ t n(1 + 1 + i d )
Intrinsic Cutoff fT ≅
1
fT ≅
1
2( 1 + i d − 1)
Frequency (f T) 2πτ 2πτ
Minimum Output VDSsat
( 1 + i d − 1) + 4
VCEsat
≅ 6 to 8 =
Voltage (VO) φt φt
Low Voltage Analog Circuit
Design Techniques: Roadmap
Low voltage (LV) power supply circuit design techniques are addressed in
this tutorial. In particular:
(i) Introduction;
The floating gate voltage VF ,assuming that the initial charge QF in the floating gate is zero,,is
described by:
Metal Poly II
Poly I CFGD
VG1 CG1
VG1 VG1
VG2 VG2 CG2
VG2
VG3
CGn
VGn VGn
CFGS
S D
CFGB
N Diffusion
(a) Layout (b) Schematic Symbol (c) Equivalent Circuit
Floating Gate MOS Transistors
CG (control Gate)
Poly - I
Cg
Poly - II
CO = Cgs + Cgb + Cgd
S D
CT= CO + Cg
M2 G
m W/L
G
X
W/L
M1 S
S
(a) Self-Cascode Composite NMOS Transistor (b) Equivalent Simple Transistor
In practical cases, for optimal operation the W/L ratio of M2 should be larger
than that of M1, i.e. m>1.
The 2-transistor structure can be treated as a composite transistor, which has
a much larger effective channel length (thus lower output conductance).
The lower transistor M1 is equivalent to a resistor, but this resistor is input dependent..
The effective transconductance of the composite transistor is approximately
equal to the transconctance of M1:gm-eff =gm2/m=gm1
Equivalent Transistor Parameter
For the composite transistor work in saturation region, we know M2 should
in saturation and M1 is in linear region. Thus, we can write equations for these
two transistors as:
b2 1
i1 = (VGS − VX − VT )2
i1 = b 1 GS
V − VT − VX V X
2 2
m 1
If b2 = m ⋅ b1 b eq = b1 = b2
m+1 m+1
b eq = b1
m− >∞
Comments on VDSAT
Because transistor M1 always operates in linear region while the top
transistor operates in saturation or linear region. Voltage between the source
and drain terminal of M1 is so small that there is no discernable VDSAT
difference in both the composite and simple transistors. Thus,self-cascode
structure can be used in low voltage applications.
7. A.I.A. Cunha, M.C. Schneider, and C. Galup-Montoro, “An MOS transistor model
for analog circuit design”, IEEE J. Solid-State Circuits, vol. 33, No. 10, pp 1510-
1519, Oct. 1998
Potential LV Current-Mirrors
Goals: To reduce the input impedance and to increase the output impedance,
while keeping the voltage operation
Iout
Iin Iout
Iin Vref Vref
Mc
M2 Mc
Mm
M1 Mm
M1 Vmirror
Iout
Iout IB IB Iin Iout
IB IB Iin
Iin M5
Vcas M2 M4
M2 M2 M4 X
M1 M3 M1 M3 M1 M3
Vshift Vdd
Iin Iin IB1 Iin Iout
Iout M3 M4 Iout
ROB
AFB
M1 M2
M1 M2 M1 M2
IB2
How can we obtain a large impedance and low head room
for the tail current used in a differential pair ?
Vdd LV CURRENT-SOURCE
Z
M2 M1 Vx
A R0S
X − + Y I
I R0B
IB
R0S (b)
(a)
A conceptual Schematic of the low voltage current source. (a) Current source representation
(b) Architecture
Analog and Mixed-Signal Center (AMSC) TAMU
1 + g m1A o /(g o1 + g oB)
R os = (1)
g o 2(1+ Ao g m1 /( g o1 + g ) − A og m 2 / g o 2 )
oB
respectively. Ao is the DC gain of the error amplifier “A” and g oB ( R oB ) is the output
R os ≈ − R oB (2)
Note that the resistance is negative and is equal to the resistance of the reference source IB.
gm4
R os ≈ − (3)
g o3g o 4
Z
M2 M1
Y
Io
R 0S
M4 Vb
Vdd
IB ID
Z
M2 M1
−
A
+ Y
M3
X
I
V
IB R0B
R0S
Current Ref. Error Amplifier A
(a) Vss
Full implementation of the LV current source.
Analog and Mixed-Signal Center (AMSC) TAMU
Measured output current of the simple (curve A) and LV (Curve B) current source.
6mA
1.5V Drain Current
ID
4mA
Bulk-Source
VGS VBS Driven
2mA
Gate-Source
Driven
0mA
-3V -1.5V 0V 1.5V 3V
Gate-Source or Bulk-Source Voltage
Overhead of Bulk-Driven MOS Transistors
M1 M2
M1 M2
Vin Vb Vb Vin Vin
Vdd Vdd
Vdsat,Ib1 Vdsat,Ib1
SRVX, Swing range
Swing range of Vy
of Vx
Vdsat,M1 (a) VGS,M2 (b)
-Vss -Vss
SRVY=Vsup -Vdsat,Ib1 -VGS,M2
SRVX=Vsup-Vdsat,Ib1-Vdsat,M1 = Vsup-Vdsat,Ib1-Vdsat,M2-VT
The bulk-driven amplifier is more suitable for low voltage operation. Please
notice that the maximum allowable voltage at Vx is VDIODE.
Advantages of Bulk-Driven MOS
Transistors
• The depletion characteristic allows zero, negative, and even small
positive values of bias voltage to achieve the desired dc current. This
can lead to larger input common mode voltage range and voltage
swing that could not otherwise be achieved at low power supply
voltages. ( Please refer the following example in this section and bulk-
driven differential pair discussed in following sections )
• We can use the conventional gate to modulate the bulk-driven MOS
transistor.
• Example
Assume for the low voltage amplifiers, power supply voltage is
Vsup = Vdd+|Vss|<V DIODE+Vdsat ,
where VDIODE is the forward Si diode cut-in voltage.
The voltage swing of Vx ( Figure a, the amplifier with bulk-driven MOS
FETs ) has only 2Vdsat’s decrease over Vsup. In such a low voltage, the
conventional gate-driven amplifier ( Figure b ) fails to operate or may be
greatly limited in voltage swing.
Disadvantages of Bulk-Driven MOS
Transistors
• The transconductance of a bulk-driven MOS FET is substantially
smaller than a conventional gate-driven MOS transistor. This may
result in lower GBW and worse frequency response, but better
linearity and smaller power supply requirements.
• For a conventional gate-driven MOSFET, the frequency response
capacity is described by its transitional frequency, fT,
gm
fT , gate − driven =
2p C gs
• For the bulk-driven MOSFET, fT is given by
g mb h gm
fT ,bulk − driven = =
2p (Cbs + Cbsub ) 2p (Cbs + Cbsub )
GM VOUT = GMROUTVIN
VIN
VDD
IOUT
ROUT = 8.3 Mohms
1.2 AMI Technology M7 M8
IBIAS VSS
Vout
M3 M4
M5 M6
VSS
EXPERIMENTAL TEST SETUP
DESIGN A - REFERENCE OTA
DESIGN A - REFERENCE OTA
VDD
M9 M4 M3 M11
M10
M12
VSS
MM1 M1 M2 MM2
Vi- Vout
M16 Vi+
VDD
ISS
M8 M6 M17 M18 M5 M7
VSS
DESIGN B - CURRENT DIVISION and SD OTA
VDD
M8 M7
M9 M10
ISS
VSS Vb
MM1 M1 M2 MM2
Vout
Vi- Vi+
M5 M3 M4 M6
VSS
DESIGN C - FLOATING GATE OTA
VDD
M8 M7
M9 M10
ISS
VSS
VG
MM1 M1 M2 MM2
Vout
Vi- Vi+
M5 M3 M4 M6
VSS
DESIGN D - BULK DRIVEN OTA
R2
R1 R2
• From the table, we see that for inverting configuration, rail-to-rail input
common mode range is not needed. But for non-inverting configuration,
some input common mode voltage swing is required, especially for a
voltage follower which usually works as an output buffer, we need a rail-
to-rail input common mode voltage range! To make an Op Amp work
under any circumstance, a differential input with rail-to-rail common
mode range is needed.
To the next
stage
Vi+ Vi-
Vi+ Vi-
Ib1
To the next
stage
Vdd Itail
Vdsat,Ib
gm
Ib VGS,M1,2
Vi+
M1 M2 Vi-
Vdd Itail
To the next
stage gm
VCMR
Vdd
There should be an IP
Ib
subsequent stages
Summation and
overlap between
VCMR,N
Current
VCMR,P and VCMR,N , Vi+ Vi-
so the minimum
power supply M1 M3 M4 M2
VCMR,P
voltage requirement
is IN
( 4Vdsat+VTN+VTP ) Mb2
Mb1
-Vss
P Pair N Pair Simple N-P complementary input stage
Almost all of the rail-to-rail input stages are doing
VSUP ≥ 4Vdsat+VTN+VTP in this way by some variations! But how well
does it work?
Observations on transconductance performance
for the entire region.-
gmN gmP
Region II. When Vicm is in the middle range, both of the P
and N pairs operate. The total transconductance is given
-Vss by gmT = gmN+gmP=2gm.
Vdd
Common Mode Voltage
Region III. When Vicm is close to the positive rail, only N-
The total transconductance of the input channel pair operates. The total transconductance is
stage varies from gm to 2gm, the given by gmT = gmN=gm.
variation is 100% !
How does the CMRR varies with the input common-mode signal ?
6 90
CMRR(dB)
CMRR
4 80
Vio(mV)
2 70
0 60
Vio
Vi- C2 C2'
Vi+ Vi+ Vi-
M1 M2 ViFG- C '
ViFG+
C1 1
IB IB
(a) Floating Gate DP (b)
Io+ Io-
VB
Vi-
Vi+
M1 M2
IB
(c) Bulk Driven DP
Another Potential Solutions for Rail-to-Rail Amplifiers
One more Rail-to-Rail Op Amp Technique
M1
V1 M2 V3
vSHIFT vSHIFT
vI+ vI-
vSHIFT vSHIFT
V2 M4 V4
M3
IL1 IL2 R10 R11
V1 Q1 V3 Q VB2
Q2
To next stage
10
RL1 RL2
vI+ vI- Q11
RL3 RL4
Q3 Q8 Q9
V2 Q4 V4
IL3 IL4 R8 R9
0.2
VSHIFT VI,CM (V)
0.2 0.4 0.6 0.8 1.0
ML1 ML4 M9 Vdd
ML2 ML3 M11
IL M1 M10 M12
To next stage
RL1 M2 RL2
Level-Shift Current
vI+ vI-
Generator
ML6 ML7 M5 M7
ML8
-Vss
N-P complementary input stage Current summation
with dynamic level shift
References
[1] J. H. Huijsing, and D. Linebarger, “Low voltage operational amplifier with rail-to-
rail input and output stages,” IEEE Journal of Solid-State Circuits, vol. SC-20, no.
6, pp. 1144-1150, December 1985
[2] W.-C. S. Wu, W. J. Helms, J. A. Kuhn, and B. E. Byrkett, “Digital-compatible
high-performance operational amplifier with rail-to-rail input and output ranges,”
IEEE Journal of Solid-State Circuits, vol. 29 , no. 1, pp. 63-66, January 1994
[3] R. Hogervorst, R. J. Wiegerink, P. A. L. de Jong, J. Fonderie, R. F. Wassenaar, and
J. H. Huijsing, “CMOS low-voltage operational amplifiers with constant-gm rail-
IEEE Proc. ISCAS 1992, pp. 2876-2879
[4] R. Hogervost, J. P. Tero, R. G. H. Eschauzier and J. H. Huijsing, “A compact
power-efficient 3-V CMOS rail-to-rail input/output operational amplifier for VLSI
cell libraries,” IEEE Journal of Solid-State Circuits, vol. 29, no. 12, pp. 1505-
1513, December 1994
[5] R. Hogervorst, S. M. Safai, and J. H. Huijsing, “A programmable 3-V CMOS rail-
to-rail opamp with gain boosting for driving heavy loads,” IEEE Proc. ISCAS
1995, pp. 1544-1547
[6] J. H. Huijsing, R. Hogervorst, and K.-J. de Langen, “Low-power low-voltage
VLSI operational amplifier cells,” IEEE Trans. Circuits and Systems-I, vol. 42. no.
11, pp. 841-852, November 1995
References ( cont’d )
[7] W. Redman-White, “A high bandwidth constant gm, and slew-rate rail-to-rail
CMOS input circuit and its application to analog cell for low voltage VLSI
systems,” IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 701-712, May
1997
[8] C. Hwang, A. Motamed, and M. Ismail, “LV opamp with programmable rail-to-
rail constant-gm,” IEEE Proc. ISCAS 1997, pp. 1988-1959
[9] C. Hwang, A. Motamed, and M. Ismail, “Universal constant-gm input-stage
architecture for low-voltage op amps,” IEEE Trans. Circuits and Systems-I, vol.
42. no. 11, pp. 886-895, November 1995
[10] R. Hogervost, J. P. Tero, and J. H. Huijsing, “Compact CMOS constant-gm rail-to-
rail input stage with gm-control by an electronic zener diode,” IEEE Journal of
Solid-State Circuits, vol. 31, no. 7, pp. 1035-1040, July 1996
[11] M. Wang, T. L. Mayhugh, Jr., S. H. K. Embabi, and E. Sánchez-Sinencio,
“Constant-gm rail-to-rail CMOS op-amp input stage with overlapped transition
IEEE Journal of Solid-State Circuits, vol. 34, no. 2, pp. 148-156,
February 1999
[12] G. Ferri and W. Sansen, “A rail-to-rail constant-gm low-voltage CMOS
operational transconductance amplifier,” IEEE Journal of Solid-State Circuits, vol.
32, no. 10, pp. 1563-1567, October 1997
References ( cont’d )
[13] S. Sakurai and M. Ismail, “Robust design of rail-to-rail CMOS operational amplifiers for a
IEEE Journal of Solid-State Circuits, vol. 31, no. 2, pp. 146-
156, February 1996
[14] J. H. Botma, R. F. Wassenaar, and R. J. Wiegerink, “Simple rail-to-rail low-voltage constant
transconductance CMOS input stage in weak inversion,” Electronics Letters, vol. 29, no. 12,
pp. 1145-1147, June 1993
[15] V. I. Prodanov and M. M. Green, “Simple rail-to-rail constant transconductance input stage
operating in strong inversion,” IEEE 39 th Midwest Symposium on Circuits and Systems, vol
2, pp. 957-960, August 1996
[16] J. H. Botma, R. F. Wassenaar, and R. J. Wiegerink, “A low voltage CMOS op amp with a
rail-to-rail constant-gm input stage and a class AB rail-to-rail output stage,” IEEE Proc.
ISCAS 1993, vol. 2, pp. 1314-1317, May 1993
[17] J. F. Duque-Carrillo, J. M. Valverde, and R. Perez-Aloe, “Constant-gm rail-to-rail common-
IEEE Journal of Solid-State
Circuits, vol. 28, no. 6, pp. 661-666, June 1993
[18] A. L. Coban and P. E. Allen, “A low-voltage CMOS op amp with rail-to-rail constant-gm
input stage and high-gain output stage,” IEEE Proc. ISCAS 1995, vol. 2, pp. 1548-1551,
April-May 1995
[19] J.F.Duque-Carrillo et al, “ 1-V Rail-to-Rail Operational Amplifiers in Standard CMOS
IEEE Journal of Solid-State Circuits, vol. 35, no. 1, pp. 33-44, January 2000
Voltage Multistage Transconductance Amplifier Topologies
For LV Power Supply.
• Good voltage gain can be obtained using cascode stages. But these stages
are not amenable for LV power supply.
• Direct Cascade of simple (inverting) stages gives the required voltage gain
without control of poles and zeroes.
I b1 Ib 2 I b1 M2
Vin V0 Vi V0 Vi Vx
Vx
M1 M2 M1 CP Ib 2
g m1 CL CP
C P g m2
V (s ) + g m1g m 2 / C p C L
H (s ) = 0 ≅
Vin (s ) C L C p C pC L 2
1 + s + + s
g 02 g01 g01g 02
g m1 CL
C p g m2
V0 (s ) g m1(g m2 − sC m1) / C LC m1
H (s ) = =
Vin (s ) s 2 + s (g 01(C L + C m1 ) / C LC p + g m 2 / C L + g02 / C L )+ g 01g 02 / C LC m1
V0 (s ) g m1(g m2 − sC m1) / C LC m1
H (s ) = =
Vin (s ) s 2 + s (g 01(C L + C m1 ) / C LC p + g m 2 / C L + g02 / C L )+ g 01g 02 / C LC m1
C m1
Now the corresponding H(s) becomes:
Vin V0
g m2 CL − g m1g m2
g m1 H (s ) =
s 2C m1C L + sC m1g m 2 + g01g 02
g mf g mf = g m1
No zero
C m1
C m2
V0
Vi
g m1 g m2 g m3 CL
g mf 2
g mf 1
Three-stage amplifier topology with NGCC
g g g g
A 0 = m1 m3 m 2 and f1 = GB = m1
g 01g03 g 02 C m1
g g g g
f 2 = m2 , f 2f3 = m2 m3 ; f i = mi
Cm2 C m2 C L C mi
C m1
C m2
Vi 1 2 3 Cm3 V0
(a) Multipath nested miller compensation topology.
FF
g m1 g m2 g m3 − g m4
g mf
C m1
C m2
Vi 1 2 3 Cm3 V0
(b) An abstract model for the amplifier proposed by
g m1 g m2 g m3 − g m4 Castello, et.al.
g mf
C m1
Vi V0 (c ) The amplifier with multipath miller zero
cancellation.
g m1 g m2
− A0
H (s ) =
(1 + a1s + a 2s 2 + a3s3 )
C m1 s
1+
C m2 P
1
Vi C m3 V0 GB
P1 =
CL A0
g m1 gm2 g m3 g m4
1 1 1
a1 = , a2 = , a3 =
f2 f 2 f3 f 2f 3f 4
g mf 3
1 C C 1 C mi
= m2 m3 , =
f 2 f 3 g m2 g m3 f i g mi
g mf 2
g mf1
Four stage amplifier topology with NGCC (Fan You et al)
f1 < f 2 < f 3 ≤ f 4 , f1 = GB
f2
f4 >
1 − f2 / f3
• Power Comsumption
n− 1 α f C mi g
P = (VDD − Vss )I n 1 + ∑ i i , αi = , α i f i = mi
i=1 f n CL CL
I n and f n are current and frequency normalization factors, respectively.
Comparison of Several Topologies.
g g
V0 (s ) 1 − b1s − b 2s 2 − b3s 3 ki = mi , i = 1,3 and f i = mi
= − A0 , g oi C mi
Vi (s ) 2 3
(1 + s / P1)(1 + a1s + a 2s + a 3s )
Where
f GB
A 0 = k1k 2k 3k 4 , P1 = 1 =
A 0 A0
Comparison of Polynomial Coefficients for Four Stage NMC and NGCC Amplifier.
Design
Ph(s) a1 a2 a3
(g m 4 C m 2 − g m 2 C m 3 ) (g m 4 − g m 2 − g m 3 )C m 2 C m 3 Cm 2Cm3CL
NMC g m 2g m 3g m 4 g m 2 g m 3g m 4 Complex
g m 2g m 4
Cm2 Cm 2Cm3 Cm 2Cm3CL
NGCC gm2 gm 2gm3 g m 2 g m 3g m 4 Simple
Z(s) b1 b2 b3
Cm3 Cm 2Cm3 C m1C m 2 C m 3
NMC gm 4 gm3gm 4 g m 2 g m 3g m 4
NGCC 0 0 0
C m2
Vi C mn V0
g m1 g m2 g mn g mn + 1
g mfn Level n
g mf 2 Level 2
g mf 1 Level 1
Conceptual multistage amplifier topology with NGCC.
C m1
Vi V0
g m1 A (s )
g mf 1
Abstract model.
Vdd
C m1
Vi V0 g m2
M12 M13
G m1 G m2 M 22
G mf 1 Vout
Vb1
M14
g mf 1
(a) Representation
Vb 2
Vi Mf 1
M11
M 21
G m1 ⇒ M11 − M14 , g mM11 = g m1 g m1 Vss
G m 2 ⇒ M 21 − M 22 , g mM22 = g m2 (b) Transistor Level
G mf 1 ⇒ Mf 1
Vdd
g m4
V+ C m2 Cm3 Vout
V−
C m1
Vb 2 gmf 2
Vb1 gmf 3
Vb 3
M3 M 4 M5
gmf1
g m1 g m2 g m3
Vss
4 40
2 20
0 0
1 2 3 4 5 6 7 8
f4/GB
7.5 * NMC
7 +
NGCC
*
Normalized Power
6.5
6 *
+
5.5
*
5
+
*
4.5 +
+ *
4 + *+
*+ *+
3.5 * *
3
0.5 1 1.5 2 2.5 3
Ts*GB
The normalized power consumption of the NGCC and the NMC amplifiers as
a function of the normalized settling time.
K.N. Leung, P.K. T. Mok, W.-H. Ki, and J. K. O. Sin, “ Three-Stage Large Capacitive Load
Amplifier with Damping Factor-Control Frequency Compensation, “IEEE J. of Solid-State
Circuits, Vol. 35, No. 2, pp. 221-230, February 2000
Joe Edgar
Analog and Mixed-Signal Center, TAMU