Documente Academic
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Documente Cultură
[1] Y. Neuvo, “Cellular Phones as Embedded Systems”, ISSCC Dig. Tech. Papers,pp.32-37,
February 2004.
[2] S.Y.Hui and K.H.Yeung, “ Challenges in the Migration to 4G Mobile Systems”, IEEE
Communications Magazine, pp.54-59, December 2003.
[3] M.Shafi, S.Ogose and T. Hattori, Wireless Communications in the 21st Century, John Wiley
& Sons, 2002.
[4] C. De Ranter and M. Steyaert, High Data Rate Transmitter Circuits: RF CMOS Design and
Techniques for Design Automation, Kluwer Academic Publishers, 2003.
[5] X.Li and M.Ismail, Multi-Standard CMOS Wireless Receivers: Analysis and Design,
Kluwer Academic Publishers, 2002.
[6] Adiseno, Mohammed Ismail, and H. Olsson, “A Wide-Band RF Front-end for Multiband
Multistandard High-Linearity Low-IF Wireless Receivers”, IEEE J. Solid-State Circuits,
vol. 37, pp. 1162-1168, August 2002.
[7] B. Razavi, “Challenges in the Design of Frequency Synthesizers for Wireless Applications,”
Proc. CICC, pp.395-402, May 1997.
[8] C.S. Vaucher, Architectures for RF Frequency Synthesizers, Kluwer Academic Publishers,
2002.
[9] J. Craninckx and M. Steyaert, Wireless CMOS Frequency Synthesizer Design, Kluwer Aca-
demic Publishers, 1998.
[10] B. Razavi, “A 1.8 GHz CMOS voltage-controlled oscillator,” ISSCC Dig. Tech. Papers,
pp.388-389, Feb. 1997.
[13] G.D. Vendelin, A.M. Pavio, and U.L. Rohde, Microwave Circuit Design Using Linear and
Nonlinear Techniques. John Wiley & Sons, 1990.
[14] U.L. Rohde, Microwave and Wireless Synthesizers: Theory and Design. John Wiley &
Sons, 1997.
[15] W.F. Egan, Frequency Synthesis by Phase Lock, John Wiley & Sons, 1981.
[16] R.E. Best, Phase-Locked Loops Theory, Design, and Applications, 2nd ed., McGraw-Hill
Inc, 1993.
[17] B. Razavi,ed. Monolithic Phase-Locked Loops and Clock Recovery Circuits,IEEE Press,
1996.
[18] D. Banerjee, PLL Performance, Simulation and Design, National Semiconductor, 1998.
[19] D.B. Leeson, “A simple model for oscillator noise spectrum,” Proc. IEEE, vol. 54, pp. 329
330, Feb. 1966.
[21] A. Hajimiri and T.H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,”
IEEE J. Solid-State Circuits, vol.33, pp.179-194, February 1998.
[23] www.mentor.com/ams/eldorf.html
[24] www.cadence.com/datasheets/spectrerf.html
[25] eesof.tm.agilent.com
[27] A. Aktas, F.Johnson, R.Ahola, and M.Ismail, “A 4 GHz CMOS PLL Frequency syn-
thesizer with wide-band VCO for multi-standard wireless applications,” Proc. of NORCHIP
2003, Nov. 2003.
[28] S.Li, I.Kipnis and M.Ismail, “A 10-GHz CMOS Quadrature LC-VCO for Multirate Optical
Applications”, IEEE J. Solid-State Circuits, vol.38, pp.1626-1634, October 2003.
[29] Y.Wu and V.Aparin, “ A Monolithic Low Phase Noise 1.7GHz CMOS VCO for Zero-IF
Cellular CDMA Receivers”, ISSCC Dig.Tech. Papers, pp.396-397, Feb. 2004.
[30] A.A. Abidi, “Direct-conversion radio transceivers for digital communication,” IEEE J.
Solid-State Circuits, vol.30, pp.1399-1410, December 1995.
[31] J. Strange and S. Atkinson, “ A direct conversion transceiver for multi-band GSM appli-
cation,” In 2000 RFIC Symp. Dig. Papers, pp.25-28, 2000.
REFERENCES 171
[32] A. Zolfaghari and B. Razavi, “A Low-Power 2.4-GHz Transmitter-Receiver CMOS IC,”
IEEE J. Solid-State Circuits, vol.38, pp.176-183, February 2003.
[33] Y. Tang, A. Aktas, M. Ismail, S. Bibyk, “ A fully integrated dual-mode frequency syn-
thesizer for GSM and Wideband CDMA in CMOS”, Proc. of the 44th IEEE 2001
Midwest Symposium, Vol. 2, pp.866-869, 2001.
[34] A. Kral, F. Behbahani, and A.A. Abidi, “RF-CMOS oscillators with switched tuning”,
Proceedings of Custom Integrated Circuits Conference, pp. 555-558, Santa Clara, CA May,
1998.
[35] J.F. Parker and D. Ray, “A 1.6-GHz CMOS PLL with On-Chip Loop Filter,” IEEE J.
Solid-State Circuits, vol. 30, pp. 1457-1462, Mar. 1998.
[37] J.W.M. Rogers, J.A. Macedo and C. Plett, “ The effect of varactor nonlinearity on the phase
noise of completely integrated VCOs,” IEEE J. Solid-State Circuits, vol. 35, pp. 1360-1367,
September 2000.
[39] C. Samori, A. L. Lacaita, F. Villa, and F. Zappa, “Spectrum folding and phase noise in LC
tuned oscillators,” IEEE Trans. Circuits Syst. II, vol.45, pp. 781-790, July 1998.
[41] D. F. Peterson, “Varactor properties for wide-band linear-tuning microwave VCOs,” IEEE
Trans. Microwave Theory Tech., vol. MTT-28, pp. 110-119, Feb. 1980.
[42] E.Hegazi and A.A.Abidi,”Varactor Characteristics, Oscillator Tuning Curves, and AM-FM
Conversion” IEEE J. Solid-State Circuits, vol. 38, pp. 1003-1009, June 2003.
[44] T. Soorapanth, C.P. Yue, D.K. Shaeffer, T.H. Lee and S.S. Wong, “Analysis and Optimiza-
tion of Accumulation-Mode Varactor for RF ICs”, Symposium on VLSI Circuits, pp. 32-33,
June 1998.
[45] A.S. Porret, et al., “Design of High-Q Varactors for low-power Wireless Applications”,
IEEE J. Solid-State Circuits, Vol.35 , pp.337-345, March 2000.
[46] R. Castello, P. Erratico, S. Manzini and F. Svelto, ”A ± 30% Tuning Range Varactor
Compatible with Future Scaled Technologies” , 1998 Symposium on VLSI Circuits Digest
of Technical Papers, pp. 34-35, June 1998.
172 CMOS PLLs AND VCOs FOR 4G WIRELESS
[47] APN1007, “Switchable Dual-Band 170/420 MHz VCO for Handset Cellular Applications,”
http://www.alphaind.com/
[48] E. Pedersen,“RF CMOS Varactors for 2 GHz Applications”, Analog Integrated Circuits
and Signal Processing, Vol.26, pp.27-36, January 2001.
[49] P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCOs,”IEEE J. Solid-
State Circuits, vol. 35, pp. 905-910, June 2000.
[50] P. Andreani and S. Mattisson, “A 2.4-GHz CMOS monolithic VCO based on an MOS
varactor,”in Proc. ISCAS’99, vol. II, pp. 557-560. May/June 1999.
[52] M.Tibeout, “A CMOS Fully Integrated 1 GHz and 2 GHz Dual Band VCO with a Voltage
Controlled Inductor,”Proc. ESSCIRC 2002, pp.799-802. 2002.
[53] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J.
Solid-State Circuits, vol. 34, pp. 717 724, May 1999.
[54] J.W.M. Rogers, D.Rahn, and C.Plett, “A Study of Digital and Analog Automatic-Amplitude
Control Circuitry for Voltage-Controlled Oscillators”, IEEE J. Solid-State Circuits, vol. 38,
pp. 352-356, January 2003.
[55] M. Margarit, J. Tham, R. Meyer, and M. Deen, “A low-noise low-power VCO with auto-
matic amplitude control for wireless applications,”IEEE J. Solid-State Circuits, vol. 34, pp.
761-771, June 1999.
[56] J. Long and M. Copeland, ‘The modeling, characterization, and design of monolithic
inductors for silicon RF IC’s,“IEEE J. Solid-State Circuits, vol. 32, pp. 357-369, Mar.
1997.
[59] J. Y.-C. Chang, A. A. Abidi, and M. Gaitan, “Large suspended inductors on silicon and
their use in a CMOS RF amplifier,” IEEE Electron Device Lett., vol. 14, pp. 246-248,
May 1993.
[60] C. P. Yue and S. S. Wong, “On-chip spiral inductors with patterned ground shields for
Si-based RF IC’s,”IEEE J. Solid-State Circuits, vol. 33, pp. 743-752, May 1998.
[62] FEMLAB,http://www.femlab.com/electro/
[65] A. M. Niknejad, R. G. Meyer, “Analysis, design, and optimization of spiral inductors and
transformers for Si RF ICs”, IEEE J. Solid-State Circuits, vol.33, pp.1470-1481, Oct. 1998.
[66] S.S. Mohan, M.Hershenson, S.P.Boyd, and T.H.Lee,“Simple accurate expressions for pla-
nar inductances,” IEEE J. Solid-State Circuits, vol. 34, pp. 1419-1424, Oct. 1999.
[69] P. Andreani, “A comparison between two 1.8 GHz CMOS VCO’s tuned by different var-
actor,” Proc. 24th European Solid-State Circuits Conf., Sep. 1998, pp. 380-383.
[70] W.B. Wilson, U.K. Moon, K.R.Lakshmikumar, and L. Dai, “A CMOS Self-calibrating
Frequency Synthesizer”, IEEE J. Solid-State Circuits Vol 35, pp.1437-1444, October 2000.
[71] Y.Shibahara and M. Kokubo, “A 0.7-V 200-MHZ Self-Calibration PLL”, IEICE Trans.
Elec., Vol.E85-C, No.8, pp.1577-1580, August 2002.
[72] J. Fenk, “Highly integrated RF-IC’s for GSM and DECT systems-A status review,” IEEE
Microwave Theory and Techniques, vol. 45, pp. 2531-2539, Dec 1997.
[75] http://www.abiresearch.com/reports/WLAN.html
[76] A.Aktas, K.Rama Rao, J.Wilson and M.Ismail, “A single chip radio transceiver for 802.11
a/b/g WLAN in 0.18um CMOS”, Proc. of 10th IEEE International Conference on Electronic
Circuits and Systems, ICECS 2003, Dec. 2003.
[77] A.Aktas, K.Rama Rao, J.Wilson, “A tri-band radio architecture for a WLAN transceiver”,
Sweden PRV. Patent No. 0102554-3. Mar. 2003.
[78] R. Ahola, A. Aktas, J. Wilson, K.Rama Rao, et al., “A Single Chip CMOS Transceiver for
802.11a/b/g WLANs”, ISSCC Dig. Tech. Papers,pp.92-93,Feb. 2004.
[79] B. Come, R. Ness, S. Donnay, L. Van der Perre, W. Eberle, P. Wambacq, M. Engels and
I. Bolsens, “Impact of front-end non-idealities on Bit Error Rate performances of WLAN-
OFDM transceivers,” Microwave Journal, February 2001.
[80] B. Razavi, K.F. Lee, and R.H. Yan, “ Design of High-Speed, Low-Power Frequency Di-
viders and Phase-Locked Loops in Deep Submicron CMOS,” IEEE J. Solid-State Circuits
Vol 30, pp.101-109, February 1995.
[82] J. Yuan and C. Svensson, “High-speed CMOS Circuit Technique,” IEEE J. of Solid-State
Circuits, Vol.24, no.l, pp. 62-70, January 1989.
[83] J. Yuan and C. Svensson, “New single-clock CMOS latches and flipflops with improved
speed and power savings,” IEEE J. of Solid-State Circuits, vol. 32, no. 1, pp. 62-67, January
1997.
[85] M.A. Margarit,D.Shih, P.J.Sullivan, and F. Ortega, “A 5-GHz BiCMOS RFIC Front-End
for IEEE 802.11a/HiperLANWireless LAN,” IEEE J. Solid-State Circuits Vol 38,pp. 1284-
1287, July 2003.
[86] F. Op’t Eynde, et al., “A Fully-Integrated Single-Chip SOC for Bluetooth,” ISSCC Digets
of Technical Papers, pp.196-197, Feb. 2001.
[87] B. Razavi, “CMOS Technology Characterization for Analog and RF Design,” IEEE J.
Solid-State Circuits, vol.34 pp.268-276, March 1999.
[88] “On-Wafer Vector Network Analyzer Calibration and Measurements,” Application Note,
Cascade Microtech, Inc.
[89] A. Aktas and M. Ismail, “Pad de-embedding in RF CMOS”, IEEE Circuits and Devices
Magazine, vol.17, pp. 8-11, May 2001.
[90] H. Cho and D.E. Burk,“ A Three-Step Method for the De-Embedding of High- Frequency
S-parameter Measurements”, IEEE Trans. on Electronic Devices, Vol. 38, No. 6, pp. 1371-
1375, June 1991.
[91] P. J. van Wijnen, et al, “A New Straightforward Calibration and Correction Procedure for
On wafer High Frequency S-parameter Measurements (45 MHz-18 GHz),” Bipolar Circuits
and Technology Meeting, pp. 70-73, 1987.
[92] Arthur Fraser, Reed Gleason, E. W. Strid, “GHz On-Silicon Wafer Probing Calibration
Methods” Bipolar Circuits and Technology Meeting, pp. 154-157, 1988.
[93] “Introduction to bipolar device GHz measurement techniques,” Application Note, Cascade
Microtech, Inc.
[94] “Layout Rules for GHz-Probing,” Application Note, Cascade Microtech, Inc.