ALEXANDER GROBMAN

Address: 6012 Roxbury Lane Austin TX, 78739

email: agb0c7a2@westpost.net
Phones: h: (512) 301-1154 | m: (512) 905-5050
Performance-driven ASIC SOC/IP Design/Verification Engineer with over 15 years o
f experience in the design, verification and validation of complex systems on ch
ip (SOCs) and international experience - lived and worked in three countries.
CORE COMPETENCIES:
* Digital IP Design
* Microprocessor Architecture
* VLSI Testing
* Post Silicon Validation
* Design Methodologies
* Configuration & Debugging
* SOC/IP/CPU verification
* System integration
* User Support
TECHNICAL BACKGROUND
Verilog, VCS, LEC, RTL compiler, Synopsis synthesis and timing static analysis t
ools, Perl, C, Pascal, PLM, UNIX C-shell, PowerPC, I8051/86 , microchip assemb
ler programming.

PROFESSIONAL EXPERIENCE
Freescale Semiconductor, Inc, Austin, TX 2001 - 2009
SOC/IP Senior Design Engineer
* Seventeen automotive flash based SOCs projects in 90/130 nm processes for powe
r train, communication gateways, breaking, advanced stability control and automo
tive radar applications.
. Designed:
- hardware modules (IPs), (e.g. RAM and ROM memory systems with
Hamming Error Correction Code (ECC) and FlexRay communication
controller bus interface unit),
- firmware - SOC boot code, using C and PowerPC assembler languages.
- SOC level verification and production patterns/environment. Used C,
assembler and complex Verilog/C patterns. Designed the C patterns
boot code and methods to compile, build and load these patterns into
microcontroller memories - flash, RAM or external memory models.
Used Perl scripts, GNU make and C compiler tools
-Took part in post silicon validation (including power consumption
characterization and analysis).
- Designed production patterns to cover test "holes", including for flash
modules.
. Total life time revenue from designed products is above $2 billion.
* ROM based ASIC cost reduction version of the flash based dual CPU microcontrol
ler.
Served as:
- ECC ROM memory system designer (RTL and verification).
- developed production flow for customer code to ROM mask, based on
internal tool and Perl scripts, with only one mask layer replacement
 instead of standard 2 layers updates for this technology, reducing
customer code maskset cost by 50%.
- SOC verification leader. The project was single revision success and
received the customer recognition reward. Updated M-core, C based
verification environment with more than 700 functional patterns to
support ROM instead of Flash, designed Make flow to build and load
ROM image into the SOC verilog model, updated many verification
patterns to work with the ROM, designed functional verification patterns
to test the ROM system. Several customer code masksets are running
now in full production mode.
* 1.5 M gates video accelerator IP for Advanced Driver Assistance System, featu
ring road signs recognition, lane departure warning, adaptive cruise control sup
port.
Designed two modules:
- The host and debug interface, serving as a control interface for
debugging and host interaction with four internal accelerator
microprocessors.
Executed design flow from creating design specification, RTL coding to
synthesis and verification. Created initial verification environment,
including verilog based testbench with drivers and monitors.
- The circle detector, designed to detect circular shapes in the video
frames.
Executed design flow from creating design specification, RTL
coding to synthesis and verification. Created initial verification
environment, including verilog based testbench with drivers and
monitors, Perl scripts to build test image patterns
Conducted peers modules RTL reviews, identifying code style improvements, code a
nd area size reductions up to 50%.

* Serial Peripheral Interface module IP - added several new features, fixing bug
s while maintaining backward compatibility with previous version. Executed full
design cycle in two months ahead of schedule with no support from previous IP ow
ner. Resurrected testbuilder based C++ verification environment, fixing monitors
, drivers and tasks to support new features. Creating regression scripts in Perl
to easy run more than 600 patterns.
Motorola Semiconductor Israel Ltd, Hertzliya, Israel 1994 - 2001
VLSI Design Engineer
* Served as an integral member of the international design team, designing, deve
loping and engineering MPC5XX family of the highly popular automotive single chi
p microcontrollers (with total revenue over $1 billion).
* Developed successful flow for migrating embedded Power PC core design over sev
eral process nodes. Enhanced the core with a new bus interface unit with real ti
me application code decompression feature, allowing up to 100% more application
code to be stored in the microcontroller internal flash. Registered several pat
ents on the subject.
* Led a team of 10 engineers in the functional test coverage enhancement of the
MPC5XX microcontrollers. Increased fault coverage from ~50% to more than 98%, re
ducing customer return rate to single digit PPM (parts per million). Developed o
ver 400 functional patterns, written with PowerPC assembler language. Maintained
and updated the embedded PowerPC core verification environment, including model
 build and patterns compilation Perl scripts, random pattern generation scripts,
designed verifault environment for the core patterns stuck at fault grading, in
cluding Perl based scripts to convert tester stimulus to verilog memory based te
ster model, extract detected faults lists, create new undetected fault lists, ru
n simulations, generate reports, visualize undetected faults, drawing schematics
with remains faults.
* Provided MPC5XX parts customer support, helping resolve application problems.
Ganot Industries Ltd, Netanya, Israel 1991 - 1994
Hardware/Software Design Engineer
* Designed and developed Remote Power meters data collection systems.
* Developed communication protocols for Power Line Carrier networks.
* Designed hardware and software for data collection and front-end units.
* Supported production of military equipment.
EDUCATION
Moscow Technical University of Electronics, Moscow, Russia
Master of Science in Electrical Engineering with specialization in microprocesso
r systems;
Moscow Technical University of Communications and Informatics Moscow, Russia
Master of Science in Electrical Engineering with specialization in Radio communi
cation and broadcasting; Magna cum laude;
Languages: English, Russian, Hebrew.