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  • Corrections To Fault Secure Encoder and Decoder For Nanomemory Applications

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    selvan_eee338
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    In the code under consideration is a (15,7,5) EG-LDPC code. We used this code as an example to concretely illustrate the concept of the fault secure encoder, decoder, and checker; and the implementation of these units. There are a few representation errors in Figures 5, and 6 of paper that we will correct in this document.

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    In the code under consideration is a (15,7,5) EG-LDPC code. We used this code as an example to concretely illustrate the concept of the fault secure encoder, decoder, and checker; and the implementation of these units. There are a few representation errors in Figures 5, and 6 of paper that we will correct in this document.

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    Descărcați ca PDF, TXT sau citiți online pe Scribd
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    16 vizualizări3 pagini

    Corrections To Fault Secure Encoder and Decoder For Nanomemory Applications

    Încărcat de

    selvan_eee338
    In the code under consideration is a (15,7,5) EG-LDPC code. We used this code as an example to concretely illustrate the concept of the fault secure encoder, decoder, and checker; and the implementation of these units. There are a few representation errors in Figures 5, and 6 of paper that we will correct in this document.

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    Descărcați ca PDF, TXT sau citiți online pe Scribd
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    din 3

    Corrections to

    Fault Secure Encoder and Decoder for


    NanoMemory Applications

    Helia Naeimi (helia.naeimi@intel.com)


    André DeHon (andre@acm.org)

    This document is prepared as an attachment to [1], and its purpose is


    to correct the error in the presentation of a code in that paper. In [1] the
    code under consideration is a (15,7,5) EG-LDPC code. We used this code as
    an example to concretely illustrate the concept of the fault secure encoder,
    decoder, and checker; and the implementation of these units. There are a few
    representation errors in Figures 5, and 6 of paper [1] that we will correct in
    this document. The (15,7,5) EG-LDPC code has the generator polynomial

    1 + x4 + x6 + x7 + x8 . (1)

    This generator polynomial will result in the generator matrix, shown in


    Figure A below. We perform linear row operations to make this cyclic non-
    systematic generator matrix into systematic form. We perform the following
    operations:

    i0 = i0 + i4 + i6 (2)
    i1 = i1 + i5
    i2 = i2 + i6 (3)

    This systematic form is presented in Figure B. This is the correct repre-


    sentation of this systematic format and should replace Figure 5 of [1]. Based
    on this new generator matrix the encoder structure shown in Figure 6 of [1]
    will also need to be changed to the new encoder shown in Figure C.

    1
    i6 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1

    i0 i2 i6 i0 i1 i3 i1 i2 i4 i2 i3 i5 i0 i2 i3 i4 i6 i0 i1 i3 i4 i5 i0 i1 i4 i5 i6 i0 i2 i6

    p0 p1 p2 p3 p4 p5 p6 p7

    7 Information Bits

    i0 i1 i2 i3 i4 i5 i6
    c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14

    i0 i1 i2 i3
    i
    i40 1i 0 0i 0 i01 i10i3 1 i1 1i2 1i4 0i2 0i3 0
    i5 i03 i40 i60 i0 i1 i3 i4 i5 i1 i2 i4 i5 i6 i0 i1 i2 i 5 i6 i0 i2 i6
    5 6
    i1 0 1 0 0 0 1 0 1 1 1 0 0 0 0 0
    i2 0 0 1 0 0 0 1 0 1 1 1 0 0 0 0
    i3 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0
    i4 0 0 0 0 1 0 0 0 1 0 1 1 1 0 0
    c0 c1 c2 c3 ci54 0c50 c6
    0 0 0 c17 0 0c8 0 1 0c9 1 1 c101 0 c11 c12 c13 c14
    i6 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1

    7 Information Bits 8 Parity Bits


    Figure A: The generator matrix of (15,7,5) EG-LDPC code in cyclic format

    c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14

    i0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1
    i1 0 1 0 0 0 0 0 1 1 0 0 1 1 1 0
    i2 0 0 1 0 0 0 0 0 1 1 0 0 1 1 1
    i3 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0
    i4 0 0 0 0 1 0 0 0 1 0 1 1 1 0 0
    i5 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0
    i6 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1

    Figure B: The generator matrix of (15,7,5) EG-LDPC code in systematic format

    7 Information Bits

    i0 i1 i2 i3 i4 i5 i6

    i0 i1 i2 i3 i4 i5 i6 i 0 i1 i3 i1 i2 i4 i 2 i3 i5 i 3 i4 i6 i0 i1 i3 i4 i5 i1 i2 i4 i5 i6 i0 i1 i2 i 5 i6 i0 i2 i6

    c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14

    7 Information Bits 8 Parity Bits

    Figure C: The systematic encoder circuit of (15,7,5) EG-LDPC code


    c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14

    i0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1
    i1 0 1 0 0 0 0 0 12 1 0 0 1 1 1 0
    i2 0 0 1 0 0 0 0 0 1 1 0 0 1 1 1
    i3 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0
    i4 0 0 0 0 1 0 0 0 1 0 1 1 1 0 0
    i5 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0
    i6 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1
    References
    [1] Helia Naeimi. Fault Secure Encoder and Decoder for NanoMemory Applications. IEEE
    Transaction on VLSI, 17(4):473–486, April 2009.

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