C Based

System Level Design

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Agenda

&System level design challenges

&SystemC - A modeling environment for
hardware and software
&CoCentricTM System Studio
&Conclusions
System Level Design
Challenges
 System Level Design in the
System-on-a-Chip World
< 0.25µ Geometries

Manage the Details

System
on a
Chip
Manage the Complexity
Higher Levels of SLD
Abstraction
Design Reuse
Millions of Gates
Higher Design Complexity
Requirements

&Specify, simulate and optimise systems

at higher levels of abstraction
– Performance
– Behavior
&Create new and reuse old IP
&Efficiently traverse the path to
hardware/software implementations
&Use a design environment that supports
your design flow
System Level Design Flow
Algorithm Product Architecture
Specification

Functional Architectural
Validation Validation

Algorithmic Co-Design Architectural

Models Models

Co-
Software Hardware
Verification
Performance Modeling

&Abstract performance models

– Enable trade-off estimations
– Examples: Modeling of power consumption,
delay

&Performance models with behavioral

functionality
– Scheduling of functions not fully specified
– Resource bindings not fully specified
Behavioral Modeling

&Untimed functional space

– Reactive control
– Dataflow

&Timed functional space

– Behavioral process
– RTL process
The Major Challenges in
System Level Design
How real
&Tight coupling of dataflow systems look ...
and control
&Reuse of IP at high control

abstraction levels dataflow

&Structured methods to control

communicate and handle

the system complexity
control

– Software
– Architecture
dataflow
SystemC -
A Modeling Environment for
Hardware and Software
SystemC -
A Modeling Environment for
Hardware and Software
&What is SystemC?
&Language overview
&System simulation in SystemC
&Example
&What is SystemC useful for?
SystemC -
A C++ Class Based Approach

Process 1
Process 3
sc_signal
sc_signed

Process 2
sc_ sc_logic
sig
na l
sc_sync sc_async
sc_aproc

&System description:
Multiple concurrent Processes
&Communication: Signals, clocks, reset
&Rich variety of hardware data types
&Model at all levels of abstraction
System Simulation
in SystemC

&SystemC consists of
– Set of header files describing the C++ classes
– Link library that contains a cycle-based
simulation kernel
&An ANSI C++ compliant compiler can
compile SystemC, together with your
program
&The resulting executable serves as a
simulator for the system described
Language Overview:
Modules and Processes

&Modules contain other modules or

processes
&Processes are used to describe
functionality
&Communication between processes
depends on signals, no global variables
&Processes can be reactive to any input
signal or to a clock signal
Process Types

&Synchronous processes
– Timing control statements like wait() implement
synchronization and writing
– Instructions between timing control statements
are executed without delay
&Asynchronous processes
– Instructions are executed without delay
– Local variables are redefined each time the block
is invoked
Various Levels of Abstraction

&The more details you have to SystemC -

System Level
simulate, the slower is the
simulation Algorithm
&Pure functionality of the
system, algorithm Behavioral
&Software and testbenches
can be described in C++ RTL
&Hardware implementation
– Behavioral, RTL style models
– Handshaking, clock, reset possible
Choosing the Right Data Type

&Atthe higher levels of abstraction, use

C++ native types
int, short, long, char, float, double, struct
&When you require hardware data types
for arithmetic operations, choose:
– sc_int, sc_uint: 1 to 64 bit integer type
– sc_bigint/sc_biguint: arbitrary sized signed
integer
– sc_bit/sc_bv: 2 value bit vector type
– sc_logic/sc_lv: 4 value logic vector type
Example: Counter 0 to 6
reset
data
Test_counter Counter

clock clock
main

&Processes are represented by two files

– Declaration in a header file
– Functionality in a C/C++ file
&A main program contains the main entry
point and instantiates the processes
Header File counter.h
SC_MODULE(Counter)
SC_MODULE(Counter) {{
//
// Inputs
Inputs class definition
sc_in<bool>
sc_in<bool> reset;
reset;
//
// Outputs
Outputs
sc_out<int>
sc_out<int> data;
data;
sc_in_clk
sc_in_clk CLK;
CLK;
//
// Constructor
Constructor constructor
SC_CTOR(Counter)
SC_CTOR(Counter) {{
SC_CTHREAD(entry,
SC_CTHREAD(entry, CLK.pos());
CLK.pos()); process definition
// Global watching for reset
// Global watching for reset
watching(reset.delayed()
watching(reset.delayed() ==== true);
true);
}}
//
// Process
Process functionality
functionality
void
void entry();
entry();
};
};
Functionality File counter.cpp
#include
#include <stdio.h>
<stdio.h>
#include
#include "systemc.h"
"systemc.h"
#include
#include "Counter.h"
"Counter.h"
void
void Counter::entry()
Counter::entry() {{ constructor
int count =
int count = 0;0;
//
// Reset
Reset behavior
behavior
if
if (reset.read()
(reset.read() == == true)
true) {{
count
count == 0;
0;
printf("RESET!
printf("RESET! Count
Count == %d\n",count);
%d\n",count);
wait();
wait(); timing control statements
}}
while
while (true)
(true) {{
printf("Count
printf("Count == %d\n",count);
%d\n",count);
count++;
count++;
if
if (count
(count >> 7)
7) {{ count
count == 0;
0; }} process functionality
data.write(count);
data.write(count); enclosed in an infinite loop
wait();
wait();
}}
}}
Main Program main.cpp
#include
#include "systemc.h"
"systemc.h"
#include
#include "Test_Counter.h"
"Test_Counter.h"
#include
#include "Counter.h"
"Counter.h"

int
int sc_main(int
sc_main(int argc,
argc, char
char *argv[])
*argv[]) {{
sc_signal<int>
sc_signal<int> data("DATA");
data("DATA");
sc_signal<bool>
sc_signal<bool> reset;
reset;
sc_clock
sc_clock clock("CLOCK",
clock("CLOCK", 100,
100, 0.5,
0.5, 0.0);
0.0);

Test_Counter
Test_Counter TestBench("TestBench");
TestBench("TestBench");
TestBench
TestBench <<
<< clock
clock <<
<< reset;
reset;

Counter
Counter DUT("ThreeBit");
DUT("ThreeBit");
DUT
DUT <<
<< reset
reset <<
<< data
data <<
<< clock;
clock; connections
sc_clock::start(-1);
sc_clock::start(-1);
return
return 0;
0;
}}
What is SystemC Useful For?

&Supporting methodology and tools to

verify a system
&Creating an executable specification
&Modeling hardware
– Algorithmic and behavioral
– RTL
&Modeling software
Obtain SystemC

&Source Code
&User Guide
&Reference Manual
&All available from www.SystemC.org
CoCentricTM System Studio
System Studio Overview

&Dataflow and control modelling

&Model management and System Studio
design center user interface
&Model implementation types
– Dataflow
– Control
&Examples
&Simulationin System Studio
&Design Reuse
System Studio Allows
Different Modeling Styles
to Interact
&Dataflow:
Block diagram
&Control, FSM:
States and transitions
C/C++
&C/C++ functions
&VHDL, Verilog
&SystemC processes
Combining Dataflow and
Control in System Studio

&You may embed a control model in a

hierarchical dataflow graph
&You may embed a dataflow model in a
hierarchical state of a control model
 Dataflow Modeling
&Dataflow graph: Network of
communicating processes
&Interconnects are
FIFO queues of data D
&Scheduling of
A B C
process activations
is constrained by data E
availability
– Data rates may vary
– No clock, no handshaking necessary
When do I Use Dataflow
Modeling?

&Wireless: Paging, cordless, cellular,

satellite, radar
&Image: Video processing,
image compression/coding
&Wireline: Voiceband data modems,
ADSL/HDSL modems, cable modems
&Consumer: Voice processing, speech
compression

DFG
When do I Need Control
Modeling?

&Data streams have finite length

&Configuration of the system can be
changed dynamically
&Parts of the system have to be
dynamically reset/re-initialised
&System comprises (reactive) control

FSM
Model Management

&Workspaces contain user libraries,

System Studio system libraries and
COSSAP system libraries
&Libraries contain models and libraries
&Models
– Created using the System Studio Design Center
– Model database file contains all information
related to a model
&Revision control systems for models and
libraries (e.g.: RCS, Clearcase)
System Studio Design Center
User Interface

Model Edit Area

Workspace
Browser

Message/Diagnostics Window
Model Implementation Types

&Primitive models
– prim_models
" Actions written in C/C++ style
" Allow to model static and dynamic dataflow and
control
– COSSAP SDS models
– Inline actions to control model states
in C/C++ style
&Hierarchical models
– Dataflow graph (DFG)
– States and transitions in control models
Model Interface

&Portsenable communication between

models
– FIFO queues in Dataflow models
(prim_models, SDS models, hierarchical DFGs)
– Signals belonging to parent models of control
models
&Parameters change the model behavior
– read-only
– constant, read-on-reset, dynamic
&Documentation
Data Types and
Type Parameters

&Data Types for Parameters, Ports,

Signals, Variables
bool, int, char, short, sub_range, float, double,
fixed, complex<T>, bit_vector, string
&Type Parameters <T> allow you to write
generic System Studio models
– Design structure does not change
– Use one generic models instead of a model for
each data type
 Example: prim_model
With Static I/O Pattern
prim_model
prim_model reverse
reverse {{
type_param
type_param TT == double;
double;
param
param int
int BSize
BSize == 4;
4;
Type is specified by
port
port in
in TT Inp;
Inp;
port
port out
out TT OutP;
OutP;
parameter

main_action
main_action {{
int
int j;
j; Inp T Outp
TT buffer[BSize];
buffer[BSize]; Reverse
for
for (j
(j == 0;
0; jj << BSize;
BSize; j++)
j++) {{ BlockSize
read
read (Inp);
(Inp);
buffer[j]
buffer[j] == Inp;
Inp;
}}
for
for (j
(j == Bsize-1;
Bsize-1; jj >=
>= 0;
0; j++)
j++) {{
Outp
I/O pattern
Outp == buffer[j];
buffer[j];
write
write (Outp);
(Outp); is static
}}
}}
 Example: prim_model
With Dynamic I/O Pattern
prim_model
prim_model select
select {{
type_param
type_param TT == double;
double;
port InTrue
port in
in TT InTrue,
InTrue, InFalse;
InFalse;
port
port out
out TT OutP;
OutP;
port
port in
in bool
bool control;
control;
Outp
main_action
main_action {{
read
read (control);
(control); InFalse
if
if (control)
(control) {{
read control
read (InTrue);
(InTrue);
Outp
Outp == InTrue;
InTrue;
}} else
else {{ Input pattern
read
read (InFalse);
(InFalse); is dynamic
Outp
Outp == InFalse;
InFalse;
}}
write
write (Outp);
(Outp);
}}
Control Model Types

&OR -- extended FSM

– Mutually exclusive states
– Model reset on entry
&GATED -- dynamic switching
– Gating condition controls
which page is executed
– State of suspended page is frozen
&AND -- concurrency
– Pages execute in parallel
– A page may contain a dataflow graph
or an OR model
OR Model -- Extended Finite
State Machine (E-FSM)

&Local variables can c1 / a1

Timelock
extend control Acquire
inside states c2 / a2

&Atomic states can have c3 / a3 Track

subset of C/C++ code

as inline actions
&Hierarchical states contain any kind of
System Studio models
&Actions can be executed in states and
transitions
Control Model Examples

&OR models embedded in a hierarchical

dataflow graph (DFG)

&Numerically controlled oscillator and

filter with controller in 2-Page AND Model

&Dynamic system configuration

OR Model Embedded in a
Hierarchical DFG

&Bit-serialsignals of ASCII text and image

are multiplexed into a TDMA signal,
modulated, and transmitted
600 bits 24 bits 96 bits

Training sequence 1 Text 0 Image 0 Image 0

0 time
(1 text frame, 20 image frames, 1 text frame, ...)

&Receiver:
– Mixed image-text-TDMA signal is filtered and
equalised using a Least Mean Square algorithm
– Equalised signal is demodulated and decoded
Receiver Front-end

&Reference is used to update equalizer

&Switching of a Training Sequence tunes
the equalizer in the beginning

Input Matched
Filter
To
Adaptive demodulator

Equalizer
Equal Training
Sequence Reference
Model: Training Sequence
Training sequence
0 time

Dataflow models
Reference

Equal
OR models
 OR Model: mux_trainingseq

S1 S2 S3 S2 S3 S2 S3
Training sequence
0 delay high low time

S1 S2 S3

Output port 1st Input port Local variable Parameters 2nd Input port
Example: NCO and Filter With
Controller in 2-Page AND Model
Inline Signals
Code

Input
ports
 Example: Dynamic System
Configuration
/* Function of the
parent OR model */ Parent OR

if( par == “S1” ) par == “S1” par ==“S2”

execute DFG;
else S1 S2
execute prim_model;

prim_model
prim_model reverse
reverse {{
type_param
type_param TT == double;
double;
param
param int
int BSize
BSize == 4;
4;
port in T Inp;
port in T Inp;
port out T OutP;
port out T OutP;

main_action
main_action {{
int
int j;
j;
TT buffer[BSize];
DFG for
buffer[BSize];
for (j == 0;
(j
read
0; jj << BSize;
read (Inp);
(Inp);
BSize; j++)
j++) {{

buffer[j]
buffer[j] == Inp;
Inp;
}}
for
for (j = Bsize-1; j >=
(j = Bsize-1; j >= 0;
0; j++)
j++) {{
Outp
Outp == buffer[j];
buffer[j];
write
write (Outp);
(Outp);
}}

prim_model }}
Simulation in System Studio

&Code analysis and scheduling

&C/C++ code generation and compilation
&Simulation execution
Code Analysis and
Scheduling
Black
Black box
box
&prim_model code is int
int foo(int
foo(int x,
x, int
int y);
y);
parsed and translated Transparent
Transparent box
box
– Transparent model:
int
int foo(int
foo(int x,
x, int
int y)
y)
Static dataflow scheduling; {{
if not possible turn into a if
if (x)
(x)
return
return 2*
2* y;
y;
dynamic SDS model else
else
return
return 0;
0;
– C/C++ code generation }}

– Generated C/C++ code is

different from prim_model code
Code Analysis and
Scheduling (continued)

&Control models
– Translated into an Esterel equivalent and then
into sequential C/C++
– Static scheduling domain

&SDS models
– Black box, implementation is already available in
C or Fortran code
– Dynamic scheduling domain
Static vs. Dynamic
Scheduling

&Static scheduling at compile time allows

fast simulation, when you use
– prim_models with static behavior
– Control models

&Scheduling at run time cannot be

avoided, when you use
– prim_models with dynamic behavior
– COSSAP SDS models
C/C++ code Generation
and Compilation

&Code generation for static scheduling

domains is optimised for
– Dead code elimination
– Minimal memory consumption
– High simulation speed

&Compilation
Simulation

&Simulation executable can be started

– Out of the System Studio Design Center
– Command line interface
– Simulation executable is slavable,
can be invoked out of other simulators,
e.g. SystemC, VCS and SDL
&StreamDriven SimulatorTM is a key
component of System Studio
– Run time scheduling
– Simulation of COSSAP SDS models
 Simulation Control File

&TCL/TK Syntax

&Example: set
set ref_value
ref_value "1.0e-06”
"1.0e-06”

for
for {set
{set ii 2}
2} {$i
{$i <=
<= 32}
32} {incr
{incr ii 1}
1} {{
set_parameter
set_parameter wl_data
wl_data $i
$i
Define limit
run_iteration
run_iteration

Loop simulation set

set Id_r
Id_r [open
[open file.am
file.am r]
r]
set
set value
value [gets
[gets $Id_r]
$Id_r]
parameter close
close $Id_r
$Id_r

if
if {{ [expr
[expr $value
$value << $ref_value]
$ref_value] }} {{
exit
exit
Read file.am }}
that was just created }}
Design Reuse: Import from
COSSAP into System Studio

&COSSAP libraries to
System Studio libraries
&Schematics and
hierarchical models to
System Studio DFGs
&Assignment files to
simulation control files
&COSSAP models can be
easily edited and maintained
in System Studio
Design Reuse: Importing
HDL and SystemC Models

&Import of VHDL/Verilog models

– Behavioral and RTL
– Co-simulation using HDL simulators

&Import of SystemC models

– Timed and untimed
– Co-simulation using
SystemC simulation executable
C Based System Level Design
using System Studio

&Design environment supports

– Modeling of dataflow and control
– Creating, managing, sharing and reusing
system-level IP
&Richset of new data types and type
parameters
&Backward Compatibility
– Migration from COSSAP to System Studio
– Co-simulation with HDL and SystemC models
Conclusion
Benefits of C Based System
Level Design

&C/C++ are the dominant languages used

by chip architects, software engineers,
and system engineers
– SystemC:
Hardware and software modeling constructs
using C++ class libraries
– CoCentricTM System Studio:
C/C++ code generation and code optimization
&Simulation of C/C++ code allows for
faster design capture, architecture and
algorithm exploration and analysis
Consistent Flow with
System Studio and SystemC

&System Studio simulation executables

are slavable in a SystemC simulation

&SystemC processes can be imported into

System Studio and co-simulated
Environments for
C Based System Level Design

&SystemC
– Model hardware and software using C++ classes
and a simulation kernel
– Create, validate and share models
&CoCentricTM System Studio
– Handle complex systems using a graphical user
interface
– Combine dataflow and control in the same
environment