TABLE OF CONTENTS TOPICS 1. 2. 3. 4. Page No.

Introduction.........................................................................................................2 VHDL function for a divider...............................................................................2 Shift and Subtract Division implementation (Behavioral)..................................2 Shift and Subtract Division implementation (Structural)................................... 3 i. Data Path........................................................................................................3 ii. Controller....................................................................................................... 4 iii. Integration of Data Path and Controller.........................................................5 5. Testbenches......................................................................................................... 6 6. Synthesis of various models and components.....................................................6 7. References...........................................................................................................6

1. Introduction
This report aims to address the short project implementation as part of the VHDL course. A shift and subtract divider was implemented as the project task and synthesized using both behavioral and structural models. The correctness of the final design was checked using testbenches with all possible input stimuli combinations. The Divider takes Unsigned vectors as inputs and returns Quotient and Remainder of the same type. It is assumed that the dividend vector length 'm' is more than that of the divisor.

2. VHDL Function for a Divider

A simple function was implemented in VHDL which calculated the quotient and remainder without using any division, multiplication or shifting operations. This is achieved using subtraction of the divisor from the dividend recursively until the dividend becomes lesser than the divisor.

3. Shift and Subtract Division implementation (Behavioral)

The shift and subtract division is implemented using the following algorithm : (m : Dividend's length; n : Divisor's length. M > N. Both dividend and divisor have no leading zeros.) 1 . Start 2 . Quotient = 0, Reminder = Dividend (Initialization) 3 . Shift Divisor (m-n times) by appending zeros at the end (Initialization) 4 . for m-n+1 number of times repeat till step 8 5 . if reminder is greater than or equal to Divisor then do step 6 and step 7 else goto step 8 6 . reminder = reminder Divisor 7 . Quotient = (Quotient *2) + 1 8 . Quotient = (Quotient *2) 9 . Divisor = Divisor / 2 10 . end

4. Shift and Subtract Division implementation (Structural)

The structural model for the shift and subtract division was implemented in two sections. First the above mentioned algorithm was analyzed and broken into steps and hence deduced a corresponding data flow. With reference to the deduced data flow diagram, a data path circuit was designed. The data path is controlled by a separate controller. The implementation of the controller was done as a Finite State Machine. i. Data Path To design the data path, the algorithm was reduced to a set of small steps. And correspondingly a data flow diagram was produced. The data flow diagram is shown as below :

In total, 4 cycles are used in one loop operation of the divider. The data flow diagram shows 5 cycles, but 2 of them (cycle 4 and 5) are mutually exclusive and only one of them would be executed in any given loop. The variable n1 holds the count of the loops which is to be done m-n+1 times. ii. Controller The controller obviously is a finite state machine. The number of states in this design is 5. The number of states can also be reduced increasing the parallelism, but at a cost of extra hardware components. The present design uses 1 comparator, 1 bit shifter, 1 adder and 1 subtracter. These components are controlled by various control signals. Also the operands for these components are chosen using selection signals to multiplexers. Similarly, the output results are stored in various registers depending on which register is enabled. All these decisions of enable/disable, selection etc are taken care by the controller. The controller also outputs a signal 'BUSY' when the divider is calculating and not available to process other inputs. The state transition diagram of the controller is as shown below :

A layout of the data path circuit designed is given below.

iii. Integration of Data Path and Controller Finally, the data path and the controller were integrated into a single circuit resulting the complete and fully functional divider. The divider as an entity, takes input A and B as unsigned vectors and outputs Q and R of the same type. This is a synchronous circuit and hence takes a clock input, and a reset input as well. Apart from that, the circuit is having an enable pin, which when given a high input makes the circuit active. 5

5. Testbenches
The correctness of a circuit can only be ensured after testing the circuit with all possible input values. Therefore testbenches were written in this project too, which when run, stimulates the divider circuit with all possible input values, and checks the output results with the expected values.

6. Synthesis of various models and components

The various models thus designed, including the structural divider, individual components such as controller and data path were synthesized using the Synopsys tool. The designs were Analyzed and Elaborated for any errors and then compiled for a optimized output. The synthesizer generates a flat netlist by un-grouping the hierarchies and bringing down the circuit to the primitives. The abstract behavior of the circuit is thus converted to a gate level design implementation. The synthesizer uses recursive algorithms to flatten the hierarchies. Its a sequential process. The hierarchy information is captured in the netlist itself. To simulate from the flat netlist, it needs to be compiled first which produces a single library. That can be simulated and will have no functional difference from the original structural model.

7. References
1. http://en.wikipedia.org/wiki/Netlist 2. http://www.vhdl-online.de/