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VARAN INTERFACE MODULE

CIV 521

C-DIAS Control Module


The C-DIAS CIV 521 module expands the VARAN bus network with numerous standard interface connections. In addition to the integrated VARAN splitter that allows the configuration of linear structures, the module is equipped with a standard Ethernet interface. The Ethernet interface can be used for servicing purposes or integration into office networks. The main function, however, is to integrate conventional bus systems into the flexible VARAN bus network. The module has a CAN bus, RS232, RS422/485 as well as a DIAS, C-DIAS and TTY interface.

CIV 521

Technical Data
Performance data
Interface connections 2 x VARAN-Bus (with distributor function) 1 x Ethernet bus 1 x RS232 1 x RS422/RS485 1 x TTY current interface (20 mA) 1 x C-DIAS bus (under side) 1 x DIAS bus 1 x CAN bus

Electrical requirements
Supply voltage Current consumption of voltage supply Current capacity on C-DIAS bus (power supply for I/O modules). Power consumption 18 30 V DC The current consumption is dependent on the connected loads (max. 1.4 A) Maximum 1.2 A >2.4 W

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CIV 521 Miscellaneous


Article number

VARAN INTERFACE MODULE

12-003-521 1.x UL in preparation

Hardware version Standardization

Environmental conditions
Storage temperature Operating temperature Humidity EMV resistance Shock resistance Protection -20 70C 0 50C 0 95 %, uncondensed According to EN 61000-6-2 (industrial area) EN 60068-2-27 EN 60529 150 m/s IP 20

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VARAN INTERFACE MODULE

CIV 521

Mechanical Dimensions

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CIV 521

VARAN INTERFACE MODULE

Connector Layout

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VARAN INTERFACE MODULE X1: Ethernet

CIV 521

Pin 1 2 3 4-5 6 7-8

Assignment Tx+ TxRx+ Rx-

X2: VARAN-IN X3: VARAN-OUT

Pin 1 2 3 4-5 6 7-8

Assignment TX/RX+ TX/ RXRX/TX+ RX /TX-

X4: DIAS

12
Pin 1 2 3 4 5 6 Assignment MBUS+ MBUSSBUS+ SBUSGND -

56

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CIV 521 X5: RS485/422

VARAN INTERFACE MODULE

1 2
Pin 1 2 3 4 5 6 7 8 9 10 Function RS422 RS422 TxD+ RS422 TxDRS422 RxD+ RS422 RxDGND RS422 TxD+ RS422 TxDRS422 RxD+ RS422 RxDFunction RS485 RS485 A RS485 B GND RS485 A RS485 B -

9 10
X6: RS232

12
Pin 1 2 3 4 5 6 Assignment RxD RTS TxD CTS DTR GND

56
X7: TTY (20 mA)

12
Pin 1 2 3 4 5 6 Assignment Tx+ TxRx+ Rx20 mA GND

56

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VARAN INTERFACE MODULE X8: CAN-BUS

CIV 521

12
Pin 1 2 3 4 5 6 Assignment CAN A (LOW) CAN B (HIGH) CAN A (LOW) CAN B (HIGH) GND +5 V / 500 mA

56
X9: Power plug

Pin 1 2

Assignment +24 V supply GND

Applicable connectors
X1 X3: X5: X4, X6 X8: X9: 3,5 8-pin. RJ45 10-pin. Weidmller connector B2L3, 5/10 6-pin. Weidmller connector B2L3, 5/6 2-pin. Phoenix connector with screw terminal technology MC1, 5/2-ST2-pin. Phoenix connector with spring terminals FK-MCP1, 5/2-ST-3,5

The complete C-DIAS CKL 022 connector set with spring terminals is available from SIGMATEK under the article number 12-600-022.

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CIV 521

VARAN INTERFACE MODULE

Wiring Guidelines for the RS232


General data /specifications For RS232 connections, shielded data cables must be used! Maximum bus participants: 2 stations Maximum length: 15 m

Wiring Guidelines for the RS422


General data /specifications For wiring data cables, twisted pair cables with shielding must be used! Maximum bus participants: 1 master, 10 Slaves Maximum length: 500 m (ISO Norm 8482) Sender/Receiver IC: MAX1486

Terminating the CIV

100

Wiring

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VARAN INTERFACE MODULE

CIV 521

Wiring Guidelines for the RS485


General data /specifications For wiring data cables, twisted pair cables with shielding must be used! Maximum bus participants: 32 stations Maximum length: 500 m (ISO Norm 8482) Sender/Receiver IC: MAX1486

Terminating the CIV

100

Wiring Because the RS485 requires a defined quiescent point, a pull-up and pull-down resistor is required in addition to the termination resistor.

The 5 V supply shown in the diagram above is generated externally.

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CIV 521

VARAN INTERFACE MODULE

Wiring Guidelines for the TTY


General data /specifications For wiring data cables, twisted pair cables with shielding must be used! Maximum bus participants: 2 stations Maximum length: 300 m Sender / receiver IC Optic coupler

Wiring and configuration (X3/X4) ACTIVE PASSIVE

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VARAN INTERFACE MODULE

CIV 521

CAN Bus Termination


In a CAN bus system, both end modules must be terminated. This is required to avoid data transfer errors that are caused by reflections in the data lines.

Device 1
e.g. CPU DCP 080 CAN-Bustermination on terminal module

Device 2
e.g. Terminal ET 081

Device 3

Device n
e.g. Terminal ET 805 D-SUB-plug with terminating resistors

CAN-Bus-Connections

If the CIV 521 is an end module, it can be terminated by placing a 150-Ohm resistor between CAN-A (Low) and CAN-B (High).

1 x 150R resistor

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CIV 521

VARAN INTERFACE MODULE

DIAS Bus Termination


In a DIAS bus system, both end modules must be terminated. This is required to avoid data transfer errors that are caused by reflections in the data lines. The DIAS bus termination is integrated in the CIV 521 and must no longer be built into the connector.

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VARAN INTERFACE MODULE

CIV 521

The DIAS Bus Connection


To ensure a good bus connection, several wiring guidelines must be followed: It is important to ensure the cables used are designed for the data transfer speed. Data cables (10Mbit, 2 x 2 wire TWISTED PAIR, shielded) i.e.: LAPPKABEL / UNITRONIC-BUSLEITUNG FD P LD Due to the internal resistance of the module, the cable impedance should be 100 Ohms. For twisted-pair cables, caution must be taken to ensure that the correct pair are connected with one another: 2x2 pair cables: Pair 1 MBUS+ MBUSPair 2 SBUS+ SBUSThe shielding must be connected to GND over the widest surface and shortest route possible at both ends To connect the individual wires to the connector, the insulation must be removed and the exposed shielding shifted to the side. Only as much insulation as required should be removed. It is important to ensure that the send and receive modules are connected to the same GND potential.

The maximum length allowed for twisted-pair cables per DIAS bus connector is 20 M (when using the UNITRONIC BUS-Leitung FD P LD / Fa. LAPPKABEL)

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CIV 521

VARAN INTERFACE MODULE

Example
Isulation

i.e.: C-IPC

2 x2 wire twisted pair cable

The distance between a and b should be as small as possible! Shift the shielding and connect it to GND over the shortest route and largest area

The CIV 521 can also be connected to a DIAS module. However, the DIAS modules require a power supply (a DPS 001, for example) as well as an adapter module for connect the twisted-pair cable to the ribbon cable connector (i.e.: DKO 012 /013).

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VARAN INTERFACE MODULE

CIV 521

Status Display

LED number AC line ET VI VO LI Row ET VI VO TX Row C1 C2 C3 CA RX Line C1 C2 C3 CA Status Roy DC R SY DA

LED color Yellow Yellow Yellow Green Green Green Yellow Yellow Yellow Yellow Green Green Green Green Green RED Green Yellow

Definition

Description

Ethernet Active VARAN IN Active VARAN OUT Active Ethernet Link VARAN IN Link VARAN OUT Link RS485/422 Transmit RS232 Transmit TTY Transmit CAN Transmit RS485/422 Receive RS232 Receive TTY Receive CAN Receive DCOK RESET PLL-Sync DIAS Active

Lights when data is sent or received. Lights when data is received over the VARAN bus Lights when data is sent over the VARAN bus Lights when the connection between the two PHYs is established Lights when the connection between the two PHYs is established Lights when the connection between the two PHYs is established Lights when data is sent. Lights when data is sent. Lights when data is sent. Lights when data is sent. Lights when data is received. Lights when data is received. Lights when data is received. Lights when data is received. Lights when the 24 V and 5 V supply is present Lights when the module is in Reset. Lights when the VARAN PLL is locked. Lights when data is sent or received over the DIAS bus.

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CIV 521

VARAN INTERFACE MODULE

Applicable Modules
C-DIAS All C-DIAS module groups are supported, however, using the interrupt function is not possible.

Exception: The following communication modules are not supported, since here, the interrupt function is required. CSI 021 CSI 023 CSI 025 CCA 021 / TCCA 021 CBC 021 CSE 011

DIAS The CIV 521 allows the connection of DIAS modules. No interrupt function is supported however, as it would limit the function. Modules that require the interrupt (e.g. communication modules) cannot be used.

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VARAN INTERFACE MODULE

CIV 521

Wishbone Data Mover


The "wb_mover" element shifts data between different Wishbone devices. The source and destination device is defined in the program code that should be loaded in the "mover RAM".

Types of Access There are various types of access with different priorities in the "Data Mover". The "alive" access (DIAS watchdog) is an additional access type used to prevent a DIAS reset when the DIAS bus is inactive and has the highest priority. With each Watchdog trigger and Sync signal, the DIAS alive message is sent over the DIAS bus. The lowest priority has the admin access. It starts when the admin list enable bit is set and no other accesses are active. The admin access enable bit is cleared at the end of the list. The fast access is assigned the next lower priority and extra control register at the end of the register block. This access type supports only two instructions: fast read and fast write. The synchronous access has the next lower priority. This access starts when the synchronous list enable bit is set and the sync tick is triggered. After accessing, the enable bit is not cleared. Each sync is therefore started when the enable bit is set. The asynchronous access has the lowest priority. Access is triggered when the asynchronous list enable bit is set. At the end of the list, the asynchronous enable bit is cleared. The fast and alive access types immediately interrupt all other lists. The active instruction is interrupted and continued after the fast/alive access is completed. To avoid high or low byte errors, the Word access is not interrupted. Synchronous access interrupts asynchronous access at the end of each instruction.

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CIV 521

VARAN INTERFACE MODULE

The Direct, synchronous and asynchronous access types have list counters that display the time the list was executed. Overflow counters are available, which calculate the duration of the list through the software. The synchronous access has a time register, which defines the maximum time for processing the synchronous lists. A time slice error occurs when this maximum value is exceeded.

Time diagram

Admin Task Asynchronous Task Isochronous Task

Fast Access

Dias Alive

Tn+1

Tn+2

Instructions The main instructions are move, move_en, delay and end. The fast read and fast write instructions are used with fast access only.
Instruction Move move_en Delay End fast_read fast_write Value (Hex) x1 x2 x3 x0 x4 x5 Instruction length (bytes) 12 16 4 4 1 1 Description Shifts the number of bytes from the source address to the destination address. Similar to the Move instruction. The execution of this instruction defines an enable byte in the data RAM. The Data Mover is waiting for the defined time. End of list "fast read" instruction "fast write" instruction

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VARAN INTERFACE MODULE The "Move" Instruction

CIV 521

The move instruction copies various amounts of data from a source address to a destination address. The number of data bytes is determined by the byte counter. The complete move instruction is 12 bytes long.
Command section Instruction Byte counter Source address Destination address Length 1-byte 3 bytes 4 bytes 4 bytes

The instruction byte A lower nibble of the instruction byte consists of the actual instruction. The upper nibble is the access type for the source and destination devices. Access types are either control or memory in the VARAN address space.
7 6 Access type, source address 00 : MEM ACCESS 01 : CNTRL ACCESS 5 4 ACCESS TYPE, DESTINATION ADDRESS 00 : MEM ACCESS 01 : CNTRL ACCESS 3 Instruction 2 1 0

For example, x31 means: shift data from the memory address area to the control address area. Byte counter The byte counter defines the number of data bytes to shift. Source address The source address is the address of the Wishbone module from which the data bytes are read. Destination address The destination address is the address of the Wishbone module to which the data bytes are written.

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CIV 521

VARAN INTERFACE MODULE

The "Move Enable" instruction The "move_en instruction is similar to the "move" instruction, except that the Mover checks the address in the data DPRAM (identified with the enable byte address) to see if the instruction should be executed or not (is active). The complete move instruction is 16 bytes long.
Command section Instruction Byte counter Source address Destination address Enable byte address Length 1 byte 3 bytes 4 bytes 4 bytes 4 bytes

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VARAN INTERFACE MODULE Enable byte address The data stored in the enable byte address have the following functions:
Data Bit 0 = 1 Bit 1 = 1 Other Function The move instruction is executed each time a list is called (continuous process). The move instruction is executed and the enable byte is set to null. The move enable bit must be set when the next list is processed (one-time process). The move instruction is not executed.

CIV 521

Continuous processes have a higher priority than one-time processes. If both enable bits re set, the continuous process is executed.

The Delay instruction The delay instruction stops the code list from being run for the period of time defined in the delay time register.
Command section Instruction Delay time Length 1 byte 3 bytes

Instruction A lower nibble of the instruction byte is the actual instruction; the upper nibble is reserved Delay time Delay time in s. The End instruction. The end instruction stops the code list execution.
Command section Instruction Reserved Length 1 byte 3 bytes

A lower nibble of the instruction byte is the actual instruction; the upper nibble is reserved

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CIV 521

VARAN INTERFACE MODULE

The "Fast Write" instruction The fast_write instruction copies the bytes from the code DPRAM to the module. The number of bytes is defined by the fast access byte-count register.
Command section Instruction Length 1 byte

To write data using fast access: 1. Set the destination address in the fast access data register. 2. Set the write instruction, fast access enable bit and access type in the fast access control register. 3. Sets the number of bytes to send in the fast access count register. 4. Writes data to the code DPRAM. 1+2+3+4 = 1 VARAN data object If the last data byte has been written to the code DPRAM, the Mover starts the fast access. The "Fast read" instruction At fast_read command the mover reads the bytes from device (pointed with Fast Access Data Address) and puts it to the Code DP RAM. When fast access is complete, the data can be read out from Code DPRAM.
Command section Instruction Length 1 byte

To read data with fast access: 1. Set the source address in the fast access data register 2. Set the Read instruction, fast access enable bit and access type in the fast access control register. 3. Set number of bytes to send in Fast Access Byte Counter Register 1+2+3 = 1 VARAN data object As soon as all data bytes are written to the fast access byte counter, the Mover starts the fast access. When fast access is complete, the read data are stored in Code DPRAM, fast access enable bit and fast access active bit are cleared. The data could be read out now with Varan access on Code DPRAM.

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VARAN INTERFACE MODULE Status/Error Administration

CIV 521

Status/error administration defines the signals used by the "wb_mover" to show the actual response. Error administration can be set through the software; the default values are set with generic. The signals employed are as follows:
Bits 7 Hold on time slice error 6 hold on wishbone eror 5 hold on OP-Code error 4 DIAS Alive access enable 3 Asynchronous access enable 2 Admin access enable 1 Synchronous access enable 0 Mover enable

Bit 0: 0 = disable Data Mover 1 = enable Data Mover Bit 1: 0 = disable Synchronous List 1 = enable Synchronous List Bit 2: 0 = disable admin access 1 = enable admin access, admin access is running Bit 3: 0 = disable asynchronous access 1 = enable asynchronous access, asynchronous access is running Bit 4: 0 = disable dias alive access 1 = enable dias alive access Bit 5: 0 = no error 1 = data mover stop after detecting OP-Code error Bit 6: 0 = no error 1 = data mover stop after detecting Wishbone error Bit 7: 0 = no error 1 = data mover stop after detecting Time Slice error

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CIV 521

VARAN INTERFACE MODULE

Status Register
Bits 7 reserved 6 reserved 5 reserved 4 Fast access active 3 Asynchronous access active 2 Admin access active 1 Synchronous access active 0 Mover active

Bit 0: 0 = mover is not active 1 = mover is active, any access is running at the moment Bit 1 0 = synchronous access is not running 1 = synchronous access is running at the moment Bit 2: 0 = admin access is not running 1 = admin access is running at the moment Bit 3: 0 = asynchronous access is not running 1 = asynchronous access is running at the moment Bit 4: 0 = fast access is not running 1 = fast access is running at the moment Bit 5: 0 = admin access is running/not active 1 = admin access is done Task Status
enable task DIAS alive DIAS alive access enable = 1 Fast Access fast access enable = 1 Fast Access active = 0 Admin access admin access enable = 1 Fast Access enable = 1 Fast Access active = 1/0 Admin access enable = 1 Admin access active = 1/0 Admin access done = 0 Synchronous access Synchronous access enable = 1 Synchronous access active = 0 Synchronous access enable = 1 Synchronous access active = 1/0 Fast Access active = 0 Admin access enable = 0 Admin access active = 0 Admin access done = 0 Synchronous access enable = 1 Synchronous access active = 0 (task is not running, complete or paused) Synchronous access enable = 0 Admin access enable = 0 Fast Access enable = 0 task is running task complete disable task DIAS alive access enable = 0 Fast Access enable = 0

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VARAN INTERFACE MODULE


asynchronous access Asynchronous access enable = 1 Asynchronous access active = 0 Asynchronous access enable = 1 Asynchronous access active = 1/0 Asynchronous access enable = 0 Asynchronous access active = 0

CIV 521

Asynchronous access enable = 0

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CIV 521 Error register

VARAN INTERFACE MODULE

Bits 7 reserved 6 reserved 5 Time slice error 4 Wishbone Bus error 3 2 1 OP-Code error error in fast access error in admin access error in asynchronous access error in synchronous access 0

Bit 0 -3: wrong command in a list or end of the list is reached and no end command exists Bit 0: 0 = no error 1 = error in synchronous acces Bit 1: 0 = no error 1 = error in asynchronous access Bit 2: 0 = no error 1 = error in admin access Bit 3: 0 = no error 1 = error in fast access Bit 4: 0 = no error 1 = error in wishbone bus (wrong address or too large address in sub bus) Bit 5: 0 = no error 1 = time in synchronous list time register is reached or execution time of the list is greater than the cycle time (sync occurs during list is active).

If an error occurs and the "hold on error bit" is set, the Mover stops the state machine and sets an relevant error bit in the error register. The further commands are not executed. The mover and all lists are disabled. If an error occurs and the "hold on error bit" is set, the Mover cancels the actual list execution, sets an relevant error bit in the error register and continues with the next operation list.

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VARAN INTERFACE MODULE

CIV 521

Addressing
Address (hex) Memory UART Interface Handler 1 (TTY) Modem Control Register Bit 0: Data Terminal Ready Bit 1: Request to Send Bit 2: Mode/de: 0 = RS 232 mode, 1 = Data enable RS 422/485 Bit 3: Mode: 0 = RS422, 1 = RS485 Bit 4: Loop Bit 5: Echo 1 = disable Bit 6 .. 7: Reserved Line Control Register Bit 0 .. 1: Word Length Select Bit 2: Number of Stop Bits Bit 3: Parity Enable Bit 4: Even Parity Select Bit 5: Stick Parity Bit 6: Set Break Bit 7: Reserved Divisor Latch Register Set the Baud rate (for more information see UART description) Bytes to Send Counter reserved Transmit Buffer reserved Modem Status Register Bit 0: Delta Clear to Send Bit 1: Delta Data Set Ready Bit 2: Trailing Edge Ring Indicator Bit 3: Delta Data Carrier Detect Bit 4: Clear to Send Bit 5: Data Set Ready Bit 6: Ring Indicator Bit 7: Data Carrier Detect Line Status Register Bit 0: Transmitter Holding Register Empty Bit 1: Parity Error Bit 2: Framing Error Bit 3: Break Control Bit Bit 4: Busy Bit 5 : Receive Buffer Overflow Bit 7 6: reserved Size (Byte) Access Type: Description Reset value

0000

0001

0002 0004 0005 0006 007E

2 1 1 120 2

w w r w

0080

0081

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CIV 521

VARAN INTERFACE MODULE


Modem Control Register Bit 0: Data Terminal Ready Bit 1: Request to Send Bit 2: Mode/de: 0 = RS 232 mode, 1 = Data enable RS 422/485 Bit 3: Mode: 0 = RS422, 1 = RS485 Bit 4: Loop Bit 5: Echo 1 = disable Bit 6 .. 7: Reserved Line Control Register Bit 0 .. 1: Word Length Select Bit 2: Number of Stop Bits Bit 3: Parity Enable Bit 4: Even Parity Select Bit 5: Stick Parity Bit 6: Set Break Bit 7: Reserved Receive Byte Counter Receive Buffer Reserved

0082

0083

00

0084 0086 00FE

1 120 2

r r r

00 00 00

UART Interface Handler 2 (RS 232) Modem Control Register Bit 0: Data Terminal Ready Bit 1: Request to Send Bit 2: Mode/de: 0 = RS 232 mode, 1 = Data enable RS 422/485 Bit 3: Mode: 0 = RS422, 1 = RS485 Bit 4: Loop Bit 5: Echo 1 = disable Bit 6 .. 7: Reserved Line Control Register Bit 0 .. 1: Word Length Select Bit 2: Number of Stop Bits Bit 3: Parity Enable Bit 4: Even Parity Select Bit 5: Stick Parity Bit 6: Set Break Bit 7: Reserved Divisor Latch Register Set the Baud rate Bytes to Send Counter reserved Transmit Buffer reserved -

0100

0101

0102 0104 0105 0106 017E

2 1 1 120 2

w w r w

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VARAN INTERFACE MODULE


Modem Status Register Bit 0: Delta Clear to Send Bit 1: Delta Data Set Ready Bit 2: Trailing Edge Ring Indicator Bit 3: Delta Data Carrier Detect Bit 4: Clear to Send Bit 5: Data Set Ready Bit 6: Ring Indicator Bit 7: Data Carrier Detect Line Status Register Bit 0: Transmitter Holding Register Empty Bit 1: Parity Error Bit 2: Framing Error Bit 3: Break Control Bit Bit 4: Busy Bit 5 : Receive Buffer Overflow Bit 7 6: reserved Modem Control Register Bit 0: Data Terminal Ready Bit 1: Request to Send Bit 2: Mode/de: 0 = RS 232 mode, 1 = Data enable RS 422/485 Bit 3: Mode: 0 = RS422, 1 = RS485 Bit 4: Loop Bit 5: Echo 1 = disable Bit 6 .. 7: Reserved Line Control Register Bit 0 .. 1: Word Length Select Bit 2: Number of Stop Bits Bit 3: Parity Enable Bit 4: Even Parity Select Bit 5: Stick Parity Bit 6: Set Break Bit 7: Reserved Receive Byte Counter Receive Buffer Reserved

CIV 521

0180

0181

0182

0183

00

0184 0186 01FE

1 120 2

r r r

00 00 00

UART Interface Handler 3 (RS 485/422) Modem Control Register Bit 0: Data Terminal Ready Bit 1: Request to Send Bit 2: Mode/de: 0 = RS 232 mode, 1 = Data enable RS 422/485 Bit 3: Mode: 0 = RS422, 1 = RS485 Bit 4: Loop Bit 5: Echo 1 = disable Bit 6 .. 7: Reserved

0200

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CIV 521

VARAN INTERFACE MODULE


Line Control Register Bit 0 .. 1: Word Length Select Bit 2: Number of Stop Bits Bit 3: Parity Enable Bit 4: Even Parity Select Bit 5: Stick Parity Bit 6: Set Break Bit 7: Reserved Divisor Latch Register Set the Baud rate Bytes to Send Counter reserved Transmit Buffer reserved Modem Status Register Bit 0: Delta Clear to Send Bit 1: Delta Data Set Ready Bit 2: Trailing Edge Ring Indicator Bit 3: Delta Data Carrier Detect Bit 4: Clear to Send Bit 5: Data Set Ready Bit 6: Ring Indicator Bit 7: Data Carrier Detect Line Status Register Bit 0: Transmitter Holding Register Empty Bit 1: Parity Error Bit 2: Framing Error Bit 3: Break Control Bit Bit 4: Busy Bit 5 : Receive Buffer Overflow Bit 7 6: reserved Modem Control Register Bit 0: Data Terminal Ready Bit 1: Request to Send Bit 2: Mode/de: 0 = RS 232 mode, 1 = Data enable RS 422/485 Bit 3: Mode: 0 = RS422, 1 = RS485 Bit 4: Loop Bit 5: Echo 1 = disable Bit 6 .. 7: Reserved Line Control Register Bit 0 .. 1: Word Length Select Bit 2: Number of Stop Bits Bit 3: Parity Enable Bit 4: Even Parity Select Bit 5: Stick Parity Bit 6: Set Break Bit 7: Reserved Receive Byte Counter -

0201

0202 0204 0205 0206 027E

2 1 1 120 2

w w r w

0280

0281

0282

0283

00

0284

00

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VARAN INTERFACE MODULE


0286 02FE 120 2 r r Receive Buffer Reserved 00 00

CIV 521

Generate IRQ User IRQ Register Bit 0 : DIAS user IRQ 0800 1 r Bit 1 : CDIAS IRQ0 Bit 2 : CDIAS IRQ1 Bit 3..7 : reserved System IRQ Register Bit 0 : DIAS error IRQ 0801 1 r Bit 1: System status IRQ Bit 2..7 : reserved 0802 0803 1 1 r/w r/w User Interrupt Enable Register System Interrupt Enable Register 00 00 00 00

I2C Master Interface 0820 2 r/w Clock Prescale Register Control Register Bit 0..5: reserved Bit 6: Interrupt enable ('1' = enable) Bit 7: I2C core enable ('1' = enable) Transmit Register Bit 0: when data transfer Bit 0 = LSB, when slave address transfer Bit 0 = read or write bit ('1' = read) Bit 1..7: next byte to transmit Receive Register Command Register Bit 0: Interrupt acknowledge (set '1' clears a pending interrupt) Bit 1..2: reserved Bit 3: acknowledge ('0' = ack, '1' = nack) Bit 4: write to slave Bit 5: read from slave Bit 6: generate stop condition Bit 7: generate start (repeated start) condition Status Register Bit 0: interrupt flag Bit 1: transfer in progress Bit 2..5: reserved Bit 6: bus busy Bit 7: receive acknowledge from slave ('0' = ack) FFFF

0822

r/w

00

0823

00

0823

00

0824

00

0824

00

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CIV 521
0825 IC Mux 10

VARAN INTERFACE MODULE


reserved

0830

I2C Software Request: Bit 0: reserved Bit 1: CDIAS EEPROM I2C Software Grant: Bit 0: reserved Bit 1: CDIAS EEPROM 00 FF 10 FF 00

0830

0831 0832 0833

1 1 13

r r

reserved I2C Bus Configuration 1: Type of I2C Bus (CDIAS EEPROM) reserved

CDIAS Interface CDIAS Interface Note : These registers have a slower intern processing time in the Varan Client. tClient_access = (300 ns + tCDIAS_READY_DELAY) / byte (see Varan Bus timing in the Varan Bus Specification)

1000

2048

r/w

DPRAM 2000 4096 r/w DPRAM

CAN Interface Handler Transmit Isochronous Message - Configuration Message TX_ISO1 Configuration Register Bit 7 6: Reserved Bit 5 : Remote Bit 4 : Extended Identifier Bit 3 0: DLC Data length Code Message TX_ISO1 Arbitration Register Bit 31 ... 29: Reserved Bit 28 ... 0: ID28 ID0 Message TX_ISO1 Start Address (0 = End of messages) e.g. x0200 Reserved Message TX_ISO2 Configuration Register Bit 7 6: Reserved Bit 5 : Remote Bit 4 : Extended Identifier Bit 3 0: DLC Data length Code Message TX_ISO2 Arbitration Register Bit 31 ... 29: Reserved Bit 28 ... 0: ID28 ID0

4000

r/w

00

4001

r/w

00000000

4005 4007

2 1

r/w r/w

0000 00

4008

r/w

00

4009

r/w

00000000

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VARAN INTERFACE MODULE


400D 400F 4010 2 1 r/w r/w Message TX_ISO2 Start Address (0 = End of messages) e.g. x0200+9 Reserved

CIV 521
0000 00

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CIV 521

VARAN INTERFACE MODULE

Transmit Isochronous Message - Data and Control Message TX_ISO1 Data 0 7 *) Address is not fix, can be configured. Message TX_ISO1 Control Bit 7 1: Reserved Bit 0 : Transmit Request *) Address is not fix, can be configured. Message TX_ISO2 Data 0 7 *) Address is not fix, can be configured. Message TX_ISO2 Control Bit 7 1: Reserved Bit 0 : Transmit Request *) Address is not fix, can be configured. Message TX_ISO3 TX_ISO14 (max. 14 x 9 bytes = 126 bytes in one VARAN object) *) Address is not fix, can be configured. Transmit Asynchronous Message - Configuration, Data and Control 4400 4402 2 2 r/w Clear Transmit Request Register Bit 15 0: 1 = Clear Transmit Request Message TX_ASY16 TX_ASY1 Reserved Transmit Request Register Bit 15 0: Transmit Request Message TX_ASY16 TX_ASY1 Transmit Request Bit is reset after sending. (Write Bit = 0 dont care) E.g. for transmitting of message TX_ASY1 set Bit 0 = 1 and pinl this Bit until = 0, before starting new request. Reserved Message TX_ASY1 Configuration Register Bit 7 6: Reserved Bit 5 : Remote Bit 4 : Extended Identifier Bit 3 0: DLC Data length Code Message TX_ASY1 Arbitration Register Bit 31 ... 29: Reserved Bit 28 ... 0: ID28 ID0 0000 0000 00000000 00000000 00000000 00000000

4200*

4208*

00

4209*

4211*

00

4212*

4404

r/w

0000

4406

0000

4408

r/w

00

4409

r/w

00000000

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VARAN INTERFACE MODULE


440D 8 r/w Message TX_ASY1 Data 0 -7 Message TX_ASY2 Configuration Register Bit 7 6: Reserved Bit 5 : Remote Bit 4 : Extended Identifier Bit 3 0: DLC Data length Code Message TX_ASY2 Arbitration Register Bit 31 ... 29: Reserved Bit 28 ... 0: ID28 ID0 Message TX_ASY2 Data 0 -7 Message TX_ASY3 TX_ASY16 (max. 9 x 13 + 4 = 121 bytes in 1st VARAN object, and max. 7 x 13 = 91 bytes in 2nd VARAN object) Reserved

CIV 521
00000000 00000000

4415

r/w

00

4416

r/w

00000000 00000000 00000000

441A

r/w

4412

182

r/w

44D8

812

Receive Isochronous Message - Configuration Message RX_ISO1 Configuration Register Bit 7 6: Reserved Bit 5 : Remote Bit 4 : Extended Identifier Bit 3 0: Reserved Message RX_ISO1 Arbitration Register Bit 31 ... 29: Reserved Bit 28 ... 0: ID28 ID0 Message RX_ISO1 Start Address (0 = End of messages) e.g. x0A00 Reserved Message RX_ISO2 Configuration Register Bit 7 6: Reserved Bit 5 : Remote Bit 4 : Extended Identifier Bit 3 0: Reserved Message RX_ISO2 Arbitration Register Bit 31 ... 29: Reserved Bit 28 ... 0: ID28 ID0 Message RX_ISO2 Start Address (0 = End of messages) e.g. x0A00+9 Reserved

4800

r/w

00

4801

r/w

00000000

4805 4807

2 1

r/w r/w

0000 00

4808

r/w

00

4809

r/w

00000000

480D 480F 4810

2 1

r/w r/w

0000 00

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CIV 521

VARAN INTERFACE MODULE

Receive Isochronous Message - Control and Data Message RX_ISO1 Data 0 7 *) Address is not fix, can be configured. Message RX_ISO1 Bit 7 4: DLC Data length Code Bit 3 0: Receive Counter *) Address is not fix, can be configured. Message RX_ISO2 Data 0 7 *) Address is not fix, can be configured. Message RX_ISO2 Bit 7 4: DLC Data length Code Bit 3 0: Receive Counter *) Address is not fix, can be configured. 4A12* Message RX_ISO3 RX_ISO14 (max. 14 x 9 bytes = 126 bytes in one VARAN object) *) Address is not fix, can be configured. Receive Asynchronous Message Configuration Message RX_ASY1 Configuration Register Bit 7 6: Reserved Bit 5 : Remote Bit 4 : Extended Identifier Bit 3 0: Reserved Message RX_ASY1 Arbitration Register Bit 31 29: Reserved Bit 28 0: ID28 ID0 Message RX_ASY1 Mask Register Bit 31 29: Reserved Bit 28 0: ID28 ID0 Message RX_ASY1 Start Address (0 = End of messages) e.g. x0E00, but it is automatically the start address of FIFO = x0E00 Reserved Message RX_ASY2 Configuration Register Bit 7 6: Reserved Bit 5 : Remote Bit 4 : Extended Identifier Bit 3 0: Reserved Message RX_ASY2 Arbitration Register Bit 31 29: Reserved Bit 28 0: ID28 ID0 00000000 00000000 00000000 00000000

4A00*

4A08*

00

4A09*

4A11*

00

4C00

r/w

00

4C01

r/w

00000000

4C05

r/w

00000000

4C09

r/w

0000

4C0B

r/w

00

4C0C

r/w

00

4C0D

r/w

00000000

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18.12.2009

VARAN INTERFACE MODULE


Message RX_ASY2 Mask Register Bit 31 29: Reserved Bit 28 0: ID28 ID0 Message RX_ASY2 Start Address (0 = End of messages) Reserved

CIV 521

4C11

r/w

00000000

4C15 4C17 4C10

2 1

r/w r/w

0000 00

Receive Asynchronous Message FIFO Transmit Request Status Register Bit 15 0: Transmit Request Bits Message 31 15 Transmit Request Bit is reset after sending. Software must pinl this Bit until = 0, before starting new request. The Transmit Request Register is here mapped too, for reducing VARAN objects. Reserved FIFO Status Register Bit 15: 1 = FIFO overflow Bit 14 11: Reserved Bit 10 0: Available bytes in FIFO Message RX_ASY_X Data 0 7 Message RX_ASY_X Bit 7 4: DLC Data length Code Bit 3 0: Reserved Message RX_ASY_X ID Register Bit 31 29: Reserved Bit 28 0: ID28 ID0 Message RX_ASY_Y Data 0 7 Message RX_ASY_Y Bit 7 4: DLC Data length Code Bit 3 0: Reserved Message RX_ASY_Y ID Register Bit 31 29: Reserved Bit 28 0: ID28 ID0 Message RX_ASY_Z (max. 9 x 13 + 2 + 4 bytes = 123 bytes in one VARAN object) Reserved

4E00

0000

4E02

0000

4E04

r16

0000

4E06

00000000 00000000 00

4E0E

4E0F

00000000 00000000 00000000 00

4E13

4E1B

4E1C

00000000

4E10 4E7C

392

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CIV 521

VARAN INTERFACE MODULE

Global Configuration Control Register Bit 7: Transmit interrupt enable Bit 6: Receive interrupt enable Bit 5: Bus off interrupt enable Bit 4 2 : Reserved Bit 1: Receive FIFO reset (1 = clear all data in FIFO) Bit 0: CAN enable (0 = disabled, 1 = enabled) Status Register (IRQ Quit register) Bit 7: Reserved Bit 6 4: Last error code Bit 3 2: Reserved Bit 1: Receive Error Passive Bit 0: Error warn level Bit Timing Register 0 Bit 15: SPL Sample Mode (1 = three samples, 0 = one sample) Bit 14 13: SJW - Synchronization Jump Width (0 .. 3) Bit 12 0: TSEG1 Time Segment 1 (0 .. 16383) Bit Timing Register 1 Bit 15 11 Reserved Bit 10 0: TSEG2 Time Segment 2 (1 .. 4095) Transmit Error Counter Bit 15 9: Reserved Bit 8 ... 0: Transmit Error Counter Receive Error Counter Transmit Isochronous not ready Counter IRQ register (IRQ is cleared at reading) Bit 7: Transmit interrupt (one asynchronous message transmitted) Bit 6: Receive interrupt (one asynchronous message received) Bit 5: Bus off interrupt Bit 4 0: Reserved Reserved Maximal Isochronous Transmit Time[10 ns] (After this time, when not all messages were sent, the transmit isochronous not ready Counter would be incremented)

5000

r/w

00

5001

00

5002

r/w

0000

5004

r/w

0000

5006 5008 5009

2 1 1

r r r/w

0000 00 00

500A

00

500B

00

500C

r/w

00000000

Page 38

18.12.2009

VARAN INTERFACE MODULE


Data Mover Control Register Bit 0: mover enable Bit 1: synchronous list enable Bit 2: admin access enable Bit 3: asynchronous list enable Bit 4: DIAS alive enable Bit 5: hold on OP-Code error Bit 6: hold on WB-Error Bit 7: hold on Time Slice Error Status Register Bit 0: mover active Bit 1: synchronous access active Bit 2: admin access active Bit 3: asynchronous access active Bit 4: fast access active Bit 7 5: reserved (read as zero) 8002 1 r reserved (read as zero) Error Register Bit 0: OP-Code Error, Synchronous list Bit 1: OP-Code Error, Asynchronous list Bit 2: OP-Code Error, Admin Access Bit 3: OP-Code Error, Fast Access Bit 4: Wishbone Bus Error Bit 5: Time slice error Bit 7 6: reserved Synchronous list time register (maximum execution time of synchronous list, in s) Synchronous Counter (Duration time of Synchronous list, in s), (as overflow counter) 8004 2 r 8006 2 r reserved Asynchronous Counter (Duration time of Asynchronous list, in s) (as overflow counter) 8008 2 r 800A 22 r time of list execution (active time of the list) only read when list is not active time between sync and end of the list execution only read when list is not active 00

CIV 521

8000

r/w

00

8001

00

8003

00

8004

0000

0000

0000

reserved

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CIV 521
8020 8022 8024 8026 8028 802A 802C 802E 8030 8032 8034 8036 80F4 2 2 2 2 2 2 2 2 2 2 2 190 4

VARAN INTERFACE MODULE


r/w r r/w r r/w r r/w r r/w r r/w r r/w Synchronous list start address reserved Synchronous list end address reserved Asynchronous list start address reserved Asynchronous list end address reserved Admin Access list start address (when enabled) reserved Admin Access list end address (when enabled) reserved DIAS Alive Address DIAS Alive mode Bit 0..1 : Access Mode (wishbone, see 5.1.3.1 for more 0000 00 0000 00 0000 00 0000 00 0000 00 0000 0000 0000

80F8

r/w information, ) Bit 2 ..7 : reserved

00

80F9 80FA

1 4

r/w

reserved Fast Access Data Address Fast Access Control Register Bit 0..3 : Command

0000

80FE

r/w

Bit 4 Bit 5

: Fast Access enable : reserved

00

Bit 6..7 : Access Mode (wishbone) (see 5.1.3.1) 80FF 8100 9100 1 4096 2048 r/w r/w (First 122 bytes are used for storage of Fast Access Data) r/w Admin DPRAM (when enabled) Fast Access Number of Bytes (see 5.1.3.5) Code DPRAM 00

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VARAN INTERFACE MODULE

CIV 521

Detailed Addressing for Subsystem Components


Address (hex) CDIAS Interface CDIAS Interface Note : These registers have a slower intern processing time in the VARAN Client. tClient_access = (300 ns + tCDIAS_READY_DELAY) / byte (see VARAN Bus timing in the VARAN Bus Specification) Size (Byte) Access Type: Description Reset value

0000

2048

r/w

DPRAM 2000 DIAS Master 1000013FFF 1400017FFF 180001BFFF 16000 16000 16000 r/w r/w r/w DIAS Byte access DIAS Word access DIAS Control access Error Source Register 1C000 1 r Bit 5..0: module number Bit 7..6: code a Retry Counter all modules 1C008 1 r This byte is incremented on each retry. Retry Register 1C00A 1 w Bit 1..0: Sets the number of retries on the DIAS bus. Error Register Bit 0: set if the number of retries on the DIAS bus is greater then the value in the Retry Register (DIAS Error). Writing any value to this register resets the Error Flag. 1C00C 1C00C 1C00D 1C00E 1 1 1 1 w r r r IRQ Scan Delay Register Bit 3..0: defines the time to elapse to start a IRQ scan in multiples of 4us. Hardware version FPGA version Old master ID, ASCII O 3 10 10 4F 03 00 00 4096 r/w DPRAM

1C00B

r/w

00

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CIV 521
1C00F

VARAN INTERFACE MODULE


1 r Old master ID, ASCII M IRQ Scan Source Register Bit 7..0: corresponds to the 8 possible interrupt sources. Set by IRQ scan and cleared by Software. Timeout Register Bit 3..0: defines the time to elapse to start a retry in multiples of 2us. IRQ Scan Module Address Register Specify the Module numbers for the IRQ scan. 4D

1C010

r/w

00

1C014

1C0181C01F

r/w

FF FF FF ..

Page 42

18.12.2009

VARAN INTERFACE MODULE

CIV 521

VARAN Recommended Shielding


The VARAN real-time Ethernet bus system offers robust performance in harsh industrial environments. Through the use of IEEE 802.3 standard Ethernet physics, the potential between an Ethernet line and sending/receiving components is kept separate. The VARAN Manager resends messages to a bus participant immediately when an error occurs. It is principally recommended that the shielding guidelines below be followed. For applications in which the bus line is run outside the control cabinet, correct shielding is required. This is especially important, if due to physical requirements, the bus lines must be placed next to sources of strong electromagnetic noise. It is recommended that whenever possible, to avoid wiring VARAN-Bus lines parallel to power cables. SIGMATEK recommends the use of CAT5e industrial Ethernet bus lines. For the shielding variants, an S-FTP bus line is recommended, which is a symmetric, multiwire cable with unshielded pairs. For the total shielding, a combination of foil and braiding is used; it is recommended that an unvarnished variant be used. The VARAN cable must be secured at a distance of 20 cm from the connector for protection against vibration!

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CIV 521

VARAN INTERFACE MODULE

1. Wiring from the Control Cabinet to an External VARAN Component


If the Ethernet lines are connected from a VARAN component to a VARAN node outside the control cabinet, the shielding should be placed at the entry point to the control cabinet housing. All noise can then be deflected from the electronic components before reaching the module.

Page 44

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VARAN INTERFACE MODULE

CIV 521

2. Wiring Outside of the Control Cabinet


If a VARAN bus line must be connected outside of the control cabinet only, no additional shielding is required. Outside the control cabinet, IP67 modules and connectors are used only. These components have an extremely robust and noise-resistant structure. The shielding for all sockets in IP67 modules are internally connected to a common bus or electrically connected to the housing, whereas the deflection of voltage spikes does not flow through the electronics.

18.12.2009

Page 45

CIV 521

VARAN INTERFACE MODULE

3. Shielding for Wiring Within the Control Cabinet


Sources of strong electromagnetic noise located within the control cabinet (drives, Transformers, etc.) can induce interference in a VARAN bus line. Spike voltages are deflected over the metallic housing of a RJ45 connector. Noise is conducted through the control cabinet housing without further action from the electronic components To eliminate sources of noise during data transfer, it is recommended that the shielding from all electronic components be connected within the control cabinet.

Page 46

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VARAN INTERFACE MODULE

CIV 521

4. Connecting Noise-Generating Components


With the connection of power components that generate strong electromagnetic noise, it is also critical to ensure correct shielding. The shielding should be placed before a power component (or a group thereof).

18.12.2009

Page 47

CIV 521

VARAN INTERFACE MODULE

5. Shielding Between Two Control Cabinets


If two control cabinets must be connected over a VARAN bus, it is recommended that the shielding be located at the entry points to both cabinets. Noise can thereby be kept from reaching the electronics within the control cabinet.

Page 48

18.12.2009

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