Simulation and generation of SPWM waveform using VHDL for FPGA interfaced H Bridge Power Inverter

Mriganka Sekhar Sur , S. N. Singh, Anumeha, Puspa Kumari

Electronics and Communication Engineering Department NIT Jamshedpur(India) mriganka_sur@yahoo.co.in, snsnitjsr@gmail.com
AbstractIn this paper, we propose a novel scheme to generate sinusoidal pulse width modulated (SPWM) switching pulses using Direct Modulation Strategy and its implementation has been done through software developed using VHDL code. In the given proposed scheme, the periodic PWM signals are generated, separated by positive and negative group of polarity control switching pulse and evoked at the output as a control signal for FPGA interfaced H bridge inverter circuit. Keywords - VHDL; MUX; polarity control; multiple circuit switching. (Sinusoidal pulsewidth modulation (SPWM)) .

q = MUX output (PWM Main Switching Signal) w00 = Pulse width P( i = 1) w11 = Pulse width P( i =2) wii = Pulse width P( i =N) The positive half cycle and negative half cycle group of PWM control pulses are extracted with the following logical expression (Eq. 2 and Eq. 3). mss_p = q AND w33 (positive group) mss_n = q AND (NOT w33) ( negative group) (2) (3)

I.

INTRODUCTION

Sinusoidal Pulse Width Modulation, abbreviated as SPWM, is a method of transmitting information on a series of pulses. A proper use of signal generator with varying pulse width in accordance with amplitude of sine wave can produce approximated sine wave through an inverter circuit on averaging its output pulses [1]. In direct modulation scheme PWM pulses are generated directly and thus require less memory space as compared to conventional sine-triangular scheme [2]. This effectively simplifies the circuit and reduces the power consumption during the process of PWM signal generation without subtle loss or no loss at all. The proposed scheme is based on VHDL coded software developed with flexibility in its algorithm for generation of N number of control SPWM pulses in each cycle and easily be implemented to produce AC power using FPGA interfaced H bridge power inverter circuit. II. SOFTWARE SCHEME FOR PWM GENERATION

The truth table of MUX for PWM pulses (N=3) is shown in Table 1.
TABLE I.
S[1]

T RUTH TABLE OF MUX FOR N=3 Output

S[0] q(N)

Selection Line Inputs 0 0 1 1 0 1 0 1

w00 w11 w22 w22

The software for generation of SPWM pulses has been developed in VHDL code as per the algorithm given below: The sinusoidal amplitude modulated pulse width Pi ( i = 1,2..N) of each cycle is fed to the MUX unit for outputting N number of PWM control pulses and is outputted by the logical expression (Eq. 1). q(N) = w00 + w11+ w22wii where, i =1,2 .. N = Number of PWM pulses in each half of a cycle (1)

The algorithm has been implemented using VHDL code. VHDL is the acronym for Very High Speed Integrated Circuit (VH_SIC) hardware Descriptive Language. It is a high level programming language used for designing, simulating and synthesizing complex digital logic circuits. In the given proposed scheme, a MUX is used for multiplexing the individual pulses of SPWM wave of varying pulse width i.e Pi which are generated by signal generators. The scheme is applicable for both periodic and a-periodic wave form of different frequency with N number of PWM pulses. Polarity control are introduced to get positive and negative group of signal required to generate a AC sine wave as shown in combinational logic block of schematic diagram (Figure 1 (a)

and (b)) The entity of the control circuit with its architecture is shown in Figure 2 and Figure 3.. The output signal S(1:0) is the selection line of MUX unit.

drive pulses which can be interfaced with H Bridge Inverter circuit to get approximated sine wave. III. PROGRAMMING WITH VHDL

(a)

The programming in VHDL is done in two stages. The first stage consists of entity declaration in which the whole circuit can be seen as a black box of which a set of input and outputs are defined. This portion of programming is done with an external view. The entity of the given programme is shown in Figure 2. In the second stage the internal architecture is defined i.e. the exact connections and the required logic is defined in this section. The internal architecture of the circuit is shown in Figure 3. The steps of operation for the simulating the program developed in VHDL code [3] have been followed as per the instructions summarized below: Step 1 : Open New Project from the File menu. Step 2 : Enter the project name as RTL. Click Next to Continue. Step 3 : Enter the FPGA kit properties in the Device Properties window. Click Next to get the New Project Wizard Step 4 : Select New Source and enter RTL in File Name and select VHDL Module. Check on Add Project. Step 5 : Enter the name of the input and output ports. Step 6 : Click Finish and then Yes. Step 7 : Click Next. Again click next and then Finish. Step 8 : Now we get the RTL.vhd file which already consists of libraries, entity declaration . Step 9: Now edit the architecture body as given in the code. Step 10: After writing the complete code save the code and double click on Check syntax. It will check for the syntax error. Step 11: Then click on View Technological Schematic in Process tab to see the block diagram on entity. Step 12: Then click on View RTL Schematic in Process tab to see the Figure 6. Step 13: Select Behavioral Simulation from Sources For menu in Sources tab. Step 14: Double click on Create New Source . Write TRTL in the File Name and select Test Bench WaveForm. Click Next to continue. Step 15: Click Next and then Finish to generate the testbench waveform. Step 16: At first the Initial Timing and Clock Wizard will appear where the clock properties can be edited. Select Single Clock and then click on Finish Step 17: Now we get the unedited testbench wave form. Set RST as high and save it. Step 18: Click on Process tab and then on the plus sign of Xilinx ISE Simulator. Then double click on Simulate Behavioral Model. Now the simulated waveform is generated . A few representative windows are shown in Figure 4, 5 and 6.

(b)
Figure 1(a) Block diagram of the PWM waveform (b) Power H- Bridge inverter module

The program has been downloaded on FPGA board using Xilinx ISE Simulator (version 9.2i) to generate base drive signal for H Bridge Inverter circuit which can produce approximated sine wave output of variable frequency.
Figu Entity of circuit re 2. the

Figure 3. The internal architecture of the circuit

The outputs w00, w11, w22 are the specified generated input by signal generator signals and w33 is the polarity control signal. mss_p and mss_n are the multiplexed signals for the positive and negative group signal respectively. The CLKIN is the master clock synchronized with input and output signals. The positive and the negative parts i.e. mss_p and mss_n are obtained after ANDing with MUX output (mss) with the polarity control signal. A counter is used to generate the selection lines S(1: 0). The reset pin (RST) is used as like a key to switch on the circuit i.e when the RST is 0 the output is zero and when RST is made 1 we get the signal according to the switching. At the output we affectively get the Control base

Figure 4. Project wizard on ISE Xilinx 9.2i

combination. During coding sometimes we need to use some internal signals which are not visible from outside. Such signals demand declaration before using them in the logic. The keyword signal is used for this purpose. Even it is possible to assign a specific value (for example signal CLK_0: std_logic := '0'; is used in the code) to them otherwise they are associated with the default values by the compiler. In our code there is a master clock which is fed to the signal generator in order to generate all the signals. There is a use of counter which selects the input channels of the MUX. The output of the MUX is ANDed with the polarity control signal to produce the mss_p output. The other output is the mss_n which is produced by ANDing the MUX output with the inverted polarity control signal. Here the use of polarity control signal is to extract the positive half (mss_p) and the negative half(mss_n) from the MUX output. From the output (Figure 7) it is clearly seen that both of the mss_p and mss_n can drive positive and negative group of inverter module to get the sinusoidal signal across load (Figure 8).

Figure 5. New source wizard on ISE Xilinx 9.2i

Figure 7 : Output control pulses (a) PWM Main Switching Signal (Top) (b) positive group of the PWM signal (Middle) and (c) Negative group for H bridge inverter circuit.(Bottom)

Figure 6. Status of the RTL project wizard

IV.

PROGRAM DESIGN[4]

In order to write the program, the programmer needs to declare the libraries in which the definition or prototype are defined similar like Java. In Java we need to import the packages and in VHDL we need to declare the libraries by use keyword. After that the entity is declared where all the inputs and outputs (like inputs and outputs of a black box) are specified. Next comes the architecture defining. In VHDL architecture can be defined in mainly three ways as follows: Structural Style Dataflow Style Behavioral Style.

Figure 8. Voltage waveform across load

V.

SOURCE CODE

The source code of the program in VHDL[5][6][7] developed for generation of PWM sinewave is described as given below:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity RTL is Port (CLKIN: in std_logic;

Another possible way of defining the architecture is Mixed Style in which all of the above three can be used at any

RST: in std_logic; w00: out STD_LOGIC; w11: out STD_LOGIC; w22: out STD_LOGIC; w33: out STD_LOGIC; S : out STD_LOGIC_VECTOR (1 downto 0); mss : out STD_LOGIC; mss_p : out STD_LOGIC; mss_n : out STD_LOGIC); end RTL; architecture Behavioral of RTL is -- Signals and constants declaration signal CLK_0: std_logic := '0'; signal CLK_90: std_logic := '0'; signal CLK_1X: std_logic := '0'; signal LOCKED_DLL: std_logic := '0'; signal clk_buf: std_logic := '0'; signal clk_fbbuf: std_logic := '0'; signal clk_100: std_logic := '0'; signal q: STD_LOGIC; signal w0: STD_LOGIC; signal w1: STD_LOGIC; signal w2: STD_LOGIC; signal w3: STD_LOGIC := '0'; signal count: std_logic_vector(1 downto 0); begin clk_buf <= CLKIN; clk_fbbuf <= CLK_1X; process (RST,clk_buf,clk_100) begin if(RST = '0')then CLK_0 <= '0'; CLK_90 <= '0'; CLK_1X <= '0'; else clk_100 <= clk_buf after 40 ns; CLK_0 <= clk_buf xor clk_100; CLK_90 <= (clk_buf xor clk_100) after 30 ns; CLK_1X <= clk_buf; end if; end process; w0 <= CLK_0; w1 <= not (CLK_90); w2 <= not (CLK_0); w3 <= not w3 after 220 ns; process (CLKIN, RST) begin if RST ='0' then count<= "00"; elsif( RST='1') then count <= (count +1) after 70 ns; else count <= count; end if; end process; with count select q<= w0 when "00", w1 when "01", w2 when others; mss_p<= q and w3; mss_n<= q and (not w3); S <= count; mss <= q;

w00 <= w0; w11 <= w1; w22 <= w2; w33 <= w3; end Behavioral;

VI.

OUTPUT

The output of the simulated PWM control pulses are shown in Figure 9.

Figure 9. Simulated output

VII. APPLICATION The proposed scheme can be used for qualitative AC power generation from conventional as well as renewable energy input sources like PV, wind, tidal etc. Since the output waveform is a PWM sine wave and hence on averaging it, an approximation to a sine wave containing fewer harmonics is achievable. The realization of simulated waveform through hardware circuit can be easily implemented using FPGA module or in embedded ASIC chip. VIII. CONCLUSION An attemt has been made to simulate Sinusoidal PWM pulses using Direct Modulation strategy and its implementation has been carried out using VLSI technology on FPGA board. The scheme has been successfully implemented. IX. ACKNOLEDGEMENT

The work has been carried out in the VLSI System Design Laboratory of NIT Jamshedpur. The authors are thankful to the institute for providing the facility to carry out the experimental work.

REFERENCES
[1] Rashid M., Power electronics: circuits, devices and application Prentice Hall India, 2004

[2]

[3] [4] [5]

R. Seyezhai and Dr. B. L. Mathur, Performance evaluation of inverted sine pwm technique for an asymmetric cascaded multilevel inverter JATIT, 2005. www.xilinx.com. Jayaram Bhaskar, A VHDL primer Prientice Hall, 1992 pp. 6-12. Mayer-Lindenberg F.,High-Level FPGA Programming through Mapping Process Networks to FPGA Resources, 2009.

[6] [7]

Stephen Brown and Zvonko Vranesic, Fundamentals of digital logic design with VHDL, TMH, 2009, pp.341-344. Charles h Roth,jr., Digital system design using VHDL, PWS Publishing Company 2001, pp.7879.