Chapter IC 1. What do you mean by VLSI?

? Classify integrated circuit based on both the scale of integration and the structure? (3) 09 2. Discuss the problems associated with IC design. (6) 09 3. What are the advantages and disadvantages of IC? (3) 09 4. What do you know about analog and digital ICs? (3) 09 5. What are the active and passive components? (3) 09 6. Write the advantages of MOS technology over bipolar technology.(3) 09 7. Describe the various steps of fabricate IC. (6) 09 8. Draw the fabrication steps of an NPN transistor. (4) 09 9. What is VLSI? (2) 08 10. What are the available varieties of integrated circuit? (3) 08 11. Explain the problems the IC designers generally face. (6) 08 12. Describe the design abstraction with example. (4) 08 13. Define the following terminology: 1) Chip 2) Etching 3) Wafer. (3) 08 14. Explain the fabrication of a monolithic IC by the epitaxial diffusion process. (9) 08 15. Sketch the fabrication of the following components: 1) B 2) A K (3) 08

16. Define the following terminology: 1) Chip 2) Etching 3) Wafer. (3) 07 17. Define SSI, LSI, and VLSI circuits. (3) 07 18. What are the advantages of ICs over conventional circuits? What are its drawbacks? (4) 07 19. Define sheet resistance. Sketch the cross section of an IC resistor. (4) 07 20. Name and explain the different steps involved in the fabrications of monolithic integrated circuits. (6) 07

21. What do you mean by integrated circuit? Briefly explain the advantages and disadvantages of IC. (2+6) 07 22. Classify integrated circuit based on level of integration. (2) 07 23. What are the active and passive components with example? (3) 07 24. Briefly explain the various stages of IC manufacturing process. (8) 07 25. Draw and explain the fabrication of NPN transistor.(4) 07 26. Describe the various steps of fabricate IC. (6) 07 27. Define VLSI circuits. (2) 06 28. Describe the various steps of fabricate IC. (6) 06 29. What are the MOS devices? (2) 06 30. Explain conduction mechanism in enhancement type MOSFET. (3) 06 31. Draw IV characteristics of MOSFET and explain it. (3) 06 32. Discuss FET RC model. (2) 06 33. Define VLSI circuits. (2) 04 34. What are the advantages and disadvantages of IC. (3) 04 35. Discuss the design rules of VLSI circuits.(3) 04 36. Explain the design rules of VLSI circuits.(4) 03 37. Briefly discuss the function of Czochralski crystal apparatus.(6) 03 38. What are the roles of masking and etching in monolithic fabrication?(6) 03 39. Explain the process of masking and etching process.(5) 03 40. Explain the epitaxial growth process.(4) 03 41. Name and explain the different steps involved in the fabrications of monolithic integrated circuits.(6) 02 42. Define sheet resistance. Sketch the cross section of an IC resistor.(4) 02 43. Define SSI, LSI, and VLSI circuits.(3) 01

44. What are the advantages of ICs over conventional circuits? What are drawbacks? (4) 01 45. Discuss the different steps and process in preparing silicon wafer from metallurgical grade silicon.(4) 01 46. What are the different techniques used in isolation process. (4) 01 47. What are the roles of masking and etching in monolithic fabrication? (6) 01 48. Explain the steps involved in masking and etching process. (5) 01 50. Describe the design methodology adapted to VLSI design. (5)01 CHAPTER-2: 1. Define threshold voltage. Find an expression for threshold voltage of an NMOS devices.(6) 09 2. Explain the V/I characteristics of an NMOS transistor.(6) 09

3. Why it is not practical to use a resistor as a load in MOS inverter? Explain. (3) 09 4. Define threshold voltage. Find an expression for threshold voltage of an NMOS devices.(6)08 5. 6. Explain the structure of an NMOS inverter with a resistor load.(5) 08 What do you mean by body effect in MOS transistor?(3)08

7. Deduce the equations of i).fall time and ii) rise time of an NMOS inverter with a depletion load.(8) 08 8. The aspect ratio of load transistor of an NMOS inverter with an NMOS depletion load is . If its output capacitance is 0.1 PF, calculate the rise time of it.(2) 08 9. What do you mean by pass transistor? Explain its function.(2+3) 08

10. Define threshold voltage. Find an expression for threshold voltage of an NMOS devices.(6)07 11. 12. 13. What do you mean by body effect in MOS transistor?(3)07 Write the advantages of MOS IC over bipolar IC.(3)07 What are the MOS devices.(2)07

14.

Describe the principles of CMOS inverter.(4) 06

15. Deduce the equations of i).fall time and ii) rise time of an NMOS inverter with a depletion load.(8) 06 16. 17. What is pass transistor? Describe NMOS pass transistors.(6) 06 What do you mean by body effect in MOS transistor?(3)04

18. Discuss Ids versus Vds characteristics for NMOS devices and hence deduce the equations for Ids both in resistive and saturation region.(7) 04 19. 20. 21. What do you mean by ratioed and ratio less design?(3) 04 Draw and explain the structure and operation of a CMOS pass gate.(4) 04 Explain the reason to use a buffer gate chain. (3) 04

22. Describe the basic structure and conduction mechanism in an NMOS transistor. (5) 03 What is the difference between enhancement mode and depletion mode transistor? (2) 03
23.

24.

Explain the body effect in MOS transistors?(3) 03

25. Why it is not practical to use a resistor as a load in MOS inverter? Explain. (3) 02 26. Describe the main drawbacks of an NMOS enhancement load in NMOS inverter.(3) 02 27. The aspect ratio of load transistor of an NMOS inverter with an NMOS depletion load is . If its output capacitance is 0.1 PF, calculate the rise time of the inverter output.(3) 02 28. 29. 30. Explain ratioed and ratio less design?(3) 04 Draw and explain the ratio less inverter circuit.(4) 02 Explain the reason to use a buffer gate chain. (3) 02

31. What is the difference between enhancement mode and depletion mode MOS transistors?(3) 01 32. 33. What do you mean by body effect in MOS transistor?(3)01 Describe the principles of CMOS inverter.(4) 01

34. 35.

What is pass transistor? Describe NMOS pass transistors.(6) 01 What is CMOS pass gate.(2) 01 CHAPTER-3:

1.

Explain the fabrication process of CMOS inverter.(7) 09 Write the name of some electrical parameters.(4) 09

2.
3.

Find the following values: i) Line resistance ii) Line capacitance. For an interconnection of length L /m ,width w m having resistance of R /sqr and a capacitance Ci PF/m2 .(3)09 4. What are the advantages of using design rules in design process of an IC ,explain with example.(5) 09 5. 6.
7.

Explain MOS processing.(5) 09,08 Explain the various steps in NMOS processing.(7) 08

The length of an interconnection is 0.5 m, width is 0.25 m, having a resistance of 1000 /sqr, and capacitance of 10 pF/m2. Calculate i) Line resistance ii) Line capacitance iii) Line delay.(3) 08 8. What are the advantages of using decision rules?(4) 07

9. The length of an interconnection is 0.5 m, width is 0.25 m, having a resistance of 1000 /sqr, and capacitance of 10 pF/m2. Calculate i) Line resistance ii) Line capacitance iii) Line delay.(3) 07,01 Draw the stick diagram and a mask layout for an 8:1 NMOS inverter circuit. Both the input and output points should be on the polysilicon layer.(4) 06
10.

11. 12. 13. 14. 15. 16. 17.

Discuss scaling model and scaling factor for NMOS transistor.(3) 06 Discuss some limitations of scaling.(3) 06 Explain the stick diagram with example.(4) 06 ,01 Explain the stick diagram. Write its advantages.(4) 09,03,04 Describe the MOS process.(4)02 What do you mean by yield? (2) 02 What is buffer contact? Give its advantages and disadvantages.(4) 02

CHAPTER-4: 2009:1. In general PLAs have not found as much acceptance in CMOS as in NMOS technology. Explain.(3) 2. What are circuits and disadvantages of PLA? (4)

3. Draw the generic floor plan for a simple PLA and briefly describe its cells.(5) 2008: 4. Illustrate the principle of a pass transistor array.(4)

5. What do you mean by a programmable logic array (PLA)? Draw its general structure.(2+4) 6. 2007: 7. Draw static complementary NAND gate and ins layout. (4) Write the advantages and disadvantages of a PLA .(5)

8. Compute the low-to-high delay through a two input NAND gate which derives one input of a three input NOR gate.(4) 9. Draw a stick diagram for a three input NOR gate.(3)

10. Draw a circuit diagram of a three input NOR gate designed in pseudoNMOS.(4) 11. Explain switch and gate simulation.(4)

12. What is crosstalk in combinational network and explain how they are minimized?(5) 13. Explain how combinational logic is tested.(3)

14. Find the combination of input transition which introduces maximum glitching at the primary output O. (3) a
b

2006: 15. 16. 2004: 17. 18. What are differences between static and dynamic circuits.(2) Draw the basic structure of a static flip-flop and describe its operation.(4) What are differences between static and dynamic flip-flop?(4) Discuss the design methodology of a dynamic flip-flop.(6)

19. Describe random logic and transistor array to implement combinational logic circuits.(5) 20. 2003: 21. Describe the differences between static and dynamic circuits.(3) Discuss about the design methodology of a dynamic flip-flop.(5)

22. Draw and explain a two input NAND gate by NMOS technology and CMOS technology.(7) 23. Explain the basis of a static flip-flop.(4)

24. Draw the logic symbol, circuit and logic diagrams of a Set-Reset NMOS static flip-flop.Explain its operation.(6) 2002: 25. Describe the basic dynamic flip-flop.(5)

26. Draw the circuit and describe the operation of a shift chain-using dynamic circuits.(5) 27. What is random access memory?(2)

28. Draw the general schematic and describe the operation of a 2n by one bit store.(5) 29. 2001: 1. Describe random logic and transistor array to implement combinational logic circuits.(5) Why and how the same lines may be used by the X and Y address?(3)

2. 3.

What is the difference between static and dynamic circuits?(2) Describe the advantages of pass transistor array.(3)

4. What do you mean by a programmable logic array(PLA)? Draw its general structure.(2+4) 5. Implement a PLA design for a three line priority encoder.(7)

CHAPTER-5: 2009: 1. (5) 2. 3. 2008: 4. 5. 6. 2007: 7. 8. 9. 10. 2006: 11.

12.

Briefly explain the architecture of general purpose central processing unit. Write short note on multiprogram control.(8) What are the main disadvantage of fixed control approach?(2)

Explain how serial scan testing is implemented.(5) Explain signature analysis and BILBO.(5) Explain TAP controller with suitable diagram.(5)

Explain how pipelining is used to decrease clock period.(4). Explain barrel shifter with circuit diagram.(4) Explain carry-skip adder with block diagram.(4) Draw structure of a Booth multiplexer and explain it.(4)

Describe the classification of control unit.(5) 01 Draw and explain the block diagram of a micro program control.(5)

2003: 13. Draw and explain the data architecture of general purpose central processing unit with timing and control block.(5)

14. What do you mean by chip testability? What problems may be encountered in testing of system?(5)