Mcs51 Guide

Novembei 1992
MCS-51 Programmers
Guide
and Instruction Set
COPYRIGHT INTEL CORPORATION 1996
Order Number 270249-003
MCS-51 PROGRAMMERS
GUIDE AND INSTRUCTION
SET
CONTENTS PAGE
MEMORY ORGANIZATION 1
PROGRAM MEMORY 1
Data Memory 2
INDIRECT ADDRESS AREA 4
DIRECT AND INDIRECT ADDRESS
AREA 4
SPECIAL FUNCTION REGISTERS 6
WHAT DO THE SFRs CONTAIN JUST
AFTER POWER-ON OR A RESET 7
SFR MEMORY MAP 8
PSW PROGRAM STATUS WORD BIT
ADDRESSABLE 9
PCON POWER CONTROL REGISTER
NOT BIT ADDRESSABLE 9
INTERRUPTS 10
IE INTERRUPT ENABLE REGISTER
BIT ADDRESSABLE 10
ASSIGNING HIGHER PRIORITY TO
ONE OR MORE INTERRUPTS 11
PRIORITY WITHIN LEVEL 11
IP INTERRUPT PRIORITY REGISTER
BIT ADDRESSABLE 11
TCON TIMERCOUNTER CONTROL
REGISTER BIT ADDRESSABLE 12
TMOD TIMERCOUNTER MODE
CONTROL REGISTER NOT BIT
ADDRESSABLE 12
TIMER SET-UP 13
TIMERCOUNTER 0 13
TIMERCOUNTER 1 14
T2CON TIMERCOUNTER 2 CONTROL
TIMERCOUNTER 2 SET-UP 16
SCON SERIAL PORT CONTROL
CONTENTS PAGE
SERIAL PORT SET-UP 17
GENERATING BAUD RATES 17
Serial Port in Mode 0 17
Serial Port in Mode 1 17
USING TIMERCOUNTER 1 TO
GENERATE BAUD RATES 18
CONTENTS PAGE
USING TIMERCOUNTER 2 TO
GENERATE BAUD RATES 18
SERIAL PORT IN MODE 2 18
SERIAL PORT IN MODE 3 18
MCS-51 INSTRUCTION SET 19
INSTRUCTION DEFINITIONS 26
MCS-51 PROGRAMMERS GUIDE AND INSTRUCTION SET
The infoimation piesented in this chaptei is coIIected fiom the MCS-51 AichitectuiaI Oveiview and the Haidwaie
Desciiption of the 8051, 8052 and 80C51 chapteis of this book. The mateiiaI has been seIected and ieaiianged to
foim a quick and convenient iefeience foi the piogiammeis of the MCS-51. This guide peitains specificaIIy to the
8051, 8052 and 80C51.
MEMORY ORGANIZATION
PROGRAM MEMORY
The 8051 has sepaiate addiess spaces foi Piogiam Memoiy and Data Memoiy. The Piogiam Memoiy can be up to
64K bytes Iong. The Iowei 4K (8K foi the 8052) may ieside on-chip.
Figuie 1 shows a map of the 8051 piogiam memoiy, and Figuie 2 shows a map of the 8052 piogiam memoiy.
2702491
Figure 1 The 8051 Program Memory
1
2702492
Figure 2 The 8052 Program Memory
Data Memory
The 8051 can addiess up to 64K bytes of Data Memoiy exteinaI to the chip. The MOVX instiuction is used to
access the exteinaI data memoiy. (Refei to the MCS-51 Instiuction Set, in this chaptei, foi detaiIed desciiption of
instiuctions).
The 8051 has 128 bytes of on-chip RAM (256 bytes in the 8052) pIus a numbei of SpeciaI Function Registeis (SFRs).
The Iowei 128 bytes of RAM can be accessed eithei by diiect addiessing (MOV data addi) oi by indiiect addiessing
(MOV

Ri). Figuie 3 shows the 8051 and the 8052 Data Memoiy oiganization.
2
2702493
Figure 3a The 8051 Data Memory
2702494
Figure 3b The 8052 Data Memory
3
INDIRECT ADDRESS AREA
Note that in Figuie 3b the SFRs and the indiiect addiess RAM have the same addiesses (80H0FFH). Neveithe-
Iess, they aie two sepaiate aieas and aie accessed in two diffeient ways.
Foi exampIe the instiuction
MOV 80H,0AAH
wiites 0AAH to Poit 0 which is one of the SFRs and the instiuction
MOV R0,80H
MOV

R0,0BBH
wiites 0BBH in Iocation 80H of the data RAM. Thus, aftei execution of both of the above instiuctions Poit 0 wiII
contain 0AAH and Iocation 80 of the RAM wiII contain 0BBH.
Note that the stack opeiations aie exampIes of indiiect addiessing, so the uppei 128 bytes of data RAM aie avaiIabIe
as stack space in those devices which impIement 256 bytes of inteinaI RAM.
DIRECT AND INDIRECT ADDRESS AREA
The 128 bytes of RAM which can be accessed by both diiect and indiiect addiessing can be divided into 3 segments
as Iisted beIow and shown in Figuie 4.
1 Register Banks 0-3 Locations 0 thiough 1FH (32 bytes). ASM-51 and the device aftei ieset defauIt to iegistei
bank 0. To use the othei iegistei banks the usei must seIect them in the softwaie (iefei to the MCS-51 Micio
AssembIei Useis Ouide). Fach iegistei bank contains 8 one-byte iegisteis, 0 thiough 7.
Reset initiaIizes the Stack Pointei to Iocation 07H and it is inciemented once to stait fiom Iocation 08H which is the
fiist iegistei (RO) of the second iegistei bank. Thus, in oidei to use moie than one iegistei bank, the SP shouId be
intiaIized to a diffeient Iocation of the RAM wheie it is not used foi data stoiage (ie, highei pait of the RAM).
2 Bit Addressable Area 16 bytes have been assigned foi this segment, 20H-2FH. Fach one of the 128 bits of this
segment can be diiectIy addiessed (0-7FH).
The bits can be iefeiied to in two ways both of which aie acceptabIe by the ASM-51. One way is to iefei to theii
addiesses, ie. 0 to 7FH. The othei way is with iefeience to bytes 20H to 2FH. Thus, bits 07 can aIso be iefeiied to
as bits 20.020.7, and bits 8-FH aie the same as 21.021.7 and so on.
Fach of the 16 bytes in this segment can aIso be addiessed as a byte.
3 Scratch Pad Area Bytes 30H thiough 7FH aie avaiIabIe to the usei as data RAM. Howevei, if the stack pointei
has been initiaIized to this aiea, enough numbei of bytes shouId be Ieft aside to pievent SP data destiuction.
4
Figuie 4 shows the diffeient segments of the on-chip RAM.
2702495
Figure 4 128 Bytes of RAM Direct and Indirect Addressable
5
SPECIAL FUNCTION REGISTERS
TabIe 1 contains a Iist of aII the SFRs and theii addiesses.
Compaiing TabIe 1 and Figuie 5 shows that aII of the SFRs that aie byte and bit addiessabIe aie Iocated on the fiist
coIumn of the diagiam in Figuie 5.
Table 1
Symbol Name Address
ACC Accumulator 0E0H
B B Register 0F0H
PSW Program Status Word 0D0H
SP Stack Pointer 81H
DPTR Data Pointer 2 Bytes
DPL Low Byte 82H
DPH High Byte 83H
P0 Port 0 80H
P1 Port 1 90H
P2 Port 2 0A0H
P3 Port 3 0B0H
IP Interrupt Priority Control 0B8H
IE Interrupt Enable Control 0A8H
TMOD TimerCounter Mode Control 89H
TCON TimerCounter Control 88H
aT2CON TimerCounter 2 Control 0C8H
TH0 TimerCounter 0 High Byte 8CH
TL0 TimerCounter 0 Low Byte 8AH
TH1 TimerCounter 1 High Byte 8DH
TL1 TimerCounter 1 Low Byte 8BH
aTH2 TimerCounter 2 High Byte 0CDH
aTL2 TimerCounter 2 Low Byte 0CCH
aRCAP2H TC 2 Capture Reg High Byte 0CBH
aRCAP2L TC 2 Capture Reg Low Byte 0CAH
SCON Serial Control 98H
SBUF Serial Data Buffer 99H
PCON Power Control 87H
e Bit addressable
a e 8052 only
6
WHAT DO THE SFRs CONTAIN JUST AFTER POWER-ON OR A RESET
TabIe 2 Iists the contents of each SFR aftei powei-on oi a haidwaie ieset.
Table 2 Contents of the SFRs after reset
Register Value in Binary
ACC 00000000
B 00000000
PSW 00000000
SP 00000111
DPTR
DPH 00000000
DPL 00000000
P0 11111111
P1 11111111
P2 11111111
P3 11111111
IP 8051 XXX00000
8052 XX000000
IE 8051 0XX00000
8052 0X000000
TMOD 00000000
TCON 00000000
aT2CON 00000000
TH0 00000000
TL0 00000000
TH1 00000000
TL1 00000000
aTH2 00000000
aTL2 00000000
aRCAP2H 00000000
aRCAP2L 00000000
SCON 00000000
SBUF Indeterminate
PCON HMOS 0XXXXXXX
CHMOS 0XXX0000
X e Undefined
e Bit Addressable
a e 8052 only
7
SFR MEMORY MAP
8 Bytes
F8 FF
F0 B F7
E8 EF
E0 ACC E7
D8 DF
D0 PSW D7
C8 T2CON RCAP2L RCAP2H TL2 TH2 CF
C0 C7
B8 IP BF
B0 P3 B7
A8 IE AF
A0 P2 A7
98 SCON SBUF 9F
90 P1 97
88 TCON TMOD TL0 TL1 TH0 TH1 8F
80 P0 SP DPL DPH PCON 87
Figure 5 u
Bit
Addressable
8
Those SFRs that have theii bits assigned foi vaiious functions aie Iisted in this section. A biief desciiption of each bit
is piovided foi quick iefeience. Foi moie detaiIed infoimation iefei to the Aichitectuie Chaptei of this book.
PSW PROGRAM STATUS WORD BIT ADDRESSABLE
CY AC F0 RS1 RS0 OV P
CY PSW.7 Caiiy FIag.
AC PSW.6 AuxiIiaiy Caiiy FIag.
F0 PSW.5 FIag 0 avaiIabIe to the usei foi geneiaI puipose.
RS1 PSW.4 Registei Bank seIectoi bit 1 (SFF NOTF 1).
RS0 PSW.3 Registei Bank seIectoi bit 0 (SFF NOTF 1).
OV PSW.2 OveifIow FIag.
- PSW.1 Usei definabIe fIag.
P PSW.0 Paiity fIag. Set/cIeaied by haidwaie each instiuction cycIe to indicate an odd/even numbei of
1 bits in the accumuIatoi.
NOTE
1 The value presented by RS0 and RS1 selects the corresponding register bank
RS1 RS0 Register Bank Address
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH
PCON POWER CONTROL REGISTER NOT BIT ADDRESSABLE
SMOD GF1 GF0 PD IDL
SMOD DoubIe baud iate bit. If Timei 1 is used to geneiate baud iate and SMOD
e
1, the baud iate is doubIed
when the SeiiaI Poit is used in modes 1, 2, oi 3.
- Not impIemented, ieseived foi futuie use.
OF1 OeneiaI puipose fIag bit.
OF0 OeneiaI puipose fIag bit.
PD Powei Down bit. Setting this bit activates Powei Down opeiation in the 80C51BH. (AvaiIabIe onIy in
CHMOS).
IDL IdIe Mode bit. Setting this bit activates IdIe Mode opeiation in the 80C51BH. (AvaiIabIe onIy in CHMOS).
If 1s aie wiitten to PD and IDL at the same time, PD takes piecedence.
User software should not write 1s to reserved bits These bits may be used in future MCS-51 products to invoke new
features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1
9
INTERRUPTS
In oidei to use any of the inteiiupts in the MCS-51, the foIIowing thiee steps must be taken.
1. Set the FA (enabIe aII) bit in the IF iegistei to 1.
2. Set the coiiesponding individuaI inteiiupt enabIe bit in the IF iegistei to 1.
3. Begin the inteiiupt seivice ioutine at the coiiesponding Vectoi Addiess of that inteiiupt. See TabIe beIow.
Interrupt Vector
Source Address
IE0 0003H
TF0 000BH
IE1 0013H
TF1 001BH
RI TI 0023H
TF2 EXF2 002BH
In addition, foi exteinaI inteiiupts, pins INT0 and INT1 (P3.2 and P3.3) must be set to 1, and depending on whethei
the inteiiupt is to be IeveI oi tiansition activated, bits IT0 oi IT1 in the TCON iegistei may need to be set to 1.
ITx e 0 level activated
ITx e 1 transition activated
IE INTERRUPT ENABLE REGISTER BIT ADDRESSABLE
If the bit is 0, the coiiesponding inteiiupt is disabIed. If the bit is 1, the coiiesponding inteiiupt is enabIed.
EA ET2 ES ET1 EX1 ET0 EX0
FA IF.7 DisabIes aII inteiiupts. If FA
e
0, no inteiiupt wiII be acknowIedged. If FA
e
1, each inteiiupt
souice is individuaIIy enabIed oi disabIed by setting oi cIeaiing its enabIe bit.
- IF.6 Not impIemented, ieseived foi futuie use.
FT2 IF.5 FnabIe oi disabIe the Timei 2 oveifIow oi captuie inteiiupt (8052 onIy).
FS IF.4 FnabIe oi disabIe the seiiaI poit inteiiupt.
FT1 IF.3 FnabIe oi disabIe the Timei 1 oveifIow inteiiupt.
FX1 IF.2 FnabIe oi disabIe FxteinaI Inteiiupt 1.
FT0 IF.1 FnabIe oi disabIe the Timei 0 oveifIow inteiiupt.
FX0 IF.0 FnabIe oi disabIe FxteinaI Inteiiupt 0.
Usei softwaie shouId not wiite 1s to ieseived bits. These bits may be used in futuie MCS-51 pioducts to invoke
new featuies. In that case, the ieset oi inactive vaIue of the new bit wiII be 0, and its active vaIue wiII be 1.
10
ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS
In oidei to assign highei piioiity to an inteiiupt the coiiesponding bit in the IP iegistei must be set to 1.
Remembei that whiIe an inteiiupt seivice is in piogiess, it cannot be inteiiupted by a Iowei oi same IeveI inteiiupt.
PRIORITY WITHIN LEVEL
Piioiity within IeveI is onIy to iesoIve simuItaneous iequests of the same piioiity IeveI.
Fiom high to Iow, inteiiupt souices aie Iisted beIow:
IF0
TF0
IF1
TF1
RI oi TI
TF2 oi FXF2
IP INTERRUPT PRIORITY REGISTER BIT ADDRESSABLE
If the bit is 0, the coiiesponding inteiiupt has a Iowei piioiity and if the bit is 1 the coiiesponding inteiiupt has a
highei piioiity.
PT2 PS PT1 PX1 PT0 PX0
- IP. 7 Not impIemented, ieseived foi futuie use.
- IP. 6 Not impIemented, ieseived foi futuie use.
PT2 IP. 5 Defines the Timei 2 inteiiupt piioiity IeveI (8052 onIy).
PS IP. 4 Defines the SeiiaI Poit inteiiupt piioiity IeveI.
PT1 IP. 3 Defines the Timei 1 inteiiupt piioiity IeveI.
PX1 IP. 2 Defines FxteinaI Inteiiupt 1 piioiity IeveI.
PT0 IP. 1 Defines the Timei 0 inteiiupt piioiity IeveI.
PX0 IP. 0 Defines the FxteinaI Inteiiupt 0 piioiity IeveI.
Usei softwaie shouId not wiite 1s to ieseived bits. These bits may be used in futuie MCS-51 pioducts to invoke
new featuies. In that case, the ieset oi inactive vaIue of the new bit wiII be 0, and its active vaIue wiII be 1.
11
TCON TIMERCOUNTER CONTROL REGISTER BIT ADDRESSABLE
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TF1 TCON. 7 Timei 1 oveifIow fIag. Set by haidwaie when the Timei/Countei 1 oveifIows. CIeaied by haid-
waie as piocessoi vectois to the inteiiupt seivice ioutine.
TR1 TCON. 6 Timei 1 iun contioI bit. Set/cIeaied by softwaie to tuin Timei/Countei 1 ON/OFF.
TF0 TCON. 5 Timei 0 oveifIow fIag. Set by haidwaie when the Timei/Countei 0 oveifIows. CIeaied by haid-
waie as piocessoi vectois to the seivice ioutine.
TR0 TCON. 4 Timei 0 iun contioI bit. Set/cIeaied by softwaie to tuin Timei/Countei 0 ON/OFF.
IF1 TCON. 3 FxteinaI Inteiiupt 1 edge fIag. Set by haidwaie when FxteinaI Inteiiupt edge is detected.
CIeaied by haidwaie when inteiiupt is piocessed.
IT1 TCON. 2 Inteiiupt 1 type contioI bit. Set/cIeaied by softwaie to specify faIIing edge/Iow IeveI tiiggeied
FxteinaI Inteiiupt.
IF0 TCON. 1 FxteinaI Inteiiupt 0 edge fIag. Set by haidwaie when FxteinaI Inteiiupt edge detected. CIeaied
by haidwaie when inteiiupt is piocessed.
IT0 TCON. 0 Inteiiupt 0 type contioI bit. Set/cIeaied by softwaie to specify faIIing edge/Iow IeveI tiiggeied
FxteinaI Inteiiupt.
TMOD TIMERCOUNTER MODE CONTROL REGISTER NOT BIT
ADDRESSABLE
GATE CT M1 M0 GATE CT M1 M0
X Y X Y
TIMFR 1 TIMFR 0
OATF When TRx (in TCON) is set and OATF
e
1, TIMFR/COUNTFRx wiII iun onIy whiIe INTx pin is high
(haidwaie contioI). When OATF
e
0, TIMFR/COUNTFRx wiII iun onIy whiIe TRx
e
1 (softwaie
contioI).
C/T Timei oi Countei seIectoi. CIeaied foi Timei opeiation (input fiom inteinaI system cIock). Set foi Coun-
tei opeiation (input fiom Tx input pin).
M1 Mode seIectoi bit. (NOTF 1)
M0 Mode seIectoi bit. (NOTF 1)
NOTE 1
M1 M0 Operating Mode
0 0 0 13-bit Timer (MCS-48 compatible)
0 1 1 16-bit TimerCounter
1 0 2 8-bit Auto-Reload TimerCounter
1 1 3 (Timer 0) TL0 is an 8-bit TimerCounter controlled by the standard Timer 0
control bits TH0 is an 8-bit Timer and is controlled by Timer 1 control bits
1 1 3 (Timer 1) TimerCounter 1 stopped
12
TIMER SET-UP
TabIes 3 thiough 6 give some vaIues foi TMOD which can be used to set up Timei 0 in diffeient modes.
It is assumed that onIy one timei is being used at a time. If it is desiied to iun Timeis 0 and 1 simuItaneousIy, in any
mode, the vaIue in TMOD foi Timei 0 must be ORed with the vaIue shown foi Timei 1 (TabIes 5 and 6).
Foi exampIe, if it is desiied to iun Timei 0 in mode 1 OATF (exteinaI contioI), and Timei 1 in mode 2 COUNTFR,
then the vaIue that must be Ioaded into TMOD is 69H (09H fiom TabIe 3 ORed with 60H fiom TabIe 6).
Moieovei, it is assumed that the usei, at this point, is not ieady to tuin the timeis on and wiII do that at a diffeient
point in the piogiam by setting bit TRx (in TCON) to 1.
TIMERCOUNTER 0
As a Timer
Table 3
TMOD
MODE
TIMER 0
INTERNAL EXTERNAL
FUNCTION
CONTROL CONTROL
(NOTE 1) (NOTE 2)
0 13-bit Timer 00H 08H
2 8-bit Auto-Reload 02H 0AH
3 two 8-bit Timers 03H 0BH
As a Counter
Table 4
TMOD
MODE
COUNTER 0
INTERNAL EXTERNAL
FUNCTION
CONTROL CONTROL
(NOTE 1) (NOTE 2)
0 13-bit Timer 04H 0CH
1 16-bit Timer 05H 0DH
2 8-bit Auto-Reload 06H 0EH
3 one 8-bit Counter 07H 0FH
NOTES
1 The Timer is turned ONOFF by settingclearing bit TR0 in the software
2 The Timer is turned ONOFF by the 1 to 0 transition on INT0 (P32) when TR0 e 1
(hardware control)
13
TIMERCOUNTER 1
As a Timer
Table 5
TMOD
MODE
TIMER 1
INTERNAL EXTERNAL
FUNCTION
CONTROL CONTROL
(NOTE 1) (NOTE 2)
2 8-bit Auto-Reload 20H A0H
3 does not run 30H B0H
As a Counter
Table 6
TMOD
MODE
COUNTER 1
INTERNAL EXTERNAL
FUNCTION
CONTROL CONTROL
(NOTE 1) (NOTE 2)
0 13-bit Timer 40H C0H
1 16-bit Timer 50H D0H
2 8-bit Auto-Reload 60H E0H
3 not available
NOTES
1 The Timer is turned ONOFF by settingclearing bit TR1 in the software
2 The Timer is turned ONOFF by the 1 to 0 transition on INT1 (P33) when TR1 e 1
(hardware control)
14
T2CON TIMERCOUNTER 2 CONTROL REGISTER BIT ADDRESSABLE
8052 Only
TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2
TF2 T2CON. 7 Timei 2 oveifIow fIag set by haidwaie and cIeaied by softwaie. TF2 cannot be set when
eithei RCLK
e
1 oi CLK
e
1
FXF2 T2CON. 6 Timei 2 exteinaI fIag set when eithei a captuie oi ieIoad is caused by a negative tiansition on
T2FX, and FXFN2
e
1. When Timei 2 inteiiupt is enabIed, FXF2
e
1 wiII cause the CPU
to vectoi to the Timei 2 inteiiupt ioutine. FXF2 must be cIeaied by softwaie.
RCLK T2CON. 5 Receive cIock fIag. When set, causes the SeiiaI Poit to use Timei 2 oveifIow puIses foi its
ieceive cIock in modes 1 & 3. RCLK
e
0 causes Timei 1 oveifIow to be used foi the ieceive
cIock.
TLCK T2CON. 4 Tiansmit cIock fIag. When set, causes the SeiiaI Poit to use Timei 2 oveifIow puIses foi its
tiansmit cIock in modes 1 & 3. TCLK
e
0 causes Timei 1 oveifIows to be used foi the
tiansmit cIock.
FXFN2 T2CON. 3 Timei 2 exteinaI enabIe fIag. When set, aIIows a captuie oi ieIoad to occui as a iesuIt of
negative tiansition on T2FX if Timei 2 is not being used to cIock the SeiiaI Poit.
FXFN2
e
0 causes Timei 2 to ignoie events at T2FX.
TR2 T2CON. 2 Softwaie START/STOP contioI foi Timei 2. A Iogic 1 staits the Timei.
C/T2 T2CON. 1 Timei oi Countei seIect.
0
e
InteinaI Timei. 1
e
FxteinaI Fvent Countei (faIIing edge tiiggeied).
CP/RL2 T2CON. 0 Captuie/ReIoad fIag. When set, captuies wiII occui on negative tiansitions at T2FX if
FXFN2
e
1. When cIeaied, Auto-ReIoads wiII occui eithei with Timei 2 oveifIows oi
negative tiansitions at T2FX when FXFN2
e
1. When eithei RCLK
e
1 oi TCLK
e
1,
this bit is ignoied and the Timei is foiced to Auto-ReIoad on Timei 2 oveifIow.
15
TIMERCOUNTER 2 SET-UP
Fxcept foi the baud iate geneiatoi mode, the vaIues given foi T2CON do not incIude the setting of the TR2 bit.
Theiefoie, bit TR2 must be set, sepaiateIy, to tuin the Timei on.
As a Timer
Table 7
T2CON
MODE
INTERNAL EXTERNAL
CONTROL CONTROL
(NOTE 1) (NOTE 2)
16-bit Auto-Reload 00H 08H
16-bit Capture 01H 09H
BAUD rate generator receive
transmit same baud rate 34H 36H
receive only 24H 26H
transmit only 14H 16H
As a Counter
Table 8
TMOD
MODE
INTERNAL EXTERNAL
CONTROL CONTROL
(NOTE 1) (NOTE 2)
16-bit Auto-Reload 02H 0AH
16-bit Capture 03H 0BH
NOTES
1 CaptureReload occurs only on TimerCounter overflow
2 CaptureReload occurs on TimerCounter overflow and a 1 to 0 transition on T2EX
(P11) pin except when Timer 2 is used in the baud rate generating mode
16
SCON SERIAL PORT CONTROL REGISTER BIT ADDRESSABLE
SM0 SM1 SM2 REN TB8 RB8 TI RI
SM0 SCON. 7 SeiiaI Poit mode specifiei. (NOTF 1).
SM1 SCON. 6 SeiiaI Poit mode specifiei. (NOTF 1).
SM2 SCON. 5 FnabIes the muItipiocessoi communication featuie in modes 2 & 3. In mode 2 oi 3, if SM2 is set
to 1 then RI wiII not be activated if the ieceived 9th data bit (RB8) is 0. In mode 1, if SM2
e
1
then RI wiII not be activated if a vaIid stop bit was not ieceived. In mode 0, SM2 shouId be 0.
(See TabIe 9).
RFN SCON. 4 Set/CIeaied by softwaie to FnabIe/DisabIe ieception.
TB8 SCON. 3 The 9th bit that wiII be tiansmitted in modes 2 & 3. Set/CIeaied by softwaie.
RB8 SCON. 2 In modes 2 & 3, is the 9th data bit that was ieceived. In mode 1, if SM2
e
0, RB8 is the stop bit
that was ieceived. In mode 0, RB8 is not used.
TI SCON. 1 Tiansmit inteiiupt fIag. Set by haidwaie at the end of the 8th bit time in mode 0, oi at the
beginning of the stop bit in the othei modes. Must be cIeaied by softwaie.
RI SCON. 0 Receive inteiiupt fIag. Set by haidwaie at the end of the 8th bit time in mode 0, oi haIfway
thiough the stop bit time in the othei modes (except see SM2). Must be cIeaied by softwaie.
NOTE 1
SM0 SM1 Mode Description Baud Rate
0 0 0 SHIFT REGISTER Fosc12
0 1 1 8-Bit UART Variable
1 0 2 9-Bit UART Fosc64 OR
Fosc32
1 1 3 9-Bit UART Variable
SERIAL PORT SET-UP
Table 9
MODE SCON SM2 VARIATION
0 10H
Single Processor
1 50H
Environment
2 90H
(SM2
e
0)
3 D0H
0 NA
Multiprocessor
1 70H
Environment
2 B0H
(SM2
e
1)
3 F0H
GENERATING BAUD RATES
Serial Port in Mode 0
Mode 0 has a fixed baud iate which is 1/12 of the osciIIatoi fiequency. To iun the seiiaI poit in this mode none of
the Timei/Counteis need to be set up. OnIy the SCON iegistei needs to be defined.
Baud Rate
e
Osc Fieq
12
Serial Port in Mode 1
Mode 1 has a vaiiabIe baud iate. The baud iate can be geneiated by eithei Timei 1 oi Timei 2 (8052 onIy).
17
USING TIMERCOUNTER 1 TO GENERATE BAUD RATES
Foi this puipose, Timei 1 is used in mode 2 (Auto-ReIoad). Refei to Timei Setup section of this chaptei.
Baud Rate e
K x Oscillator Freq
32 x 12 x 256 b (TH1)
If SMOD
e
0, then K
e
1.
If SMOD
e
1, then K
e
2. (SMOD is the PCON iegistei).
Most of the time the usei knows the baud iate and needs to know the ieIoad vaIue foi TH1.
Theiefoie, the equation to caIcuIate TH1 can be wiitten as:
TH1 e 256 b
K x Osc Freq
384 x baud rate
TH1 must be an integei vaIue. Rounding off TH1 to the neaiest integei may not pioduce the desiied baud iate. In
this case, the usei may have to choose anothei ciystaI fiequency.
Since the PCON iegistei is not bit addiessabIe, one way to set the bit is IogicaI ORing the PCON iegistei. (ie, ORL
PCON,80H). The addiess of PCON is 87H.
USING TIMERCOUNTER 2 TO GENERATE BAUD RATES
Foi this puipose, Timei 2 must be used in the baud iate geneiating mode. Refei to Timei 2 Setup TabIe in this
chaptei. If Timei 2 is being cIocked thiough pin T2 (P1.0) the baud iate is:
Baud Rate e
Timer 2 Overflow Rate
16
And if it is being cIocked inteinaIIy the baud iate is:
Baud Rate e
Osc Freq
32 x 65536 b (RCAP2H RCAP2L)
To obtain the ieIoad vaIue foi RCAP2H and RCAP2L the above equation can be iewiitten as:
RCAP2H RCAP2L e 65536 b
Osc Freq
32 x Baud Rate
SERIAL PORT IN MODE 2
The baud iate is fixed in this mode and is oi of the osciIIatoi fiequency depending on the vaIue of the SMOD
bit in the PCON iegistei.
In this mode none of the Timeis aie used and the cIock comes fiom the inteinaI phase 2 cIock.
SMOD
e
1, Baud Rate
e
Osc Fieq.
SMOD
e
0, Baud Rate
e
Osc Fieq.
To set the SMOD bit: ORL PCON,80H. The addiess of PCON is 87H.
SERIAL PORT IN MODE 3
The baud iate in mode 3 is vaiiabIe and sets up exactIy the same as in mode 1.
18
MCS-51 INSTRUCTION SET
Table 10 8051 Instruction Set Summary
Inteiiupt Response Time: Refei to Haidwaie De-
sciiption Chaptei.
Instructions that Affect Flag Settings
(1)
Instruction Flag Instruction Flag
C OV AC C OV AC
ADD X X X CLR C O
ADDC X X X CPL C X
SUBB X X X ANL Cbit X
MUL O X ANL Cbit X
DIV O X ORL Cbit X
DA X ORL Cbit X
RRC X MOV Cbit X
RLC X CJNE X
SETB C 1
(1)
Note that opeiations on SFR byte addiess 208 oi
bit addiesses 209-215 (i.e., the PSW oi bits in the
PSW) wiII aIso affect fIag settings.
Note on instruction set and addressing modes
Rn - Registei R7R0 of the cuiientIy se-
Iected Registei Bank.
diiect - 8-bit inteinaI data Iocations addiess.
This couId be an InteinaI Data RAM
Iocation (0127) oi a SFR i.e., I/O
poit, contioI iegistei, status iegistei,
etc. (128255).
Ri - 8-bit inteinaI data RAM Iocation (0

255) addiessed indiiectIy thiough ieg-
istei R1 oi R0.
data - 8-bit constant incIuded in instiuction.
data 16 - 16-bit constant incIuded in instiuction.
addi 16 - 16-bit destination addiess. Used by
LCALL & LJMP. A bianch can be
anywheie within the 64K-byte Pio-
giam Memoiy addiess space.
addi 11 - 11-bit destination addiess. Used by
ACALL & AJMP. The bianch wiII be
within the same 2K-byte page of pio-
giam memoiy as the fiist byte of the
foIIowing instiuction.
ieI - Signed (twos compIement) 8-bit offset
byte. Used by SJMP and aII condition-
aI jumps. Range is
b
128 to
a
127
bytes ieIative to fiist byte of the foI-
Iowing instiuction.
bit - Diiect Addiessed bit in InteinaI Data
RAM oi SpeciaI Function Registei.
Mnemonic Description Byte
Oscillator
Period
ARITHMETIC OPERATIONS
ADD ARn Add register to 1 12
Accumulator
ADD Adirect Add direct byte to 2 12
Accumulator
ADD A
Ri Add indirect RAM 1 12

to Accumulator
ADD Adata Add immediate 2 12
data to
Accumulator
ADDC ARn Add register to 1 12
Accumulator
with Carry
ADDC Adirect Add direct byte to 2 12
Accumulator
with Carry
ADDC A
Ri Add indirect 1 12
RAM to
Accumulator
with Carry
ADDC Adata Add immediate 2 12
data to Acc
with Carry
SUBB ARn Subtract Register 1 12
from Acc with
borrow
SUBB Adirect Subtract direct 2 12
byte from Acc
with borrow
SUBB A
Ri Subtract indirect 1 12
RAM from ACC
with borrow
SUBB Adata Subtract 2 12
immediate data
from Acc with
borrow
INC A Increment 1 12
Accumulator
INC Rn Increment register 1 12
INC direct Increment direct 2 12
byte
INC

Ri Increment direct 1 12
RAM
DEC A Decrement 1 12
Accumulator
DEC Rn Decrement 1 12
Register
DEC direct Decrement direct 2 12
byte
DEC

Ri Decrement 1 12
indirect RAM
All mnemonics copyrighted Intel Corporation 1980
19
Table 10 8051 Instruction Set Summary (Continued)
Oscillator
Period
ARITHMETIC OPERATIONS (Continued)
INC DPTR Increment Data 1 24
Pointer
MUL AB Multiply A B 1 48
DIV AB Divide A by B 1 48
DA A Decimal Adjust 1 12
Accumulator
LOGICAL OPERATIONS
ANL ARn AND Register to 1 12
Accumulator
ANL Adirect AND direct byte 2 12
to Accumulator
ANL A
Ri AND indirect 1 12
RAM to
Accumulator
ANL Adata AND immediate 2 12
data to
Accumulator
ANL directA AND Accumulator 2 12
to direct byte
ANL directdata AND immediate 3 24
data to direct byte
ORL ARn OR register to 1 12
Accumulator
ORL Adirect OR direct byte to 2 12
Accumulator
ORL A
Ri OR indirect RAM 1 12
to Accumulator
ORL Adata OR immediate 2 12
data to
Accumulator
ORL directA OR Accumulator 2 12
to direct byte
ORL directdata OR immediate 3 24
data to direct byte
XRL ARn Exclusive-OR 1 12
register to
Accumulator
XRL Adirect Exclusive-OR 2 12
direct byte to
Accumulator
XRL A
Ri Exclusive-OR 1 12
indirect RAM to
Accumulator
XRL Adata Exclusive-OR 2 12
immediate data to
Accumulator
XRL directA Exclusive-OR 2 12
Accumulator to
direct byte
XRL directdata Exclusive-OR 3 24
immediate data
to direct byte
CLR A Clear 1 12
Accumulator
CPL A Complement 1 12
Accumulator
Oscillator
Period
LOGICAL OPERATIONS (Continued)
RL A Rotate 1 12
Accumulator Left
RLC A Rotate 1 12
Accumulator Left
through the Carry
RR A Rotate 1 12
Accumulator
Right
RRC A Rotate 1 12
Accumulator
Right through
the Carry
SWAP A Swap nibbles 1 12
within the
Accumulator
DATA TRANSFER
MOV ARn Move 1 12
register to
Accumulator
MOV Adirect Move direct 2 12
byte to
Accumulator
MOV A
Ri Move indirect 1 12
RAM to
Accumulator
MOV Adata Move 2 12
immediate
data to
Accumulator
MOV RnA Move 1 12
Accumulator
to register
MOV Rndirect Move direct 2 24
byte to
register
MOV Rndata Move 2 12
immediate data
to register
MOV directA Move 2 12
Accumulator
to direct byte
MOV directRn Move register 2 24
to direct byte
MOV directdirect Move direct 3 24
byte to direct
MOV direct
Ri Move indirect 2 24
RAM to
direct byte
MOV directdata Move 3 24
immediate data
to direct byte
MOV

RiA Move 1 12
Accumulator to
indirect RAM
20
Oscillator
Period
DATA TRANSFER (Continued)
MOV

Ridirect Move direct 2 24
byte to
indirect RAM
MOV

Ridata Move 2 12
immediate
data to
indirect RAM
MOV DPTRdata16 Load Data 3 24
Pointer with a
16-bit constant
MOVC A
AaDPTR Move Code 1 24

byte relative to
DPTR to Acc
MOVC A
AaPC Move Code 1 24

byte relative to
PC to Acc
MOVX A
Ri Move 1 24
External
RAM (8-bit
addr) to Acc
MOVX A
DPTR Move 1 24
External
RAM (16-bit
addr) to Acc
MOVX

RiA Move Acc to 1 24
External RAM
(8-bit addr)
MOVX

DPTRA Move Acc to 1 24
External RAM
(16-bit addr)
PUSH direct Push direct 2 24
byte onto
stack
POP direct Pop direct 2 24
byte from
stack
XCH ARn Exchange 1 12
register with
Accumulator
XCH Adirect Exchange 2 12
direct byte
with
Accumulator
XCH A
Ri Exchange 1 12
indirect RAM
with
Accumulator
XCHD A
Ri Exchange low- 1 12
order Digit
indirect RAM
with Acc
Oscillator
Period
BOOLEAN VARIABLE MANIPULATION
CLR C Clear Carry 1 12
CLR bit Clear direct bit 2 12
SETB C Set Carry 1 12
SETB bit Set direct bit 2 12
CPL C Complement 1 12
Carry
CPL bit Complement 2 12
direct bit
ANL Cbit AND direct bit 2 24
to CARRY
ANL Cbit AND complement 2 24
of direct bit
to Carry
ORL Cbit OR direct bit 2 24
to Carry
ORL Cbit OR complement 2 24
of direct bit
to Carry
MOV Cbit Move direct bit 2 12
to Carry
MOV bitC Move Carry to 2 24
direct bit
JC rel Jump if Carry 2 24
is set
JNC rel Jump if Carry 2 24
not set
JB bitrel Jump if direct 3 24
Bit is set
JNB bitrel Jump if direct 3 24
Bit is Not set
JBC bitrel Jump if direct 3 24
Bit is set
clear bit
PROGRAM BRANCHING
ACALL addr11 Absolute 2 24
Subroutine
Call
LCALL addr16 Long 3 24
Subroutine
Call
RET Return from 1 24
Subroutine
RETI Return from 1 24
interrupt
AJMP addr11 Absolute 2 24
Jump
LJMP addr16 Long Jump 3 24
SJMP rel Short Jump 2 24
(relative addr)
21
Oscillator
Period
PROGRAM BRANCHING (Continued)
JMP

AaDPTR Jump indirect 1 24
relative to the
DPTR
JZ rel Jump if 2 24
Accumulator
is Zero
JNZ rel Jump if 2 24
Accumulator
is Not Zero
CJNE Adirectrel Compare 3 24
direct byte to
Acc and Jump
if Not Equal
CJNE Adatarel Compare 3 24
immediate to
Acc and Jump
if Not Equal
Oscillator
Period
PROGRAM BRANCHING (Continued)
CJNE Rndatarel Compare 3 24
immediate to
register and
Jump if Not
Equal
CJNE

Ridatarel Compare 3 24
immediate to
indirect and
Jump if Not
Equal
DJNZ Rnrel Decrement 2 24
register and
Jump if Not
Zero
DJNZ directrel Decrement 3 24
direct byte
and Jump if
Not Zero
NOP No Operation 1 12
22
Table 11 Instruction Opcodes in Hexadecimal Order
Hex Number
Mnemonic Operands
Code of Bytes
00 1 NOP
01 2 AJMP code addr
02 3 LJMP code addr
03 1 RR A
04 1 INC A
05 2 INC data addr
06 1 INC

R0
07 1 INC

R1
08 1 INC R0
09 1 INC R1
0A 1 INC R2
0B 1 INC R3
0C 1 INC R4
0D 1 INC R5
0E 1 INC R6
0F 1 INC R7
10 3 JBC bit addr code addr
11 2 ACALL code addr
12 3 LCALL code addr
13 1 RRC A
14 1 DEC A
15 2 DEC data addr
16 1 DEC

R0
17 1 DEC

R1
18 1 DEC R0
19 1 DEC R1
1A 1 DEC R2
1B 1 DEC R3
1C 1 DEC R4
1D 1 DEC R5
1E 1 DEC R6
1F 1 DEC R7
20 3 JB bit addr code addr
21 2 AJMP code addr
22 1 RET
23 1 RL A
24 2 ADD Adata
25 2 ADD Adata addr
26 1 ADD A
R0
27 1 ADD A
R1
28 1 ADD AR0
29 1 ADD AR1
2A 1 ADD AR2
2B 1 ADD AR3
2C 1 ADD AR4
2D 1 ADD AR5
2E 1 ADD AR6
2F 1 ADD AR7
30 3 JNB bit addr code addr
32 1 RETI
Hex Number
Mnemonic Operands
Code of Bytes
33 1 RLC A
34 2 ADDC Adata
35 2 ADDC Adata addr
36 1 ADDC A
R0
37 1 ADDC A
R1
38 1 ADDC AR0
39 1 ADDC AR1
3A 1 ADDC AR2
3B 1 ADDC AR3
3C 1 ADDC AR4
3D 1 ADDC AR5
3E 1 ADDC AR6
3F 1 ADDC AR7
40 2 JC code addr
41 2 AJMP code addr
42 2 ORL data addrA
43 3 ORL data addrdata
44 2 ORL Adata
45 2 ORL Adata addr
46 1 ORL A
R0
47 1 ORL A
R1
48 1 ORL AR0
49 1 ORL AR1
4A 1 ORL AR2
4B 1 ORL AR3
4C 1 ORL AR4
4D 1 ORL AR5
4E 1 ORL AR6
4F 1 ORL AR7
50 2 JNC code addr
52 2 ANL data addrA
53 3 ANL data addrdata
54 2 ANL Adata
55 2 ANL Adata addr
56 1 ANL A
R0
57 1 ANL A
R1
58 1 ANL AR0
59 1 ANL AR1
5A 1 ANL AR2
5B 1 ANL AR3
5C 1 ANL AR4
5D 1 ANL AR5
5E 1 ANL AR6
5F 1 ANL AR7
60 2 JZ code addr
61 2 AJMP code addr
62 2 XRL data addrA
63 3 XRL data addrdata
64 2 XRL Adata
65 2 XRL Adata addr
23
Table 11 Instruction Opcodes in Hexadecimal Order (Continued)
Hex Number
Mnemonic Operands
Code of Bytes
66 1 XRL A
R0
67 1 XRL A
R1
68 1 XRL AR0
69 1 XRL AR1
6A 1 XRL AR2
6B 1 XRL AR3
6C 1 XRL AR4
6D 1 XRL AR5
6E 1 XRL AR6
6F 1 XRL AR7
70 2 JNZ code addr
72 2 ORL Cbit addr
73 1 JMP

AaDPTR
74 2 MOV Adata
75 3 MOV data addrdata
76 2 MOV

R0data
77 2 MOV

R1data
78 2 MOV R0data
79 2 MOV R1data
7A 2 MOV R2data
7B 2 MOV R3data
7C 2 MOV R4data
7D 2 MOV R5data
7E 2 MOV R6data
7F 2 MOV R7data
80 2 SJMP code addr
81 2 AJMP code addr
82 2 ANL Cbit addr
83 1 MOVC A
AaPC
84 1 DIV AB
85 3 MOV data addr data addr
86 2 MOV data addr
R0
87 2 MOV data addr
R1
88 2 MOV data addrR0
89 2 MOV data addrR1
8A 2 MOV data addrR2
8B 2 MOV data addrR3
8C 2 MOV data addrR4
8D 2 MOV data addrR5
8E 2 MOV data addrR6
8F 2 MOV data addrR7
90 3 MOV DPTRdata
92 2 MOV bit addrC
93 1 MOVC A
AaDPTR
94 2 SUBB Adata
95 2 SUBB Adata addr
96 1 SUBB A
R0
97 1 SUBB A
R1
98 1 SUBB AR0
Hex Number
Mnemonic Operands
Code of Bytes
99 1 SUBB AR1
9A 1 SUBB AR2
9B 1 SUBB AR3
9C 1 SUBB AR4
9D 1 SUBB AR5
9E 1 SUBB AR6
9F 1 SUBB AR7
A0 2 ORL Cbit addr
A1 2 AJMP code addr
A2 2 MOV Cbit addr
A3 1 INC DPTR
A4 1 MUL AB
A5 reserved
A6 2 MOV

R0data addr
A7 2 MOV

R1data addr
A8 2 MOV R0data addr
A9 2 MOV R1data addr
AA 2 MOV R2data addr
AB 2 MOV R3data addr
AC 2 MOV R4data addr
AD 2 MOV R5data addr
AE 2 MOV R6data addr
AF 2 MOV R7data addr
B0 2 ANL Cbit addr
B1 2 ACALL code addr
B2 2 CPL bit addr
B3 1 CPL C
B4 3 CJNE Adatacode addr
B5 3 CJNE Adata addrcode addr
B6 3 CJNE

R0datacode addr
B7 3 CJNE

R1datacode addr
B8 3 CJNE R0datacode addr
B9 3 CJNE R1datacode addr
BA 3 CJNE R2datacode addr
BB 3 CJNE R3datacode addr
BC 3 CJNE R4datacode addr
BD 3 CJNE R5datacode addr
BE 3 CJNE R6datacode addr
BF 3 CJNE R7datacode addr
C0 2 PUSH data addr
C1 2 AJMP code addr
C2 2 CLR bit addr
C3 1 CLR C
C4 1 SWAP A
C5 2 XCH Adata addr
C6 1 XCH A
R0
C7 1 XCH A
R1
C8 1 XCH AR0
C9 1 XCH AR1
CA 1 XCH AR2
CB 1 XCH AR3
24
Table 11 Instruction Opcodes in Hexadecimal Order (Continued)
Hex Number
Mnemonic Operands
Code of Bytes
CC 1 XCH AR4
CD 1 XCH AR5
CE 1 XCH AR6
CF 1 XCH AR7
D0 2 POP data addr
D1 2 ACALL code addr
D2 2 SETB bit addr
D3 1 SETB C
D4 1 DA A
D5 3 DJNZ data addrcode addr
D6 1 XCHD A
R0
D7 1 XCHD A
R1
D8 2 DJNZ R0code addr
D9 2 DJNZ R1code addr
DA 2 DJNZ R2code addr
DB 2 DJNZ R3code addr
DC 2 DJNZ R4code addr
DD 2 DJNZ R5code addr
DE 2 DJNZ R6code addr
DF 2 DJNZ R7code addr
E0 1 MOVX A
DPTR
E1 2 AJMP code addr
E2 1 MOVX A
R0
E3 1 MOVX A
R1
E4 1 CLR A
E5 2 MOV Adata addr
Hex Number
Mnemonic Operands
Code of Bytes
E6 1 MOV A
R0
E7 1 MOV A
R1
E8 1 MOV AR0
E9 1 MOV AR1
EA 1 MOV AR2
EB 1 MOV AR3
EC 1 MOV AR4
ED 1 MOV AR5
EE 1 MOV AR6
EF 1 MOV AR7
F0 1 MOVX

DPTRA
F1 2 ACALL code addr
F2 1 MOVX

R0A
F3 1 MOVX

R1A
F4 1 CPL A
F5 2 MOV data addrA
F6 1 MOV

R0A
F7 1 MOV

R1A
F8 1 MOV R0A
F9 1 MOV R1A
FA 1 MOV R2A
FB 1 MOV R3A
FC 1 MOV R4A
FD 1 MOV R5A
FE 1 MOV R6A
FF 1 MOV R7A
25
INSTRUCTION DEFINITIONS
ACALL addr11
Function AbsoIute CaII
Description ACALL unconditionaIIy caIIs a subioutine Iocated at the indicated addiess. The instiuction
inciements the PC twice to obtain the addiess of the foIIowing instiuction, then pushes the
16-bit iesuIt onto the stack (Iow-oidei byte fiist) and inciements the Stack Pointei twice. The
destination addiess is obtained by successiveIy concatenating the five high-oidei bits of the
inciemented PC, opcode bits 7-5, and the second byte of the instiuction. The subioutine caIIed
must theiefoie stait within the same 2K bIock of the piogiam memoiy as the fiist byte of the
instiuction foIIowing ACALL. No fIags aie affected.
Example InitiaIIy SP equaIs 07H. The IabeI SUBRTN is at piogiam memoiy Iocation 0345 H. Aftei
executing the instiuction,
ACALL SUBRTN
at Iocation 0123H, SP wiII contain 09H, inteinaI RAM Iocations 08H and 09H wiII contain
25H and 01H, iespectiveIy, and the PC wiII contain 0345H.
Bytes 2
Cycles 2
Encoding a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0
Operation ACALL
(PC)w(PC)
a
2
(SP)w(SP)
a
1
((SP))w(PC
7-0
)
(SP)w(SP)
a
1
((SP))w(PC
15-8
)
(PC
10-0
)wpage addiess
26
ADD A
k
src-byte
l
Function Add
Description ADD adds the byte vaiiabIe indicated to the AccumuIatoi, Ieaving the iesuIt in the AccumuIa-
toi. The caiiy and auxiIiaiy-caiiy fIags aie set, iespectiveIy, if theie is a caiiy-out fiom bit 7 oi
bit 3, and cIeaied otheiwise. When adding unsigned integeis, the caiiy fIag indicates an
oveifIow occuied.
OV is set if theie is a caiiy-out of bit 6 but not out of bit 7, oi a caiiy-out of bit 7 but not bit 6:
otheiwise OV is cIeaied. When adding signed integeis, OV indicates a negative numbei pio-
duced as the sum of two positive opeiands, oi a positive sum fiom two negative opeiands.
Foui souice opeiand addiessing modes aie aIIowed: iegistei, diiect, iegistei-indiiect, oi imme-
diate.
Example The AccumuIatoi hoIds 0C3H (11000011B) and iegistei 0 hoIds 0AAH (10101010B). The
instiuction,
ADD A,R0
wiII Ieave 6DH (01101101B) in the AccumuIatoi with the AC fIag cIeaied and both the caiiy
fIag and OV set to 1.
ADD ARn
Bytes 1
Cycles 1
Encoding 0 0 1 0 1 r r r
Operation ADD
(A)w(A)
a
(Rn)
ADD Adirect
Bytes 2
Cycles 1
Encoding 0 0 1 0 0 1 0 1 direct address
Operation ADD
(A)w(A)
a
(diiect)
27
ADD A
Ri
Bytes 1
Cycles 1
Encoding 0 0 1 0 0 1 1 i
Operation ADD
(A)w(A)
a
((R
i
))
ADD Adata
Bytes 2
Cycles 1
Encoding 0 0 1 0 0 1 0 0 immediate data
Operation ADD
(A)w(A)
a data
ADDC A
k
src-byte
l
Function Add with Caiiy
Description ADDC simuItaneousIy adds the byte vaiiabIe indicated, the caiiy fIag and the AccumuIatoi
contents, Ieaving the iesuIt in the AccumuIatoi. The caiiy and auxiIiaiy-caiiy fIags aie set,
iespectiveIy, if theie is a caiiy-out fiom bit 7 oi bit 3, and cIeaied otheiwise. When adding
unsigned integeis, the caiiy fIag indicates an oveifIow occuied.
OV is set if theie is a caiiy-out of bit 6 but not out of bit 7, oi a caiiy-out of bit 7 but not out of
bit 6: otheiwise OV is cIeaied. When adding signed integeis, OV indicates a negative numbei
pioduced as the sum of two positive opeiands oi a positive sum fiom two negative opeiands.
Foui souice opeiand addiessing modes aie aIIowed: iegistei, diiect, iegistei-indiiect, oi imme-
diate.
Example The AccumuIatoi hoIds 0C3H (11000011B) and iegistei 0 hoIds 0AAH (10101010B) with the
caiiy fIag set. The instiuction,
ADDC A,R0
wiII Ieave 6FH (01101110B) in the AccumuIatoi with AC cIeaied and both the Caiiy fIag and
OV set to 1.
28
ADDC ARn
Bytes 1
Cycles 1
Operation ADDC
(A)w(A)
a
(C)
a
(R
n
)
ADDC Adirect
Bytes 2
Cycles 1
Operation ADDC
(A)w(A)
a
(C)
a
(diiect)
ADDC A
Ri
Bytes 1
Cycles 1
Encoding 0 0 1 1 0 1 1 i
Operation ADDC
(A)w(A)
a
(C)
a
((R
i
))
ADDC Adata
Bytes 2
Cycles 1
Operation ADDC
(A)w(A)
a
(C)
a data
29
AJMP addr11
Function AbsoIute Jump
Description AJMP tiansfeis piogiam execution to the indicated addiess, which is foimed at iun-time by
concatenating the high-oidei five bits of the PC (after inciementing the PC twice), opcode bits
7-5, and the second byte of the instiuction. The destination must theiefoie be within the same
2K bIock of piogiam memoiy as the fiist byte of the instiuction foIIowing AJMP.
Example The IabeI JMPADR is at piogiam memoiy Iocation 0123H. The instiuction,
AJMP JMPADR
is at Iocation 0345H and wiII Ioad the PC with 0123H.
Bytes 2
Cycles 2
Encoding a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0
Operation AJMP
(PC)w(PC)
a
2
(PC
10-0
)wpage addiess
ANL
k
dest-byte
l
k
src-byte
l
Function LogicaI-AND foi byte vaiiabIes
Description ANL peifoims the bitwise IogicaI-AND opeiation between the vaiiabIes indicated and stoies
the iesuIts in the destination vaiiabIe. No fIags aie affected.
The two opeiands aIIow six addiessing mode combinations. When the destination is the Accu-
muIatoi, the souice can use iegistei, diiect, iegistei-indiiect, oi immediate addiessing: when
the destination is a diiect addiess, the souice can be the AccumuIatoi oi immediate data.
Note When this instiuction is used to modify an output poit, the vaIue used as the oiiginaI
poit data wiII be iead fiom the output data Iatch, not the input pins.
Example If the AccumuIatoi hoIds 0C3H (11000011B) and iegistei 0 hoIds 55H (01010101B) then the
instiuction,
ANL A,R0
wiII Ieave 41H (01000001B) in the AccumuIatoi.
When the destination is a diiectIy addiessed byte, this instiuction wiII cIeai combinations of
bits in any RAM Iocation oi haidwaie iegistei. The mask byte deteimining the pattein of bits
to be cIeaied wouId eithei be a constant contained in the instiuction oi a vaIue computed in
the AccumuIatoi at iun-time. The instiuction,
ANL P1,01110011B
wiII cIeai bits 7, 3, and 2 of output poit 1.
30
ANL ARn
Bytes 1
Cycles 1
Operation ANL
(A)w(A) (Rn)
ANL Adirect
Bytes 2
Cycles 1
Operation ANL
(A)w(A) (diiect)
ANL A
Ri
Bytes 1
Cycles 1
Encoding 0 1 0 1 0 1 1 i
Operation ANL
(A)w(A) ((Ri))
ANL Adata
Bytes 2
Cycles 1
Operation ANL
(A)w(A) data
ANL directA
Bytes 2
Cycles 1
Operation ANL
(diiect)w(diiect) (A)
31
ANL directdata
Bytes 3
Cycles 2
Encoding 0 1 0 1 0 0 1 1 direct address immediate data
Operation ANL
(diiect)w(diiect) data
ANL C
k
src-bit
l
Function LogicaI-AND foi bit vaiiabIes
Description If the BooIean vaIue of the souice bit is a IogicaI 0 then cIeai the caiiy fIag: otheiwise Ieave the
caiiy fIag in its cuiient state. A sIash (/) pieceding the opeiand in the assembIy Ianguage
indicates that the IogicaI compIement of the addiessed bit is used as the souice vaIue, but the
source bit itself is not affected No othei fIags aie affected.
OnIy diiect addiessing is aIIowed foi the souice opeiand.
Example Set the caiiy fIag if, and onIy if, P1.0
e
1, ACC. 7
e
1, and OV
e
0:
MOV C,P1.0 :LOAD CARRY WITH INPUT PIN STATF
ANL C,ACC.7 :AND CARRY WITH ACCUM. BIT 7
ANL C,/OV :AND WITH INVFRSF OF OVFRFLOW FLAO
ANL Cbit
Bytes 2
Cycles 2
Encoding 1 0 0 0 0 0 1 0 bit address
Operation ANL
(C)w(C) (bit)
ANL Cbit
Bytes 2
Cycles 2
Operation ANL
(C)w(C)
s
(bit)
32
CJNE
k
dest-byte
l
k
src-byte
l
rel
Function Compaie and Jump if Not FquaI.
Description CJNF compaies the magnitudes of the fiist two opeiands, and bianches if theii vaIues aie not
equaI. The bianch destination is computed by adding the signed ieIative-dispIacement in the
Iast instiuction byte to the PC, aftei inciementing the PC to the stait of the next instiuction.
The caiiy fIag is set if the unsigned integei vaIue of
k
dest-byte
l
is Iess than the unsigned
integei vaIue of
k
sic-byte
l
: otheiwise, the caiiy is cIeaied. Neithei opeiand is affected.
The fiist two opeiands aIIow foui addiessing mode combinations: the AccumuIatoi may be
compaied with any diiectIy addiessed byte oi immediate data, and any indiiect RAM Iocation
oi woiking iegistei can be compaied with an immediate constant.
Example The AccumuIatoi contains 34H. Registei 7 contains 56H. The fiist instiuction in the se-
quence,
CJNF R7,60H, NOT
-
FQ
: . . . . . . . . : R7
e
60H.
NOT
-
FQ: JC RFQ
-
LOW : IF R7
k
60H.
: . . . . . . . . : R7
l
60H.
sets the caiiy fIag and bianches to the instiuction at IabeI NOT
-
FQ. By testing the caiiy fIag,
this instiuction deteimines whethei R7 is gieatei oi Iess than 60H.
If the data being piesented to Poit 1 is aIso 34H, then the instiuction,
WAIT: CJNF A,P1,WAIT
cIeais the caiiy fIag and continues with the next instiuction in sequence, since the AccumuIa-
toi does equaI the data iead fiom P1. (If some othei vaIue was being input on P1, the piogiam
wiII Ioop at this point untiI the P1 data changes to 34H.)
CJNE Adirectrel
Bytes 3
Cycles 2
Encoding 1 0 1 1 0 1 0 1 direct address rel address
Operation (PC)w(PC)
a
3
IF (A)
kl
(direct)
THFN
(PC)w(PC)
a
relative offset
IF (A)
k
(direct)
THFN
(C)w1
FLSF
(C)w0
33
CJNE Adatarel
Bytes 3
Cycles 2
Encoding 1 0 1 1 0 1 0 0 immediate data rel address
Operation (PC)w(PC)
a
3
IF (A)
kl
data
THFN
(PC)w(PC)
a
relative offset
IF (A)
k
data
THFN
(C)w1
FLSF
(C)w0
CJNE Rndatarel
Bytes 3
Cycles 2
Encoding 1 0 1 1 1 r r r immediate data rel address
Operation (PC)w(PC)
a
3
IF (Rn)
kl
data
THFN
(PC)w(PC)
a
relative offset
IF (Rn)
k
data
THFN
(C)w1
FLSF
(C)w0
CJNE

Ridatarel
Bytes 3
Cycles 2
Encoding 1 0 1 1 0 1 1 i immediate data rel address
Operation (PC)w(PC)
a
3
IF ((Ri))
kl
data
THFN
(PC)w(PC)
a
relative offset
IF ((Ri))
k
data
THFN
(C)w1
FLSF
(C)w0
34
CLR A
Function CIeai AccumuIatoi
Description The AccumuIatoi is cIeaied (aII bits set on zeio). No fIags aie affected.
Example The AccumuIatoi contains 5CH (01011100B). The instiuction,
CLR A
wiII Ieave the AccumuIatoi set to 00H (00000000B).
Bytes 1
Cycles 1
Encoding 1 1 1 0 0 1 0 0
Operation CLR
(A)w0
CLR bit
Function CIeai bit
Description The indicated bit is cIeaied (ieset to zeio). No othei fIags aie affected. CLR can opeiate on the
caiiy fIag oi any diiectIy addiessabIe bit.
Example Poit 1 has pieviousIy been wiitten with 5DH (01011101B). The instiuction,
CLR P1.2
wiII Ieave the poit set to 59H (01011001B).
CLR C
Bytes 1
Cycles 1
Encoding 1 1 0 0 0 0 1 1
Operation CLR
(C)w0
CLR bit
Bytes 2
Cycles 1
Operation CLR
(bit)w0
35
CPL A
Function CompIement AccumuIatoi
Description Fach bit of the AccumuIatoi is IogicaIIy compIemented (ones compIement). Bits which pievi-
ousIy contained a one aie changed to a zeio and vice-veisa. No fIags aie affected.
Example The AccumuIatoi contains 5CH (01011100B). The instiuction,
CPL A
wiII Ieave the AccumuIatoi set to 0A3H (10100011B).
Bytes 1
Cycles 1
Encoding 1 1 1 1 0 1 0 0
Operation CPL
(A)w
s
(A)
CPL bit
Function CompIement bit
Description The bit vaiiabIe specified is compIemented. A bit which had been a one is changed to zeio and
vice-veisa. No othei fIags aie affected. CLR can opeiate on the caiiy oi any diiectIy addiess-
abIe bit.
Note When this instiuction is used to modify an output pin, the vaIue used as the oiiginaI data
wiII be iead fiom the output data Iatch, not the input pin.
Example Poit 1 has pieviousIy been wiitten with 5BH (01011101B). The instiuction sequence,
CPL P1.1
CPL P1.2
wiII Ieave the poit set to 5BH (01011011B).
CPL C
Bytes 1
Cycles 1
Encoding 1 0 1 1 0 0 1 1
Operation CPL
(C)w
s
(C)
36
CPL bit
Bytes 2
Cycles 1
Operation CPL
(bit)w
s
(bit)
DA A
Function DecimaI-adjust AccumuIatoi foi Addition
Description DA A adjusts the eight-bit vaIue in the AccumuIatoi iesuIting fiom the eaiIiei addition of two
vaiiabIes (each in packed-BCD foimat), pioducing two foui-bit digits. Any ADD oi ADDC
instiuction may have been used to peifoim the addition.
If AccumuIatoi bits 3-0 aie gieatei than nine (xxxx1010-xxxx1111), oi if the AC fIag is one,
six is added to the AccumuIatoi pioducing the piopei BCD digit in the Iow-oidei nibbIe. This
inteinaI addition wouId set the caiiy fIag if a caiiy-out of the Iow-oidei foui-bit fieId piopagat-
ed thiough aII high-oidei bits, but it wouId not cIeai the caiiy fIag otheiwise.
If the caiiy fIag is now set, oi if the foui high-oidei bits now exceed nine (1010xxxx-111xxxx),
these high-oidei bits aie inciemented by six, pioducing the piopei BCD digit in the high-oidei
nibbIe. Again, this wouId set the caiiy fIag if theie was a caiiy-out of the high-oidei bits, but
wouIdnt cIeai the caiiy. The caiiy fIag thus indicates if the sum of the oiiginaI two BCD
vaiiabIes is gieatei than 100, aIIowing muItipIe piecision decimaI addition. OV is not affected.
AII of this occuis duiing the one instiuction cycIe. FssentiaIIy, this instiuction peifoims the
decimaI conveision by adding 00H, 06H, 60H, oi 66H to the AccumuIatoi, depending on
initiaI AccumuIatoi and PSW conditions.
Note DA A cannot simpIy conveit a hexadecimaI numbei in the AccumuIatoi to BCD nota-
tion, noi does DA A appIy to decimaI subtiaction.
37
Example The AccumuIatoi hoIds the vaIue 56H (01010110B) iepiesenting the packed BCD digits of the
decimaI numbei 56. Registei 3 contains the vaIue 67H (01100111B) iepiesenting the packed
BCD digits of the decimaI numbei 67. The caiiy fIag is set. The instiuction sequence.
ADDC A,R3
DA A
wiII fiist peifoim a standaid twos-compIement binaiy addition, iesuIting in the vaIue 0BFH
(10111110) in the AccumuIatoi. The caiiy and auxiIiaiy caiiy fIags wiII be cIeaied.
The DecimaI Adjust instiuction wiII then aItei the AccumuIatoi to the vaIue 24H
(00100100B), indicating the packed BCD digits of the decimaI numbei 24, the Iow-oidei two
digits of the decimaI sum of 56, 67, and the caiiy-in. The caiiy fIag wiII be set by the DecimaI
Adjust instiuction, indicating that a decimaI oveifIow occuiied. The tiue sum 56, 67, and 1 is
124.
BCD vaiiabIes can be inciemented oi deciemented by adding 01H oi 99H. If the AccumuIatoi
initiaIIy hoIds 30H (iepiesenting the digits of 30 decimaI), then the instiuction sequence,
ADD A,99H
DA A
wiII Ieave the caiiy set and 29H in the AccumuIatoi, since 30
a
99
e
129. The Iow-oidei
byte of the sum can be inteipieted to mean 30
b
1
e
29.
Bytes 1
Cycles 1
Encoding 1 1 0 1 0 1 0 0
Operation DA
-contents of AccumuIatoi aie BCD
IF (A
3-0
)
l
9 (AC)
e
1
THFN(A
3-0
)w(A
3-0
)
a
6
AND
IF (A
7-4
)
l
9 (C)
e
1
THFN (A
7-4
)w(A
7-4
)
a
6
38
DEC byte
Function Deciement
Description The vaiiabIe indicated is deciemented by 1. An oiiginaI vaIue of 00H wiII undeifIow to 0FFH.
No fIags aie affected. Foui opeiand addiessing modes aie aIIowed: accumuIatoi, iegistei,
diiect, oi iegistei-indiiect.
Example Registei 0 contains 7FH (01111111B). InteinaI RAM Iocations 7FH and 7FH contain 00H
and 40H, iespectiveIy. The instiuction sequence,
DFC

R0
DFC R0
DFC

R0
wiII Ieave iegistei 0 set to 7FH and inteinaI RAM Iocations 7FH and 7FH set to 0FFH and
3FH.
DEC A
Bytes 1
Cycles 1
Encoding 0 0 0 1 0 1 0 0
Operation DFC
(A)w(A)
b
1
DEC Rn
Bytes 1
Cycles 1
Operation DFC
(Rn)w(Rn)
b
1
39
DEC direct
Bytes 2
Cycles 1
Operation DFC
(diiect)w(diiect)
b
1
DEC

Ri
Bytes 1
Cycles 1
Encoding 0 0 0 1 0 1 1 i
Operation DFC
((Ri))w((Ri))
b
1
DIV AB
Function Divide
Description DIV AB divides the unsigned eight-bit integei in the AccumuIatoi by the unsigned eight-bit
integei in iegistei B. The AccumuIatoi ieceives the integei pait of the quotient: iegistei B
ieceives the integei iemaindei. The caiiy and OV fIags wiII be cIeaied.
Exception if B had oiiginaIIy contained 00H, the vaIues ietuined in the AccumuIatoi and B-
iegistei wiII be undefined and the oveifIow fIag wiII be set. The caiiy fIag is cIeaied in any
case.
Example The AccumuIatoi contains 251 (0FBH oi 11111011B) and B contains 18 (12H oi 00010010B).
The instiuction,
DIV AB
wiII Ieave 13 in the AccumuIatoi (0DH oi 00001101B) and the vaIue 17 (11H oi 00010001B)
in B, since 251
e
(13 X 18)
a
17. Caiiy and OV wiII both be cIeaied.
Bytes 1
Cycles 4
Encoding 1 0 0 0 0 1 0 0
Operation DIV
(A)
15-8
w(A)/(B)
(B)
7-0
40
DJNZ
k
byte
l
k
rel-addr
l
Function Deciement and Jump if Not Zeio
Description DJNZ deciements the Iocation indicated by 1, and bianches to the addiess indicated by the
second opeiand if the iesuIting vaIue is not zeio. An oiiginaI vaIue of 00H wiII undeifIow to
0FFH. No fIags aie affected. The bianch destination wouId be computed by adding the signed
ieIative-dispIacement vaIue in the Iast instiuction byte to the PC, aftei inciementing the PC to
the fiist byte of the foIIowing instiuction.
The Iocation deciemented may be a iegistei oi diiectIy addiessed byte.
Example InteinaI RAM Iocations 40H, 50H, and 60H contain the vaIues 01H, 70H, and 15H, iespec-
tiveIy. The instiuction sequence,
DJNZ 40H,LABFL
-
1
DJNZ 50H,LABFL
-
2
DJNZ 60H,LABFL
-
3
wiII cause a jump to the instiuction at IabeI LABFL
-
2 with the vaIues 00H, 6FH, and 15H in
the thiee RAM Iocations. The fiist jump was not taken because the iesuIt was zeio.
This instiuction piovides a simpIe way of executing a piogiam Ioop a given numbei of times,
oi foi adding a modeiate time deIay (fiom 2 to 512 machine cycIes) with a singIe instiuction.
The instiuction sequence,
MOV R2,8
TOOOLF: CPL P1.7
DJNZ R2,TOOOLF
wiII toggIe P1.7 eight times, causing foui output puIses to appeai at bit 7 of output Poit 1.
Fach puIse wiII Iast thiee machine cycIes: two foi DJNZ and one to aItei the pin.
DJNZ Rnrel
Bytes 2
Cycles 2
Encoding 1 1 0 1 1 r r r rel address
Operation DJNZ
(PC)w(PC)
a
2
(Rn)w(Rn)
b
1
IF (Rn)
l
0 oi (Rn)
k
0
THFN
(PC)w(PC)
a
ieI
41
DJNZ directrel
Bytes 3
Cycles 2
Encoding 1 1 0 1 0 1 0 1 direct address rel address
Operation DJNZ
(PC)w(PC)
a
2
(diiect)w(diiect)
b
1
IF (diiect)
l
0 oi (diiect)
k
0
THFN
(PC)w(PC)
a
ieI
INC
k
byte
l
Function Inciement
Description INC inciements the indicated vaiiabIe by 1. An oiiginaI vaIue of 0FFH wiII oveifIow to 00H.
No fIags aie affected. Thiee addiessing modes aie aIIowed: iegistei, diiect, oi iegistei-indiiect.
Example Registei 0 contains 7FH (011111110B). InteinaI RAM Iocations 7FH and 7FH contain 0FFH
and 40H, iespectiveIy. The instiuction sequence,
INC

R0
INC R0
INC

R0
wiII Ieave iegistei 0 set to 7FH and inteinaI RAM Iocations 7FH and 7FH hoIding (iespective-
Iy) 00H and 41H.
INC A
Bytes 1
Cycles 1
Encoding 0 0 0 0 0 1 0 0
Operation INC
(A)w(A)
a
1
42
INC Rn
Bytes 1
Cycles 1
Operation INC
(Rn)w(Rn)
a
1
INC direct
Bytes 2
Cycles 1
Operation INC
(diiect)w(diiect)
a
1
INC

Ri
Bytes 1
Cycles 1
Encoding 0 0 0 0 0 1 1 i
Operation INC
((Ri))w((Ri))
a
1
INC DPTR
Function Inciement Data Pointei
Description Inciement the 16-bit data pointei by 1. A 16-bit inciement (moduIo 2
16
) is peifoimed: an
oveifIow of the Iow-oidei byte of the data pointei (DPL) fiom 0FFH to 00H wiII inciement
the high-oidei byte (DPH). No fIags aie affected.
This is the onIy 16-bit iegistei which can be inciemented.
Example Registeis DPH and DPL contain 12H and 0FFH, iespectiveIy. The instiuction sequence,
INC DPTR
INC DPTR
INC DPTR
wiII change DPH and DPL to 13H and 01H.
Bytes 1
Cycles 2
Encoding 1 0 1 0 0 0 1 1
Operation INC
(DPTR)w(DPTR)
a
1
43
JB bitrel
Function Jump if Bit set
Description If the indicated bit is a one, jump to the addiess indicated: otheiwise pioceed with the next
instiuction. The bianch destination is computed by adding the signed ieIative-dispIacement in
the thiid instiuction byte to the PC, aftei inciementing the PC to the fiist byte of the next
instiuction. The bit tested is not modified No fIags aie affected.
Example The data piesent at input poit 1 is 11001010B. The AccumuIatoi hoIds 56 (01010110B). The
instiuction sequence,
JB P1.2,LABFL1
JB ACC.2,LABFL2
wiII cause piogiam execution to bianch to the instiuction at IabeI LABFL2.
Bytes 3
Cycles 2
Encoding 0 0 1 0 0 0 0 0 bit address rel address
Operation JB
(PC)w(PC)
a
3
IF (bit)
e
1
THFN
(PC)w(PC)
a
ieI
JBC bitrel
Function Jump if Bit is set and CIeai bit
Description If the indicated bit is one, bianch to the addiess indicated: otheiwise pioceed with the next
instiuction. The bit will not be cleared if it is already a zero The bianch destination is comput-
ed by adding the signed ieIative-dispIacement in the thiid instiuction byte to the PC, aftei
inciementing the PC to the fiist byte of the next instiuction. No fIags aie affected.
Note When this instiuction is used to test an output pin, the vaIue used as the oiiginaI data
wiII be iead fiom the output data Iatch, not the input pin.
Example The AccumuIatoi hoIds 56H (01010110B). The instiuction sequence,
JBC ACC.3,LABFL1
JBC ACC.2,LABFL2
wiII cause piogiam execution to continue at the instiuction identified by the IabeI LABFL2,
with the AccumuIatoi modified to 52H (01010010B).
44
Bytes 3
Cycles 2
Operation JBC
(PC)w(PC)
a
3
IF (bit)
e
1
THFN
(bit)w0
(PC)w(PC)
a
ieI
JC rel
Function Jump if Caiiy is set
Description If the caiiy fIag is set, bianch to the addiess indicated: otheiwise pioceed with the next
the second instiuction byte to the PC, aftei inciementing the PC twice. No fIags aie affected.
Example The caiiy fIag is cIeaied. The instiuction sequence,
JC LABFL1
CPL C
JC LABFL 2
wiII set the caiiy and cause piogiam execution to continue at the instiuction identified by the
IabeI LABFL2.
Bytes 2
Cycles 2
Encoding 0 1 0 0 0 0 0 0 rel address
Operation JC
(PC)w(PC)
a
2
IF (C)
e
1
THFN
(PC)w(PC)
a
ieI
45
JMP

A
a
DPTR
Function Jump indiiect
Description Add the eight-bit unsigned contents of the AccumuIatoi with the sixteen-bit data pointei, and
Ioad the iesuIting sum to the piogiam countei. This wiII be the addiess foi subsequent instiuc-
tion fetches. Sixteen-bit addition is peifoimed (moduIo 2
16
): a caiiy-out fiom the Iow-oidei
eight bits piopagates thiough the highei-oidei bits. Neithei the AccumuIatoi noi the Data
Pointei is aIteied. No fIags aie affected.
Example An even numbei fiom 0 to 6 is in the AccumuIatoi. The foIIowing sequence of instiuctions wiII
bianch to one of foui AJMP instiuctions in a jump tabIe staiting at JMP
-
TBL:
MOV DPTR,JMP
-
TBL
JMP

A
a
DPTR
JMP
-
TBL: AJMP LABFL0
AJMP LABFL1
AJMP LABFL2
AJMP LABFL3
If the AccumuIatoi equaIs 04H when staiting this sequence, execution wiII jump to IabeI
LABFL2. Remembei that AJMP is a two-byte instiuction, so the jump instiuctions stait at
eveiy othei addiess.
Bytes 1
Cycles 2
Encoding 0 1 1 1 0 0 1 1
Operation JMP
(PC)w(A)
a
(DPTR)
46
JNB bitrel
Function Jump if Bit Not set
Description If the indicated bit is a zeio, bianch to the indicated addiess: otheiwise pioceed with the next
the thiid instiuction byte to the PC, aftei inciementing the PC to the fiist byte of the next
instiuction. The bit tested is not modified. No fIags aie affected.
Example The data piesent at input poit 1 is 11001010B. The AccumuIatoi hoIds 56H (01010110B). The
instiuction sequence,
JNB P1.3,LABFL1
JNB ACC.3,LABFL2
wiII cause piogiam execution to continue at the instiuction at IabeI LABFL2.
Bytes 3
Cycles 2
Operation JNB
(PC)w(PC)
a
3
IF (bit)
e
0
THFN (PC)w(PC)
a
ieI.
JNC rel
Function Jump if Caiiy not set
Description If the caiiy fIag is a zeio, bianch to the addiess indicated: otheiwise pioceed with the next
the second instiuction byte to the PC, aftei inciementing the PC twice to point to the next
instiuction. The caiiy fIag is not modified.
Example The caiiy fIag is set. The instiuction sequence,
JNC LABFL1
CPL C
JNC LABFL2
wiII cIeai the caiiy and cause piogiam execution to continue at the instiuction identified by
the IabeI LABFL2.
Bytes 2
Cycles 2
Operation JNC
(PC)w(PC)
a
2
IF (C)
e
0
THFN (PC)w(PC)
a
ieI
47
JNZ rel
Function Jump if AccumuIatoi Not Zeio
Description If any bit of the AccumuIatoi is a one, bianch to the indicated addiess: otheiwise pioceed with
the next instiuction. The bianch destination is computed by adding the signed ieIative-dis-
pIacement in the second instiuction byte to the PC, aftei inciementing the PC twice. The
AccumuIatoi is not modified. No fIags aie affected.
Example The AccumuIatoi oiiginaIIy hoIds 00H. The instiuction sequence,
JNZ LABFL1
INC A
JNZ LABFL2
wiII set the AccumuIatoi to 01H and continue at IabeI LABFL2.
Bytes 2
Cycles 2
Operation JNZ
(PC)w(PC)
a
2
IF (A)
i
0
THFN (PC)w(PC)
a
ieI
JZ rel
Function Jump if AccumuIatoi Zeio
Description If aII bits of the AccumuIatoi aie zeio, bianch to the addiess indicated: otheiwise pioceed with
the next instiuction. The bianch destination is computed by adding the signed ieIative-dis-
pIacement in the second instiuction byte to the PC, aftei inciementing the PC twice. The
AccumuIatoi is not modified. No fIags aie affected.
Example The AccumuIatoi oiiginaIIy contains 01H. The instiuction sequence,
JZ LABFL1
DFC A
JZ LABFL2
wiII change the AccumuIatoi to 00H and cause piogiam execution to continue at the instiuc-
tion identified by the IabeI LABFL2.
Bytes 2
Cycles 2
Operation JZ
(PC)w(PC)
a
2
IF (A)
e
0
THFN (PC)w(PC)
a
ieI
48
LCALL addr16
Function Long caII
Description LCALL caIIs a subioutine Iocated at the indicated addiess. The instiuction adds thiee to the
piogiam countei to geneiate the addiess of the next instiuction and then pushes the 16-bit
iesuIt onto the stack (Iow byte fiist), inciementing the Stack Pointei by two. The high-oidei
and Iow-oidei bytes of the PC aie then Ioaded, iespectiveIy, with the second and thiid bytes of
the LCALL instiuction. Piogiam execution continues with the instiuction at this addiess. The
subioutine may theiefoie begin anywheie in the fuII 64K-byte piogiam memoiy addiess space.
No fIags aie affected.
Example InitiaIIy the Stack Pointei equaIs 07H. The IabeI SUBRTN is assigned to piogiam memoiy
Iocation 1234H. Aftei executing the instiuction,
LCALL SUBRTN
at Iocation 0123H, the Stack Pointei wiII contain 09H, inteinaI RAM Iocations 08H and 09H
wiII contain 26H and 01H, and the PC wiII contain 1234H.
Bytes 3
Cycles 2
Encoding 0 0 0 1 0 0 1 0 addr15-addr8 addr7-addr0
Operation LCALL
(PC)w(PC)
a
3
(SP)w(SP)
a
1
((SP))w(PC
7-0
)
(SP)w(SP)
a
1
((SP))w(PC
15-8
)
(PC)waddi
15-0
LJMP addr16
Function Long Jump
Description LJMP causes an unconditionaI bianch to the indicated addiess, by Ioading the high-oidei and
Iow-oidei bytes of the PC (iespectiveIy) with the second and thiid instiuction bytes. The
destination may theiefoie be anywheie in the fuII 64K piogiam memoiy addiess space. No
fIags aie affected.
Example The IabeI JMPADR is assigned to the instiuction at piogiam memoiy Iocation 1234H. The
instiuction,
LJMP JMPADR
at Iocation 0123H wiII Ioad the piogiam countei with 1234H.
Bytes 3
Cycles 2
Encoding 0 0 0 0 0 0 1 0 addr15-addr8 addr7-addr0
Operation LJMP
(PC)waddi
15-0
49
MOV
k
dest-byte
l
k
src-byte
l
Function Move byte vaiiabIe
Description The byte vaiiabIe indicated by the second opeiand is copied into the Iocation specified by the
fiist opeiand. The souice byte is not affected. No othei iegistei oi fIag is affected.
This is by fai the most fIexibIe opeiation. Fifteen combinations of souice and destination
addiessing modes aie aIIowed.
Example InteinaI RAM Iocation 30H hoIds 40H. The vaIue of RAM Iocation 40H is 10H. The data
piesent at input poit 1 is 11001010B (0CAH).
MOV R0,30H :R0
ke
30H
MOV A,
R0 :A
ke
40H
MOV R1,A :R1
ke
40H
MOV B,
R1 :B
ke
10H
MOV

R1,P1 :RAM (40H)
ke
0CAH
MOV P2,P1 :P2 0CAH
Ieaves the vaIue 30H in iegistei 0, 40H in both the AccumuIatoi and iegistei 1, 10H in iegistei
B, and 0CAH (11001010B) both in RAM Iocation 40H and output on poit 2.
MOV ARn
Bytes 1
Cycles 1
Operation MOV
(A)w(Rn)
MOV Adirect
Bytes 2
Cycles 1
Operation MOV
(A)w(diiect)
MOV AACC is not a valid instruction
50
MOV A
Ri
Bytes 1
Cycles 1
Encoding 1 1 1 0 0 1 1 i
Operation MOV
(A)w((Ri))
MOV Adata
Bytes 2
Cycles 1
Operation MOV
(A)wdata
MOV RnA
Bytes 1
Cycles 1
Operation MOV
(Rn)w(A)
MOV Rndirect
Bytes 2
Cycles 2
Encoding 1 0 1 0 1 r r r direct addr
Operation MOV
(Rn)w(diiect)
MOV Rndata
Bytes 2
Cycles 1
Encoding 0 1 1 1 1 r r r immediate data
Operation MOV
(Rn)wdata
51
MOV directA
Bytes 2
Cycles 1
Operation MOV
(diiect)w(A)
MOV directRn
Bytes 2
Cycles 2
Encoding 1 0 0 0 1 r r r direct address
Operation MOV
(diiect)w(Rn)
MOV directdirect
Bytes 3
Cycles 2
Encoding 1 0 0 0 0 1 0 1 dir addr (src) dir addr (dest)
Operation MOV
(diiect)w(diiect)
MOV direct
Ri
Bytes 2
Cycles 2
Encoding 1 0 0 0 0 1 1 i direct addr
Operation MOV
(diiect)w((Ri))
MOV directdata
Bytes 3
Cycles 2
Operation MOV
(diiect)wdata
52
MOV

RiA
Bytes 1
Cycles 1
Encoding 1 1 1 1 0 1 1 i
Operation MOV
((Ri))w(A)
MOV

Ridirect
Bytes 2
Cycles 2
Encoding 1 0 1 0 0 1 1 i direct addr
Operation MOV
((Ri))w(diiect)
MOV

Ridata
Bytes 2
Cycles 1
Encoding 0 1 1 1 0 1 1 i immediate data
Operation MOV
((RI))wdata
MOV
k
dest-bit
l
k
src-bit
l
Function Move bit data
Description The BooIean vaiiabIe indicated by the second opeiand is copied into the Iocation specified by
the fiist opeiand. One of the opeiands must be the caiiy fIag: the othei may be any diiectIy
addiessabIe bit. No othei iegistei oi fIag is affected.
Example The caiiy fIag is oiiginaIIy set. The data piesent at input Poit 3 is 11000101B. The data
pieviousIy wiitten to output Poit 1 is 35H (00110101B).
MOV P1.3,C
MOV C,P3.3
MOV P1.2,C
wiII Ieave the caiiy cIeaied and change Poit 1 to 39H (00111001B).
53
MOV Cbit
Bytes 2
Cycles 1
Operation MOV
(C)w(bit)
MOV bitC
Bytes 2
Cycles 2
Operation MOV
(bit)w(C)
MOV DPTRdata16
Function Load Data Pointei with a 16-bit constant
Description The Data Pointei is Ioaded with the 16-bit constant indicated. The 16-bit constant is Ioaded
into the second and thiid bytes of the instiuction. The second byte (DPH) is the high-oidei
byte, whiIe the thiid byte (DPL) hoIds the Iow-oidei byte. No fIags aie affected.
This is the onIy instiuction which moves 16 bits of data at once.
Example The instiuction,
MOV DPTR,1234H
wiII Ioad the vaIue 1234H into the Data Pointei: DPH wiII hoId 12H and DPL wiII hoId 34H.
Bytes 3
Cycles 2
Encoding 1 0 0 1 0 0 0 0 immed data15-8 immed data7-0
Operation MOV
(DPTR)wdata
15-0
DPH V DPLwdata
15-8
V data
7-0
54
MOVC A
A
ak
base-reg
l
Function Move Code byte
Description The MOVC instiuctions Ioad the AccumuIatoi with a code byte, oi constant fiom piogiam
memoiy. The addiess of the byte fetched is the sum of the oiiginaI unsigned eight-bit Accumu-
Iatoi contents and the contents of a sixteen-bit base iegistei, which may be eithei the Data
Pointei oi the PC. In the Iattei case, the PC is inciemented to the addiess of the foIIowing
instiuction befoie being added with the AccumuIatoi: otheiwise the base iegistei is not aI-
teied. Sixteen-bit addition is peifoimed so a caiiy-out fiom the Iow-oidei eight bits may
piopagate thiough highei-oidei bits. No fIags aie affected.
Example A vaIue between 0 and 3 is in the AccumuIatoi. The foIIowing instiuctions wiII tiansIate the
vaIue in the AccumuIatoi to one of foui vaIues defined by the DB (define byte) diiective.
RFL
-
PC: INC A
MOVC A,
A
a
PC
RFT
DB 66H
DB 77H
DB 88H
DB 99H
If the subioutine is caIIed with the AccumuIatoi equaI to 01H, it wiII ietuin with 77H in the
AccumuIatoi. The INC A befoie the MOVC instiuction is needed to get aiound the RFT
instiuction above the tabIe. If seveiaI bytes of code sepaiated the MOVC fiom the tabIe, the
coiiesponding numbei wouId be added to the AccumuIatoi instead.
MOVC A
A
a
DPTR
Bytes 1
Cycles 2
Encoding 1 0 0 1 0 0 1 1
Operation MOVC
(A)w((A)
a
(DPTR))
MOVC A
A
a
PC
Bytes 1
Cycles 2
Encoding 1 0 0 0 0 0 1 1
Operation MOVC
(PC)w(PC)
a
1
(A)w((A)
a
(PC))
55
MOVX
k
dest-byte
l
k
src-byte
l
Function Move FxteinaI
Description The MOVX instiuctions tiansfei data between the AccumuIatoi and a byte of exteinaI data
memoiy, hence the X appended to MOV. Theie aie two types of instiuctions, diffeiing in
whethei they piovide an eight-bit oi sixteen-bit indiiect addiess to the exteinaI data RAM.
In the fiist type, the contents of R0 oi R1 in the cuiient iegistei bank piovide an eight-bit
addiess muItipIexed with data on P0. Fight bits aie sufficient foi exteinaI I/O expansion
decoding oi foi a ieIativeIy smaII RAM aiiay. Foi somewhat Iaigei aiiays, any output poit
pins can be used to output highei-oidei addiess bits. These pins wouId be contioIIed by an
output instiuction pieceding the MOVX.
In the second type of MOVX instiuction, the Data Pointei geneiates a sixteen-bit addiess. P2
outputs the high-oidei eight addiess bits (the contents of DPH) whiIe P0 muItipIexes the Iow-
oidei eight bits (DPL) with data. The P2 SpeciaI Function Registei ietains its pievious con-
tents whiIe the P2 output buffeis aie emitting the contents of DPH. This foim is fastei and
moie efficient when accessing veiy Iaige data aiiays (up to 64K bytes), since no additionaI
instiuctions aie needed to set up the output poits.
It is possibIe in some situations to mix the two MOVX types. A Iaige RAM aiiay with its
high-oidei addiess Iines diiven by P2 can be addiessed via the Data Pointei, oi with code to
output high-oidei addiess bits to P2 foIIowed by a MOVX instiuction using R0 oi R1.
Example An exteinaI 256 byte RAM using muItipIexed addiess/data Iines (e.g., an InteI 8155 RAM/
I/O/Timei) is connected to the 8051 Poit 0. Poit 3 piovides contioI Iines foi the exteinaI
RAM. Poits 1 and 2 aie used foi noimaI I/O. Registeis 0 and 1 contain 12H and 34H.
Location 34H of the exteinaI RAM hoIds the vaIue 56H. The instiuction sequence,
MOVX A,
R1
MOVX

R0,A
copies the vaIue 56H into both the AccumuIatoi and exteinaI RAM Iocation 12H.
56
MOVX A
Ri
Bytes 1
Cycles 2
Encoding 1 1 1 0 0 0 1 i
Operation MOVX
(A)w((Ri))
MOVX A
DPTR
Bytes 1
Cycles 2
Encoding 1 1 1 0 0 0 0 0
Operation MOVX
(A)w((DPTR))
MOVX

RiA
Bytes 1
Cycles 2
Encoding 1 1 1 1 0 0 1 i
Operation MOVX
((Ri))w(A)
MOVX

DPTRA
Bytes 1
Cycles 2
Encoding 1 1 1 1 0 0 0 0
Operation MOVX
(DPTR)w(A)
57
MUL AB
Function MuItipIy
Description MUL AB muItipIies the unsigned eight-bit integeis in the AccumuIatoi and iegistei B. The
Iow-oidei byte of the sixteen-bit pioduct is Ieft in the AccumuIatoi, and the high-oidei byte in
B. If the pioduct is gieatei than 255 (0FFH) the oveifIow fIag is set: otheiwise it is cIeaied.
The caiiy fIag is aIways cIeaied.
Example OiiginaIIy the AccumuIatoi hoIds the vaIue 80 (50H). Registei B hoIds the vaIue 160 (0A0H).
The instiuction,
MUL AB
wiII give the pioduct 12,800 (3200H), so B is changed to 32H (00110010B) and the AccumuIa-
toi is cIeaied. The oveifIow fIag is set, caiiy is cIeaied.
Bytes 1
Cycles 4
Encoding 1 0 1 0 0 1 0 0
Operation MUL
(A)
7-0
w(A) X (B)
(B)
15-8
NOP
Function No Opeiation
Description Fxecution continues at the foIIowing instiuction. Othei than the PC, no iegisteis oi fIags aie
affected.
Example It is desiied to pioduce a Iow-going output puIse on bit 7 of Poit 2 Iasting exactIy 5 cycIes. A
simpIe SFTB/CLR sequence wouId geneiate a one-cycIe puIse, so foui additionaI cycIes must
be inseited. This may be done (assuming no inteiiupts aie enabIed) with the instiuction
sequence,
CLR P2.7
NOP
NOP
NOP
NOP
SFTB P2.7
Bytes 1
Cycles 1
Encoding 0 0 0 0 0 0 0 0
Operation NOP
(PC)w(PC)
a
1
58
ORL
k
dest-byte
l k
src-byte
l
Function LogicaI-OR foi byte vaiiabIes
Description ORL peifoims the bitwise IogicaI-OR opeiation between the indicated vaiiabIes, stoiing the
iesuIts in the destination byte. No fIags aie affected.
Example If the AccumuIatoi hoIds 0C3H (11000011B) and R0 hoIds 55H (01010101B) then the in-
stiuction,
ORL A,R0
wiII Ieave the AccumuIatoi hoIding the vaIue 0D7H (11010111B).
When the destination is a diiectIy addiessed byte, the instiuction can set combinations of bits
in any RAM Iocation oi haidwaie iegistei. The pattein of bits to be set is deteimined by a
mask byte, which may be eithei a constant data vaIue in the instiuction oi a vaiiabIe computed
in the AccumuIatoi at iun-time. The instiuction,
ORL P1,00110010B
wiII set bits 5, 4, and 1 of output Poit 1.
ORL ARn
Bytes 1
Cycles 1
Operation ORL
(A)w(A) (Rn)
59
ORL Adirect
Bytes 2
Cycles 1
Operation ORL
(A)w(A) (diiect)
ORL A
Ri
Bytes 1
Cycles 1
Encoding 0 1 0 0 0 1 1 i
Operation ORL
(A)w(A) ((Ri))
ORL Adata
Bytes 2
Cycles 1
Operation ORL
(A)w(A) data
ORL directA
Bytes 2
Cycles 1
Operation ORL
(diiect)w(diiect) (A)
ORL directdata
Bytes 3
Cycles 2
Encoding 0 1 0 0 0 0 1 1 direct addr immediate data
Operation ORL
(diiect)w(diiect) data
60
ORL C
k
src-bit
l
Function LogicaI-OR foi bit vaiiabIes
Description Set the caiiy fIag if the BooIean vaIue is a IogicaI 1: Ieave the caiiy in its cuiient state
otheiwise . A sIash (/) pieceding the opeiand in the assembIy Ianguage indicates that the
IogicaI compIement of the addiessed bit is used as the souice vaIue, but the souice bit itseIf is
not affected. No othei fIags aie affected.
Example Set the caiiy fIag if and onIy if P1.0
e
1, ACC. 7
e
1, oi OV
e
0:
MOV C,P1.0 :LOAD CARRY WITH INPUT PIN P10
ORL C,ACC.7 :OR CARRY WITH THF ACC. BIT 7
ORL C,/OV :OR CARRY WITH THF INVFRSF OF OV.
ORL Cbit
Bytes 2
Cycles 2
Operation ORL
(C)w(C) (bit)
ORL Cbit
Bytes 2
Cycles 2
Operation ORL
(C)w(C) (bit)
61
POP direct
Function Pop fiom stack.
Description The contents of the inteinaI RAM Iocation addiessed by the Stack Pointei is iead, and the
Stack Pointei is deciemented by one. The vaIue iead is then tiansfeiied to the diiectIy ad-
diessed byte indicated. No fIags aie affected.
Example The Stack Pointei oiiginaIIy contains the vaIue 32H, and inteinaI RAM Iocations 30H
thiough 32H contain the vaIues 20H, 23H, and 01H, iespectiveIy. The instiuction sequence,
POP DPH
POP DPL
wiII Ieave the Stack Pointei equaI to the vaIue 30H and the Data Pointei set to 0123H. At this
point the instiuction,
POP SP
wiII Ieave the Stack Pointei set to 20H. Note that in this speciaI case the Stack Pointei was
deciemented to 2FH befoie being Ioaded with the vaIue popped (20H).
Bytes 2
Cycles 2
Operation POP
(diiect)w((SP))
(SP)w(SP)
b
1
PUSH direct
Function Push onto stack
Description The Stack Pointei is inciemented by one. The contents of the indicated vaiiabIe is then copied
into the inteinaI RAM Iocation addiessed by the Stack Pointei. Otheiwise no fIags aie affect-
ed.
Example On enteiing an inteiiupt ioutine the Stack Pointei contains 09H. The Data Pointei hoIds the
vaIue 0123H. The instiuction sequence,
PUSH DPL
PUSH DPH
wiII Ieave the Stack Pointei set to 0BH and stoie 23H and 01H in inteinaI RAM Iocations
0AH and 0BH, iespectiveIy.
Bytes 2
Cycles 2
Operation PUSH
(SP)w(SP)
a
1
((SP))w(diiect)
62
RET
Function Retuin fiom subioutine
Description RFT pops the high- and Iow-oidei bytes of the PC successiveIy fiom the stack, deciementing
the Stack Pointei by two. Piogiam execution continues at the iesuIting addiess, geneiaIIy the
instiuction immediateIy foIIowing an ACALL oi LCALL. No fIags aie affected.
Example The Stack Pointei oiiginaIIy contains the vaIue 0BH. InteinaI RAM Iocations 0AH and 0BH
contain the vaIues 23H and 01H, iespectiveIy. The instiuction,
RFT
wiII Ieave the Stack Pointei equaI to the vaIue 09H. Piogiam execution wiII continue at
Iocation 0123H.
Bytes 1
Cycles 2
Encoding 0 0 1 0 0 0 1 0
Operation RFT
(PC
15-8
)w((SP))
(SP)w(SP)
b
1
(PC
7-0
)w((SP))
(SP)w(SP)
b
1
RETI
Function Retuin fiom inteiiupt
Description RFTI pops the high- and Iow-oidei bytes of the PC successiveIy fiom the stack, and iestoies
the inteiiupt Iogic to accept additionaI inteiiupts at the same piioiity IeveI as the one just
piocessed. The Stack Pointei is Ieft deciemented by two. No othei iegisteis aie affected: the
PSW is not automaticaIIy iestoied to its pie-inteiiupt status. Piogiam execution continues at
the iesuIting addiess, which is geneiaIIy the instiuction immediateIy aftei the point at which
the inteiiupt iequest was detected. If a Iowei- oi same-IeveI inteiiupt had been pending when
the RFTI instiuction is executed, that one instiuction wiII be executed befoie the pending
inteiiupt is piocessed.
Example The Stack Pointei oiiginaIIy contains the vaIue 0BH. An inteiiupt was detected duiing the
instiuction ending at Iocation 0122H. InteinaI RAM Iocations 0AH and 0BH contain the
vaIues 23H and 01H, iespectiveIy. The instiuction,
RFTI
wiII Ieave the Stack Pointei equaI to 09H and ietuin piogiam execution to Iocation 0123H.
Bytes 1
Cycles 2
Encoding 0 0 1 1 0 0 1 0
Operation RFTI
(PC
15-8
)w((SP))
(SP)w(SP)
b
1
(PC
7-0
)w((SP))
(SP)w(SP)
b
1
63
RL A
Function Rotate AccumuIatoi Left
Description The eight bits in the AccumuIatoi aie iotated one bit to the Ieft. Bit 7 is iotated into the bit 0
position. No fIags aie affected.
Example The AccumuIatoi hoIds the vaIue 0C5H (11000101B). The instiuction,
RL A
Ieaves the AccumuIatoi hoIding the vaIue 8BH (10001011B) with the caiiy unaffected.
Bytes 1
Cycles 1
Encoding 0 0 1 0 0 0 1 1
Operation RL
(A
n
a
1)w(An) n
e
0
b
6
(A0)w(A7)
RLC A
Function Rotate AccumuIatoi Left thiough the Caiiy fIag
Description The eight bits in the AccumuIatoi and the caiiy fIag aie togethei iotated one bit to the Ieft. Bit
7 moves into the caiiy fIag: the oiiginaI state of the caiiy fIag moves into the bit 0 position. No
othei fIags aie affected.
Example The AccumuIatoi hoIds the vaIue 0C5H (11000101B), and the caiiy is zeio. The instiuction,
RLC A
Ieaves the AccumuIatoi hoIding the vaIue 8BH (10001010B) with the caiiy set.
Bytes 1
Cycles 1
Encoding 0 0 1 1 0 0 1 1
Operation RLC
(An
a
1)w(An) n
e
0
b
6
(A0)w(C)
(C)w(A7)
64
RR A
Function Rotate AccumuIatoi Right
Description The eight bits in the AccumuIatoi aie iotated one bit to the iight. Bit 0 is iotated into the bit 7
position. No fIags aie affected.
RR A
Ieaves the AccumuIatoi hoIding the vaIue 0F2H (11100010B) with the caiiy unaffected.
Bytes 1
Cycles 1
Encoding 0 0 0 0 0 0 1 1
Operation RR
(An)w(A
n
a
1) n
e
0
b
6
(A7)w(A0)
RRC A
Function Rotate AccumuIatoi Right thiough Caiiy fIag
Description The eight bits in the AccumuIatoi and the caiiy fIag aie togethei iotated one bit to the iight.
Bit 0 moves into the caiiy fIag: the oiiginaI vaIue of the caiiy fIag moves into the bit 7
position. No othei fIags aie affected.
Example The AccumuIatoi hoIds the vaIue 0C5H (11000101B), the caiiy is zeio. The instiuction,
RRC A
Ieaves the AccumuIatoi hoIding the vaIue 62 (01100010B) with the caiiy set.
Bytes 1
Cycles 1
Encoding 0 0 0 1 0 0 1 1
Operation RRC
(An)w(An
a
1) n
e
0
b
6
(A7)w(C)
(C)w(A0)
65
SETB
k
bit
l
Function Set Bit
Description SFTB sets the indicated bit to one. SFTB can opeiate on the caiiy fIag oi any diiectIy
addiessabIe bit. No othei fIags aie affected.
Example The caiiy fIag is cIeaied. Output Poit 1 has been wiitten with the vaIue 34H (00110100B). The
instiuctions,
SFTB C
SFTB P1.0
wiII Ieave the caiiy fIag set to 1 and change the data output on Poit 1 to 35H (00110101B).
SETB C
Bytes 1
Cycles 1
Encoding 1 1 0 1 0 0 1 1
Operation SFTB
(C)w1
SETB bit
Bytes 2
Cycles 1
Operation SFTB
(bit)w1
66
SJMP rel
Function Shoit Jump
Description Piogiam contioI bianches unconditionaIIy to the addiess indicated. The bianch destination is
computed by adding the signed dispIacement in the second instiuction byte to the PC, aftei
inciementing the PC twice. Theiefoie, the iange of destinations aIIowed is fiom 128 bytes
pieceding this instiuction to 127 bytes foIIowing it.
Example The IabeI RFLADR is assigned to an instiuction at piogiam memoiy Iocation 0123H. The
instiuction,
SJMP RFLADR
wiII assembIe into Iocation 0100H. Aftei the instiuction is executed, the PC wiII contain the
vaIue 0123H.
(Note Undei the above conditions the instiuction foIIowing SJMP wiII be at 102H. Theiefoie,
the dispIacement byte of the instiuction wiII be the ieIative offset (0123H-0102H)
e
21H. Put
anothei way, an SJMP with a dispIacement of 0FFH wouId be a one-instiuction infinite Ioop.)
Bytes 2
Cycles 2
Operation SJMP
(PC)w(PC)
a
2
(PC)w(PC)
a
ieI
67
SUBB A
k
src-byte
l
Function Subtiact with boiiow
Description SUBB subtiacts the indicated vaiiabIe and the caiiy fIag togethei fiom the AccumuIatoi,
Ieaving the iesuIt in the AccumuIatoi. SUBB sets the caiiy (boiiow) fIag if a boiiow is needed
foi bit 7, and cIeais C otheiwise. (If C was set before executing a SUBB instiuction, this
indicates that a boiiow was needed foi the pievious step in a muItipIe piecision subtiaction, so
the caiiy is subtiacted fiom the AccumuIatoi aIong with the souice opeiand.) AC is set if a
boiiow is needed foi bit 3, and cIeaied otheiwise. OV is set if a boiiow is needed into bit 6, but
not into bit 7, oi into bit 7, but not bit 6.
When subtiacting signed integeis OV indicates a negative numbei pioduced when a negative
vaIue is subtiacted fiom a positive vaIue, oi a positive iesuIt when a positive numbei is
subtiacted fiom a negative numbei.
The souice opeiand aIIows foui addiessing modes: iegistei, diiect, iegistei-indiiect, oi imme-
diate.
Example The AccumuIatoi hoIds 0C9H (11001001B), iegistei 2 hoIds 54H (01010100B), and the caiiy
fIag is set. The instiuction,
SUBB A,R2
wiII Ieave the vaIue 74H (01110100B) in the accumuIatoi, with the caiiy fIag and AC cIeaied
but OV set.
Notice that 0C9H minus 54H is 75H. The diffeience between this and the above iesuIt is due
to the caiiy (boiiow) fIag being set befoie the opeiation. If the state of the caiiy is not known
befoie staiting a singIe oi muItipIe-piecision subtiaction, it shouId be expIicitIy cIeaied by a
CLR C instiuction.
SUBB ARn
Bytes 1
Cycles 1
Operation SUBB
(A)w(A)
b
(C)
b
(Rn)
68
SUBB Adirect
Bytes 2
Cycles 1
Operation SUBB
(A)w(A)
b
(C)
b
(diiect)
SUBB A
Ri
Bytes 1
Cycles 1
Encoding 1 0 0 1 0 1 1 i
Operation SUBB
(A)w(A)
b
(C)
b
((Ri))
SUBB Adata
Bytes 2
Cycles 1
Operation SUBB
(A)w(A)
b
(C)
b data
SWAP A
Function Swap nibbIes within the AccumuIatoi
Description SWAP A inteichanges the Iow- and high-oidei nibbIes (foui-bit fieIds) of the AccumuIatoi
(bits 3-0 and bits 7-4). The opeiation can aIso be thought of as a foui-bit iotate instiuction. No
fIags aie affected.
SWAP A
Ieaves the AccumuIatoi hoIding the vaIue 5CH (01011100B).
Bytes 1
Cycles 1
Encoding 1 1 0 0 0 1 0 0
Operation SWAP
(A
3-0
)
x
w
(A
7-4
)
69
XCH A
k
byte
l
Function Fxchange AccumuIatoi with byte vaiiabIe
Description XCH Ioads the AccumuIatoi with the contents of the indicated vaiiabIe, at the same time
wiiting the oiiginaI AccumuIatoi contents to the indicated vaiiabIe. The souice/destination
opeiand can use iegistei, diiect, oi iegistei-indiiect addiessing.
Example R0 contains the addiess 20H. The AccumuIatoi hoIds the vaIue 3FH (00111111B). InteinaI
RAM Iocation 20H hoIds the vaIue 75H (01110101B). The instiuction,
XCH A,
R0
wiII Ieave RAM Iocation 20H hoIding the vaIues 3FH (00111111B) and 75H (01110101B) in
the accumuIatoi.
XCH ARn
Bytes 1
Cycles 1
Operation XCH
(A)
x
w
(Rn)
XCH Adirect
Bytes 2
Cycles 1
Operation XCH
(A)
x
w
(diiect)
XCH A
Ri
Bytes 1
Cycles 1
Encoding 1 1 0 0 0 1 1 i
Operation XCH
(A)
x
w
((Ri))
70
XCHD A
Ri
Function Fxchange Digit
Description XCHD exchanges the Iow-oidei nibbIe of the AccumuIatoi (bits 3-0), geneiaIIy iepiesenting a
hexadecimaI oi BCD digit, with that of the inteinaI RAM Iocation indiiectIy addiessed by the
specified iegistei. The high-oidei nibbIes (bits 7-4) of each iegistei aie not affected. No fIags
aie affected.
Example R0 contains the addiess 20H. The AccumuIatoi hoIds the vaIue 36H (00110110B). InteinaI
RAM Iocation 20H hoIds the vaIue 75H (01110101B). The instiuction,
XCHD A,
R0
wiII Ieave RAM Iocation 20H hoIding the vaIue 76H (01110110B) and 35H (00110101B) in the
AccumuIatoi.
Bytes 1
Cycles 1
Encoding 1 1 0 1 0 1 1 i
Operation XCHD
(A
3-0
)
x
w
((Ri
3-0
))
XRL
k
dest-byte
l
k
src-byte
l
Function LogicaI FxcIusive-OR foi byte vaiiabIes
Description XRL peifoims the bitwise IogicaI FxcIusive-OR opeiation between the indicated vaiiabIes,
stoiing the iesuIts in the destination. No fIags aie affected.
(Note When this instiuction is used to modify an output poit, the vaIue used as the oiiginaI
poit data wiII be iead fiom the output data Iatch, not the input pins.)
Example If the AccumuIatoi hoIds 0C3H (11000011B) and iegistei 0 hoIds 0AAH (10101010B) then
the instiuction,
XRL A,R0
wiII Ieave the AccumuIatoi hoIding the vaIue 69H (01101001B).
When the destination is a diiectIy addiessed byte, this instiuction can compIement combina-
tions of bits in any RAM Iocation oi haidwaie iegistei. The pattein of bits to be compIement-
ed is then deteimined by a mask byte, eithei a constant contained in the instiuction oi a
vaiiabIe computed in the AccumuIatoi at iun-time. The instiuction,
XRL P1,00110001B
wiII compIement bits 5, 4, and 0 of output Poit 1.
71
XRL ARn
Bytes 1
Cycles 1
Operation XRL
(A)w(A) I (Rn)
XRL Adirect
Bytes 2
Cycles 1
Operation XRL
(A)w(A) I (diiect)
XRL A
Ri
Bytes 1
Cycles 1
Encoding 0 1 1 0 0 1 1 i
Operation XRL
(A)w(A) I ((Ri))
XRL Adata
Bytes 2
Cycles 1
Operation XRL
(A)w(A) I data
XRL directA
Bytes 2
Cycles 1
Operation XRL
(diiect)w(diiect) I (A)
72
XRL directdata
Bytes 3
Cycles 2
Operation XRL
(diiect)w(diiect) I data
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73

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Novembei 1992

Ri - 8-bit inteinaI data RAM Iocation (0

Ri Add indirect RAM 1 12

AaDPTR Move Code 1 24

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