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Peter-Michael Seidel Southern Methodist University Computer Sci&Eng Department Dallas, TX, 75275 seidel@seas.smu.edu Guy Even Tel-Aviv University Electrical Engineering Department Tel-Aviv 69978, Israel guy@eng.tau.ac.il
Abstract
We present an IEEE oating-point adder (FP-adder) design. The adder accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly normalized rounded sum/difference in the format required by the IEEE Standard. The latency of the design for double precision is roughly logic levels, not including delays of latches between pipeline stages. Moreover, the design can be easily partitioned into stages consisting of logic levels each, and hence, can be used with clock periods that allow for logic levels between latches. The FP-adder design achieves a low latency by combining various optimization techniques such as: a non-standard separation into two paths, a simple rounding algorithm, unifying rounding cases for addition and subtraction, sign-magnitude computation of a difference based on ones complement subtraction, compound adders, and fast circuits for approximate counting of leading zeros from borrow-save representation. A comparison of our design with other implementations suggests a reduction in the latency by at least two logic levels as well as simplied rounding implementation. A reduced precision version of our algorithm has been veried by exhaustive testing.
An extended abstract of this work titled On the design of fast IEEE Floating-Point Adders will appear in the Proceedings of the 15th International Symposium on Computer Arithmetic (Arith15), 2001, US patent pending.
2 Notation
Values and their representation. We denote binary strings in upper case letters (e.g. S,E ,F ). The value repre). sented by a binary string is represented in italics (e.g. IEEE FP-numbers. We consider normalized IEEE FP-numbers. In double precision IEEE FP-numbers are represented by three elds S E F with sign bit S , exponent string E and signicand string F . The values of exponent and signicand are dened by:
. A FP-number S E F represents
2. E denotes the exponent string. The value represented by an exponent string E that is not all zeros or all ones is E
3. F denotes the signicand string that represents a fraction in the range (we do not deal here with denormalized numbers or zero). When representing signicands, we use the convention that bit positions to the right of the binary point have positive indices and bit positions to the left of the binary point have negative indices. Hence, the value represented by is
is S
S E F
Factorings. Given an IEEE FP-number S E F , we refer to the triple as the factoring of the FP-number. Note that S since S is a single bit. The advantage of using factorings is the ability to ignore representation details and focus on values. Inputs. The inputs of a FP-addition/subtraction are: 1. operands denoted by SA EA FA and SB EB FB ; 2. an operation SOP
where SOP
denotes a subtraction;
3. IEEE rounding mode. Output. The output is a FP-number S E F . The value represented by the output equals the IEEE rounded value of
SA EA FA
SOP SB EB FB
Manipulated operands. During FP-addition, the signicands of the operands are aligned, negated, pre-shifted, etc. We append letters to signals to indicate the manipulations that take place and the source of the signal as follows: 1. FS denotes the signicand string of the smaller operand. 2. FL denotes the signicand string of the larger operand. 3. An O denotes the ones complement negation (e.g. FAO denotes the string obtained by the inversion of all the bits of FA ). 4. A P denotes a pre-shift by one position to the left. This shift takes place in effective subtraction. 5. An apostrophe () denotes a shift by one position to the right (i.e. division by ). This shift takes place in the case of a positive large exponent difference to compensate for the ones complement subtraction of the exponents. 6. An A denotes the alignment of the signicand (e.g. FSOA is the outcome of aligning FSO ). We prex the following symbols to indicate the meaning of the signals: 1. The prex abs means the absolute value. (e.g. abs FSUM is the absolute value of FSUM ). 2. The prex xed means that the LSB of the signicand has been xed to deal with the discrepancy between round to nearest even (RNE) and round to nearest up (RNU) (see Sec. 4.3). 3. The prex r means rounded. 4. The prex norm when applied to a signicand means that the signicand is normalized to the range . 5. The prex pswhen applied to a signicand means that the signicand is post-normalized to the range .
SOP
Let S . EFF SOP . The case that S . EFF is called effective addition and the case that S . EFF is called effective subtraction. . The large operand, , and the small operand, We dene the exponent difference , are dened as follows:
SOP
SOP
if otherwise if otherwise.
S . EFF
To simplify the description of the datapaths, we focus on the computation of the results signicand, which is assumed to be normalized (i.e. in the range ). The signicand sum is dened by
S . EFF
The signicand sum is computed, normalized, and rounded as follows: 1. exponent subtraction:
2. operand swapping: compute , , and , 3. limitation of the alignment shift amount: equal to , 4. alignment shift of : 5. signicand negation: fsan 6. signicand addition: fsum 7. conversion: abs fsum 8. normalization n fsum
S . EFF ,
fsan,
fsum. The sign S of the result is dermined by S fsum
abs fsum,
9. rounding and post-normalization of n fsum. The naive FP-adder implements the steps from above sequentially, where the delay of steps rithmic in the signicands length. Therefore, this is a slow FP-adder implementation. is loga-
4 Optimization Techniques
In this section we outline optimization techniques that were employed in the design of our FP-adder.
S . EFF OR
OR
(1)
The outcome of the R-path is selected for the nal result if IS R selected. This partitioning has the following advantages: 4
1. In the R-path, the normalization shift is limited to a shift by one position (in Sec. 4.2 we show how the normalization shift may be restricted to one direction). Moreover, the addition or subtraction of the signicands in the R-path always results with a positive signicand, and therefore, the conversion step can be skipped. 2. In the N-path, the alignment shift is limited to a shift by one position to the right. Under the assumptions of the N-path, the exponent difference is in the range . Therefore, a -bit subtraction sufces for extracting the exponent difference. Moreover, in the N-path, the signicand difference can be exactly represented with bits, hence, no rounding is required. Note that the N-path applies only to effective subtractions in which the signicand difference is less than . Thus, in the N-path it is assumed that . The advantages of our partitioning criterion compared to the exponent difference criterion stem from the following two observations: (a) a conventional implementation of a far path can be used to implement also the R-path; and (b) the N-path is simpler than the near path since no rounding is required and the N-path applies only to effective subtractions. Hence, we were able to implement the N-path simpler and faster than the near-path presented in [23].
Note, that based on the signicand sum fpsum, which includes the conditional pre-shift, the path selection condition can be rewritten as
IS R
S . EFF OR
OR
(2)
In the rounding implementation in the R-path, the three rounding modes RZ, RNU and RI are further reduced to truncation using injection based rounding [7]. The reduction is based on adding an injection that depends only X X X X denote the binary representation of a signicand with the value on the rounding mode. Let X X for which (double precision rounding is trivial for ), then the injection is dened by: if RZ INJ if RNU if RI For double precision and equation:
X
X INJ
(3)
).
The
B if A A B if A
A
B B
B . We refer
The actual computation proceeds as follows: The binary string D is computed such that D to D as the ones complement lazy difference of A and B. We consider two cases:
1. If the difference is positive, then D is off by an ulp and we need to increment D . However, to save delay, we avoid the increment as follows: (a) In the case of the exponent difference that determines the amount of the alignment shift, the signicands are pre-shifted by one position to compensate for the error. (b) In the case of the signicand difference, the missing ulp is provided by computing the incremented sum of A and B using a compound adder. 2. If the exponent difference is negative, then the bits of D are negated to obtain an exact representation of the magnitude of the difference.
Technique. We follow the technique suggested by Tyagi [26] for implementing a compound adder. This technique is based on a parallel prex adder in which the carry-generate and carry-propagate strings, denoted by and , are computed [4]. Let equal the carry bit that is fed to position . The bits of the sum of the addends and are obtained as usual by:
XOR
XOR
or
Application. There are two instances of a compound adder in our FP-addition algorithm. One instance appears in the second pipeline stage of the R-path where our delay analysis relies on the assumption that the MSB of the sum is valid one logic level prior to the slowest sum bit. The second instance of a compound adder appears in the N-path. In this case we also address the problem that the compound adder does not t in the rst pipeline stage according to our delay analysis. We break this critical path by partitioning the compound adder between the rst and second pipeline stages as follows: A parallel prex adder placed in the rst pipeline stage computes the carry-generate and carry-propagate signals as well as the bitwise XOR of the addends. From these three binary strings the sum and incremented sum are computed within two logic levels as described above. However, these two logic levels must belong to different XOR and pipeline stages. We therefore compute rst the three binary strings , or which are passed to the second pipeline stage. In this way the computation of the sum is already completed in the rst pipeline stage and only an XOR-line is required in the second pipeline stage to compute also the incremented sum.
1. If
satises:
2. If
satises:
The implication of Claim 1 is that after -recoding, the number of leading zeros in the borrow-save encoded string F (denoted by in the claim) can be used as the normalization shift amount to bring the normalized result into one of two binades (i.e. in the positive case either or , and in the negative case after negation either or ). We implemented this technique so that the normalized signicand is in the range as follows: F . (See signal in Fig. 7). (1.) In the positive case, the shift amount is F . (See signal in Fig. 7). (2.) In the negative case, the shift amount is
into two paths for medium and large exponent differences. A detailed block diagram for the implementation of the rst cycle of the R-path is depicted in gure 5. The input to the second pipeline stage consists of the signicand of the larger operand and the aligned significand of the smaller operand which is inverted for effective subtractions. The goal is to compute their sum and round it while taking into account the error due to the ones complement representation for effective subtractions. The second pipeline stage is very similar to the rounding algorithm presented in our companion paper [7]. The signicands are divided into a low part and a high part that are processed in parallel. The low part computes the LSB of the nal result based on the low part and the range of the sum. The high part computes the rest of the nal result (which is either the sum or the incremented sum of the high part). The outputs of the compound adder are post-normalized before the rounding selection is performed. A detailed block diagram for the implementation of the second cycle of the R-path is depicted in gure 6. N-Path. The N-path works under the assumption that an effective subtraction takes place, the signicand difference (after the swapping of the addends and pre-shifting) is less that and the absolute value of the exponent difference is less than . The N-path has the following properties: 1. The exponent difference must be in the set . Hence, the exponent difference can be computed by subtracting the two LSBs of the exponent strings. The alignment shift is by at most one position. This is implemented in the exponent difference prediction box. 2. An effective subtraction takes place, hence, the signicand corresponding to the subtrahend is always negated. We use ones complement representation for the negated subtrahend. 3. The signicand difference (after swapping and pre-shifting) is in the range and can be exactly represented using bits to the right of the binary point. Hence, no rounding is required. Based on the exponent difference prediction the signicands are swapped and aligned by at most one bit position in the align and swap box. The leading zero approximation and the signicand difference are then computed in parallel. The result of the leading zero approximation is selected based on the sign of the signicand difference according to Sec. 4.6 in the leading zero selection box. The conversion box computes the absolute value of the difference (Sec. 4.4) and the normalization & post-normalization box normalizes the absolute signicand difference as a result of the N-path. Figure 7 depicts a detailed block diagram of the N-path.
5.2 Specication
In this section we specify the computations in the two computation paths. We describe the specication separately for the 1st stage and for the 2nd stage of the R-path and for the N-path: 5.2.1 R-path 1st cycle
,
The computation performed by the rst pipeline stage in the R-path outputs the signicands and represented by FLP and FSOPA . The signicands and are dened by
if S . EFF otherwise.
Figure 3 depicts how the computation of FLP and FSOPA is performed. For each box in Fig. 2, a region surrounded by dashed lines is depicted to assist the reader in matching the regions with blocks.
SIGN MED
S . EFF
pre-shift (left)
align-shift (right)
FSOP
1 1 0 0
according to Fig. 3.
1. The exponent difference is computed for two ranges: The medium exponent difference interval consist of , and the big exponent difference intervals consist of and . The outputs of the exponent difference box are specied as follows: Loosely speaking, the SIGN MED and MAG MED are the sign-magnitude representation of , if is in the medium exponent difference interval. Formally,
SIGN MED
MAG MED
if if dont-care otherwise
The reason for missing by in the positive case is due to the ones complement subtraction of the exponents. This error term is compensated for in the Align1 box. 2. SIGN BIG is the sign bit of exponent difference . IS BIG is a ag dened by:
IS BIG
or if otherwise
positions. Since all 3. In the big exponent difference intervals, the required alignment shift is at least positions or more are equivalent (i.e. beyond the sticky-bit position), we may limit alignment shifts of the shift amount in this case. In the Align2 region one of the following alignment shift occurs: (a) a xed alignment shift by positions in case the exponent difference belongs to the big exponent difference intervals (this alignment ignores the pre-shifting altogether); or (b) an alignment shift by mag med positions in case the exponent difference belongs to the medium exponent difference interval. 4. In the Ones Complement box, the signals FAO,FBO , and S . EFF are computed. The FAO and FBO signals are dened by
FAO
FBO
FB FA FB
FA
if S . EFF otherwise.
5. The computations performed in the Pre-shift & Align 1 region are relevant only if the exponent difference is in the medium exponent difference interval. The signicands are pre-shifted if an effective subtraction . Table 1 takes place. After the pre-shifting, an alignment shift by one position takes place if summarizes the specication of FSOP . . The subtrahend is selected for the medium 6. In the Swap region, the minuend is selected based on exponent difference (based on ) interval and for the large exponent difference interval (based on ). 7. The Pre-shift 2 region deals with pre-shifting the minuend in case an effective subtraction takes place. 10
5.2.2
The input to the second cycle consists of: the sign bit SL , a representation of the exponent , the signicand strings FLP and FSOPA , and the rounding mode. Together with the sign bit SL , the rounding mode is reduced to one of the three rounding modes: RZ, RNE or RI (see Sec. 4.3). The output consists of the sign bit SL , the exponent string (the computation of which is not discussed here), and the normalized and rounded signicand f far represented by F FAR . If the signicand sum (after pre-shifting) is greater than or equal to , then the output of the second cycle of the R-path satises:
S . EFF
f far
Note that in effective subtraction, is added to correct the sum of the ones complement representations to the sum of twos complement representations by the lazy increment from the rst clock cycle. Figure 3 depicts the partitioning of the computations in the 2nd cycle of the R-path into basic blocks and species the input- and output-signals of each of these basic blocks. 5.2.3 N-Path.
A block diagram of the N-path and the central signals are depicted in Fig. 4. 1. The Small Exponent Difference box outputs DELTA which represents in twos complement the difference . 2. The input to the Small Signicands: Select, Align, & Pre-shift box consists of the inverted signicand strings FAO and FBO . The selection means that if the exponent difference equals , then the subtrahend corresponds to FA, otherwise it corresponds to FB . The pre-shifting means that the signicands are preshifted by one position to the left (i.e. multiplied by ). The alignment means that if the absolute value of the exponent difference equals , then the subtrahend needs to be shifted to the right by one position (i,e, divided by ). The output signal FSOPA is therefore specied by
FSOPA
FA if FB if FB if
and the sign-bit of the 3. The Large Signicands: Select & Pre-shift box outputs the minuend FLP addend it corresponds to. The selection means that if the exponent difference equals , then the minuend corresponds to FB , otherwise it corresponds to FA. The pre-shifting means that the signicands are preshifted by one position to the left (i.e. multiplied by ). The output signal FSOPA is therefore specied by FB SB if FLP SL FA SA if
11
4. The Approximate LZ count box outputs two estimates, of the number of leading zeros in the binary representation of . The estimates satisfy the following property:
if if
5. The Shift Amount Decision box selects the normalization shift amount between and depending on the sign of the signicand difference as follows:
if if
6. The Signicand Compound Add boxes parts and together with the Conversion Selection box compute . The magnitude of is represented by the the sign and magnitude of binary string FPSUM and the sign of the sum is represented by FOPSUMI . The method of how the sign and magnitude are computed is described in Sec. 4.4.
by positions to the left, 7. The Normalization Shift box shifts the binary string FPSUM padding in zeros from the right. The normalization shift guarantees that norm fpsum is in the range .
8. The Post-Normalize outputs f near that satises: f near norm fpsum if norm fpsum norm fpsum if norm fpsum
SOP SA
SB
FB[0:52]
FA[0:52]
11 00
XOR
S.EFF
11 00 XOR XOR 11 11 00 00 11 11 00 00
XOR
2LL 3LL
FBO[0:52]
XOR
XOR
3LL
FAO[0:52]
Figure 1. Implementation of the Ones Complement box annotated with timing estimates.
3. The following condition is computed during the computation of the exponent difference
IS R
which will be used later for the selection of the valid path. Note that the exponent difference is computed using ones complement representation. This implies that the magnitude is off by one when the exponent difference is positive. In particular, the case of the exponent difference equal to yields a magnitude of and a sign bit of . This is why the expression andMAG MED notSIGN BIG appears in the OR-tree used to compute the IS R signal. Delay Analysis. assumptions: The annotation in Fig. 5 depicts our delay analysis. This analysis is based on the following
1. The delay associated with buffering a fan-out of is one logic level. 2. The delays of the outputs of the Ones Complement box are justied in Fig. 1. 3. The delay of a -bit adder is logic levels. Note that it is important that the MSB be valid after logic are valid after logic levels and after that levels. We can relax this assumption by requiring that bits two more bits become valid in each subsequent logic level. This relaxed assumption sufces since the right shifter does not need all the control inputs simultaneously. 4. The delay of the second -bit adder is logic levels even though the carry-in input is valid only after logic levels. This can be obtained by computing the sum and the incremented sum and selecting the nal sum based on the carry-in (i.e. carry select adder). 5. The delay of a -bit OR-tree is two logic levels. 6. The delay of the right shifter is and using - muxes. logic levels. This can be achieved by encoding the shift amount in pairs
Detailed Description. Our implementation of the R-path in the 2nd cycle consists of two parallel paths called the upper part and the lower part. The upper part deals with positions of the signicands and the lower part deals with positions of the signicands. The processing of the lower part has to take into account two additional values: the rounding injection, which depends only on the reduced rounding mode, and the missing ulp ( ) in effective subtraction due to the ones complement representation. The processing of FSOPA INJ and S . EFF is based on:
TAIL
FSOPA
FSOPA
The bits
are dened by
ORTAIL TAIL TAIL TAIL TAIL
The bits and are computed by using a -bit injection string. We distinguish between effective addition and effective subtraction. 1. Effective addition. Let denote the sticky bit that corresponds to FSOPA
ORFSOPA FSOPA
, then
2. Effective subtraction. In this case we still have to add to FSOPA the missing that we neglected to add in the binary during the rst cycle. Let denote the sticky bit that corresponds to bit positions , then representation of FSOPA
ORNOT FSOPA
NOT FSOPA
The addition of can create a carry to position which we denote by . The value of is creates a carry that ripples to position is all ones, in which case the addition of one iff FSOPA . Therefore, NOT . Again, the injection can be restricted to two bits INJ , and we by adding compute
FSOPA INJ
NOT
, because
proceeds as follows. Let in effective addition, A fast implementation of the computation of in effective subtraction. Based on S . EFF FSOPA and INJ , the signals are and computed in two paths: one assuming that and the other assuming that . Fig. 6 depicts a naive method of computing the sticky bit to keep the presentation structured rather than is performed by XOR-ing the obscure it with optimizations. A conditional inversion of the bits of FSOPA bits with S . EFF . The possibly inverted bits are then input to an OR-tree. This suggestion is somewhat slow and during the costly. A better method would be to compute the OR and AND of (most of) the bits of FS
14
alignment shift in the rst cycle. The advantages of advancing (most of) the sticky bit computation to the rst cycle is twofold: (a) There is ample time during the alignment shift whereas the sticky bit should be ready after at most logic levels in the second cycle; and (b) This saves the need to latch all bits (corresponding to FS ) between the two pipeline stages. The upper part computes the correctly rounded sum (including post-normalization) and uses for the computation . The rest of the algorithm is identical to the rounding the strings FLP FSOPA , and algorithm presented, analyzed, and proven in [7] for FP multimpication. Delay Analysis. The annotation in Fig. 6 depicts our delay analysis. This is almost identical to the delay analysis of the multiplication rounding algorithm in [7]. In this way also the 2nd cycle of the R-path implementation has a delay of logic levels, so that the whole R-path requires a delay of logic levels between the latches.
6.3 N-path
Figure 7 depicts a detailed block diagram of the N-path. The non-straightforward boxes are described below. Detailed Description. 1. The region called Path Selection Condition 2 computes the signal IS R2 which signals whether the magnitude of the signicand difference (after pre-shifting) is greater than or equal to . This is one of the clauses need to determine if the outcome of the R-path should be selected for the nal result. 2. The implementation of the Approximate LZ Count box deserves some explanations. (a) The PN-recoding creates a new digit in position . This digit is caused by the negative and positive carries. Note that the P-recoding does not generate a new digit in position . (b) The PENC boxes refer to priory encoders; they output a binary string that represents the number of leading zeros in the input string. (c) How is LZP 2 computed? Let denote the number of leading zeros in the output of the -bitwise XOR. Claim 1 implies , then . The reason for this is (using the terminology that if of Claim 1) that the position of the digit equals . We propose to bring to position (recall that an additional multiplication by is used to bring the positive result to the range ). Hence a shift is derived by computing . (d) How is LZP 1 computed? If by positions is required and LZP 2 . The reason for this is that we , then Claim 1 implies that propose to bring to position (recall that an additional multiplication by is used to bring the negative is computed by result to the range ). Hence a shift by positions is required and LZP 1 counting the number of leading zeros in positions of the outcome of the -bitwise XOR. Delay Analysis. For the N-path the timing estimates are annotated in the block diagram in gure 7. Corresponding to this delay analysis the latest signals in the whole N-path are valid after logic levels, so that this path is not time critical. The delay analysis depicted in Fig. 7 suggests two pipeline borders: one after logic levels and one after logic levels. As already discussed in section 4.5, a partitioning after logic levels requires to partition the implementation of the compound adder between two stages. This can be done with the implementation of the compound adder from section 4.5, so that we get a rst stage of the N-path that is valid after logic levels and a second stage of the N-path where the signals are valid after logic levels. This leaves some time in the second stage for routing the N-path result to the path selection mux in the R-path.
15
S . EFF OR IS R OR
S . EFF OR IS R OR
(4)
We dene IS R
S . EFF IS R, so that
IS R S . EFF OR IS R OR IS R
Because the assumptions S . EFF and IS R are exactly the assumptions that we use during the computation of in the N-path, the condition IS R is easily implemented in the N-path by the bit at position of the absolute signicand difference. The condition IS R and the signal S . EFF are computed in the R-path. After IS R is computed from the three components according to equation 4, the valid result is selected either from the R-path or the N-path accordingly. Because the N-path result is valid a few logic levels before the R-path result, the path selection can be integrated with the nal rounding selection in the R-path. Hence, no additional delay is required for the path selection and the overall implementation of the oating-point adder can be realized in logic levels between the pipeline stages.
levels. Even with this optimization our algorithm is to be partitioned into two pipeline stages with logic levels between latches, although the rst stage then only requires logic levels. Although many of the designs use two paths for the computations, not in every case these two paths really refer to one path with a simplied alignment shift and the other path with a simplied normalization shift and without the need to complement the signicand sum like originally suggested by [8]. In some cases the two paths are just used for different rounding cases. In other cases rounding is not dealt with in the two paths at all, but computed in a separate rounding step that is combined for both paths after the sum is normalized. These implementations can be recognized in table 2 by the fact that they do not pre-compute the possible rounding results and only have to consider one result binade to be rounded. Among the two-path implementations from literature there are mainly three different path selection conditions:
The rst group uses the original path selection condition from [8] which is only based on the absolute and a near-path is selected for value of the exponent difference. A far-path is then selected for . This path selection condition is used by the implementations from [3, 14, 18, 21, 23]. All of them have to consider four different result binades for rounding. A second version of the path selection condition is used by [17]. In this case the far path is additionally used for all effective additions. This allows to unconditionally negate the smaller operand in the near-path. Also this implementation has to consider four different result binades for rounding. In the implementation of [10] a third version of the path selection condition is used. In this case additionally the cases where only a normalization shift by at most one position to the right or one position to the left are computed in the far-path. In this way, the design could get rid of the rounding in the near-path. Still there are three different result binades to be considered for rounding and normalization in the far-path of this implementation.
Our path selection condition is different from these three and was developed independently from the later two. Its advantages are described in section 4.1. Not only that by our path selection condition no additions and no rounding have to be considered in the near path. We were also able to reduce the number of binades to that have to be considered for rounding and normalization in the far path. As shown in section 5 there is a very simple implementation for the path selection condition in our design that only requires very few gates to be added in the R-path. Beside the implementation in two paths, the optimization techniques most commonly used in previous designs are: the use of ones complement negation for the signicand, the parallel pre-computation of all possible rounding results in an upper and a lower part, and the parallel approximate leading zero count for an early preparation of the normalization shift. Especially for the leading zero approximation there are many different implementations suggested in literature. The main difference of our algorithm for leading zero approximation is that it operates on a borrow-save encoding with Recodings. Its correctness can be proven very elegantly based on bounds of fraction ranges. We pick two from the implementations that are summarized in table 2 and describe them in detail: (a) an implementation based on the 2000 patent [17] from AMD and (b) an implementation based on the 1998 patent [10] from SUN. The union of the optimization techniques used by these two implementation to reduce delay form a superset of the main optimization techniques from the previously published designs. Only our proposed designs add some additional optimization techniques to reduce delay and to simplify the design as pointed out in the table 2. Therefore, it is likely that the AMD design and the SUN design are the fastest implementations that were previously published. For this reason we have chosen to analyze and compare their latency with the latency of our design. Although some of the other designs additionally address other issues like for example [20, 24] try to reduce cost by sharing hardware between the two paths or like [16] demonstrates an implementation following the
17
pipelined-packet forwarding paradigm, these implementations are not optimized for speed and do not belong to the fastest designs. We therefore do not further discuss them in this study.
Figure 9 depicts a block diagram of this adopted design. This gure is annotated with timing estimates. For this estimate we assume the modied CP adder to have a delay of logic levels as discussed above. In this way our delay analysis suggests, that the adopted FP-adder implementation corresponding to the SUN patent has a delay of logic levels. In this case the implementation of the rst stage is not very fast and requires logic levels. Thus, in comparison with our design, the FP-adder implementations corresponding to the AMD patent and corresponding to the SUN patent both seem to be slower by at least two logic levels. Additionally, they have a more complicated IEEE rounding implementation and can not as easy be partitioned into two balanced stages as our design. Because the two implementations were chosen to be the fastest from literature, our implementations seem to be the fastest FP-adder implementations published to date.
Acknowledgements
We would like to thank Shahar Bar-On and Yariv Levin for running their verication procedure on our design. Shahar and Yariv used this procedure to nd counter examples to a previous version of our algorithm. They suggested simple xes, and ran the verication procedure again to support the correctness of the algorithm presented in this paper.
References
[1] S. Bar-Or, Y. Levin, and G. Even. On the delay overheads of the supporting denormal inputs and outputs in oating point adders and multipliers. in preparation. [2] S. Bar-Or, Y. Levin, and G. Even. Verication of scalable algorithms: case study of an IEEE oating point addition algorithm. in preparation. [3] A. Beaumont-Smith, N. Burgess, S. Lefrere, and C.C. Lim. Reduced latency IEEE oating-point standard adder architectures. Proc. 14th Symp. on Computer Arithmetic, 14, 1999. [4] R.P. Brent and H.T. Kung. A Regular Layout for Parallel Adders. IEEE Trans. on Computers, C-31(3):260 264, Mar. 1982. [5] M. Daumas and D.W. Matula. Recoders for partial compression and rounding. Technical Report RR97-01, Ecole Normale Superieure de Lyon, LIP, 1996. [6] L.E. Eisen, T.A. Elliott, R.T. Golla, and C.H. Olson. Method and system for performing a high speed oating point add operation. IBM Corporation, U.S. patent 5790445, 1998. [7] G. Even and P.-M. Seidel. A comparison of three rounding algorithms for IEEE oating-point multiplication. IEEE Transactions on Computers, Special Issue on Computer Arithmetic, pages 638650, July 2000. [8] P.M. Farmwald. On the design of high performance digital arithmetic units. PhD thesis, Stanford Univ., Aug. 1981. [9] P.M. Farmwald. Bifurcated method and apparatus for oating-point addition with decreased latency time. U.S. patent 4639887, 1987. [10] V.Y. Gorshtein, A.I. Grushin, and S.R. Shevtsov. Floating point addition methods and apparatus. Sun Microsystems, U.S.patent 5808926, 1998. [11] IEEE standard for binary oating point arithmetic. ANSI/IEEE754-1985.
19
[12] T. Ishikawa. Method for adding/subtracting oating-point representation data and apparatus for the same. Toshiba,K.K., U.S. patent 5063530, 1991. [13] T. Kawaguchi. Floating point addition and subtraction arithmetic circuit performing preprocessing of addition or subtraction operation rapidly. NEC, U.S. patent 5931896, 1999. [14] T. Nakayama. Hardware arrangement for oating-point addition and subtraction. NEC, U.S. patent 5197023, 1993. [15] K.Y. Ng. Floating-point ALU with parallel paths. Weitek Corporation, U.S. patent 5136536, 1992. [16] A.M. Nielsen, D.W. Matula, C.-N. Lyu, and G. Even. IEEE compliant oating-point adder that conrms with the pipelined packet-forwarding paradigm. IEEE Transactions on Computers, 49(1):3347, Jan. 2000. [17] S. Oberman. Floating-point arithmetic unit including an efcient close data path. AMD, U.S. patent 6094668, 2000. [18] S.F. Oberman, H. Al-Twaijry, and M.J. Flynn. The SNAP project: Design of oating point arithmetic units. In Proc. 13th IEEE Symp. on Comp. Arith., pages 156165, 1997. [19] W.-C. Park, T.-D. Han, S.-D. Kim, and S.-B. Yang. Floating Point Adder/Subtractor Performing IEEE Rounding and Addition/Subtraction in Parallel. IEICE Transactions on Information and Systems, E79D(4):297305, 1996. [20] N. Quach and M. Flynn. Design and implementation of the SNAP oating-point adder. Technical Report CSL-TR-91-501, Stanford University, Dec. 1991. [21] N. Quach, N. Takagi, and M. Flynn. On fast IEEE rounding. Technical Report CSL-TR-91-459, Stanford, Jan. 1991. [22] P.-M. Seidel. On The Design of IEEE Compliant Floating-Point Units and Their Quantitative Analysis. PhD thesis, University of the Saarland, Germany, December 1999. [23] P.-M. Seidel and G. Even. How many logic levels does oating-point addition require? In Proceedings of the 1998 International Conference on Computer Design (ICCD98): VLSI in Computers & Processors, pages 142149, Oct. 1998. [24] H.P. Sit, D. Galbi, and A.K. Chan. Circuit for adding/subtracting two oating-point operands. Intel, U.S.patent 5027308, 1991. [25] D. Stiles. Method and apparatus for performing oating-point addition. AMD, U.S. patent 5764556, 1998. [26] A. Tyagi. A Reduced-Area Scheme for Carry-Select Adders. IEEE Transactions on Computers, C-42(10), October 1993. [27] H. Yamada, F. Murabayashi, T. Yamauchi, T. Hotta, H. Sawamoto, T. Nishiyama, Y. Kiyoshige, and N. Ido. Floating-point addition/subtraction processing apparatus and method thereof. Hitachi, U.S. patent 5684729, 1997.
20
R path
significand 1s compl
N path
exponent difference prediction align &
11 00 11 00
exponent difference
align1
swap
align2
11 00 11 00
rounding decision
Figure 2. High level structure of the new FP addition algorithm. Vertical dashed line separates two pipelines: R-path and N-path. Horizontal dashed line separates the two pipeline stages.
21
EA[10:0]
EB[10:0]
FA[0:52]
FB[0:52]
SA
SB
SOP S.EFF
FAO[0:52]
11 00
FBO[0:52]
11 00 11 00
S.EFF ) S.EFF S.EFF )
FAOP[1:52]
FBOP[1:52]
11 00
FAOP[1:53]
FBOP[1:53]
FA[0:52] FB[0:52] SA SB
Swap
FAO[0:52]
SIGN_BIG
FBO[0:52]
Swap Mux
FSOP [1:53]
Swap Mux
FSO[0:52]
1 0 1 0
Swap Mux
SC
Max Shift
FL[0:52]
Preshift2 PreshiftL
S.EFF
FSOA.big[1:116]
IS_BIG
FLP[1:52]
to path selection
FLP[1:52]
11 00 11 00
FSOPA[1:52]
FSOPA[53:116]
XSUM[52]
S.EFF RND_MODE
FOSUMI[1:51]
11 00
FOSUM[1:51]
[1]
RND_MODE
Postnorm Shift
ps_FOSUMI[0:51]
Rounding Decision
FOSUM[51] FOSUMI[51]
ps_FOSUM[0:51] ps_FOSUMI[52]
ps_FOSUM[52] RINC
Rounding Selection
F_FAR[0:52]
22
EA[1:0]
EB[1:0]
FA[0:52]
FB[0:52]
Approx. LZ Count
LZ1[5:0]
Conversion Selection
LZ1[5:0] LZ2[5:0] LZ[5:0]
abs_FPSUM[-1:52]
Normalization Shift
norm_FPSUM[-1:52]
Post-Normalize
F_NEAR[0:52]
23
large
0,EB[10:7] 0,EA[10:7]
medium
EA[6:0] EB[6:0] FA[0:52] SA SOP SB FB[0:52]
1s complement
1s complement
Adder(7) Adder(5)
carry in
DELTA[11:7] [11] [10:7] SIGN_BIG DELTA[6:0]
4LL [6]
SIGN_MED [5:0]
3LL
Align 1
small
4LL FBOP
[0:53]
3LL
Swap
SIGN_BIG
large
1 0 4LL
5LL
Mux
Mux
0
FA[0:52] SA
5LL
FB[0:52] SB
11 00
XOR
FSOP[-1:53]
FSO[0:53]
XOR
7LL [10:6]
MAG_MED[5:0] [5:1]
1 0 1 0
5LL
6LL
7LL
S.EFF 64
ShiftR(63)
sign extend with s.eff
FSOPA.med [-1:116]
Mux
1
5LL
SL
FL[0:52]
ORtree
9LL
ORtree
IS_BIG
11LL
FSOPA.big [-1:116]
7LL
7LL
small
OR
IS_R1
1 0
Mux
1
large
12LL FSOPA[-1:116]
1 0 1 0
ShiftL(1)
S.EFF
8LL FLP[-1:52]
1 0 1 0
Exponent Difference
Align 2
Figure 5. Detailed block diagram of the 1st clock cycle of the R-path annotated with timing estimates (5LL next to a signal means that the signal is valid after 5 logic levels).
24
52 53
low
[53]
RI,RNE
HA(54)
1LL XSUM[-1:52] XCARRY[-1:51] 1LL
compute C[52],R,S
(S=0) (S=1)
XOR
1LL
OrTree(63) 0 MUX 1
1LL XSUM[52] C[52],R,S 5LL S 6LL RI RNE
Compound Adder(53)
FPOSUMI FPOSUM [-1:51] [-1:51] [-1:51] [-1:51] [-1] 10LL [-1] 9LL
FPOSUM[51] FPOSUMI[51]
Rounding Decisions
SIG-OVF RINC L(ninc) 10LL FPOSUM [-1] L(ninc) 9LL 10LL
Rounding Decision
L(inc)
FPOSUM[-1]
10LL
+Fix LSB
FPOSUMI [-1]
ShiftR
11LL
ShiftR
11LL
MUX 0
MUX 1
11LL
MUX
MUX
12LL
F.FAR[0:51]
F.FAR[52]
Figure 6. Detailed block diagram of the 2nd clock cycle of the R-path annotated with timing estimates.
25
EA[1:0]
EB[1:0]
FB[0:52]
FA[0:52]
1s Compl
1 2bit ADD
DELTA[1] 2 LL DELTA[0] 1 LL 1
INV(53)
FBO[0:52]
INV(53)
1 LL 1 FAO[0:52]
FBO[0:52]
1 0
1 LL
SA,FA[0:52]
SB,FB[0:52]
MUX 0
3 LL 1 FAO[0:52]
0
SL
MUX
4 LL
FLP[1:51]
DELTA[1]
11 00
MUX
4 LL
FSOPA[1:52] +
1 0
PNrecode
6 LL +
XOR(55)
Approx LZ Count
7 LL
11 00 11 00
Significand Addition
[1:52]
PENC(54)
PENC(55)
XNOR
FOPSUM [2:52] 12 LL
11 00
P[1:52] 12 LL
OR
GP_C[1:52] 12 LL 12LL pipeline border
MUX
1
12 LL [1:52]
XOR
FOPSUMI [1:52] 13 LL [1:52] 13LL pipeline border
LZP[5:0] 13 LL
MUX
14 LL
1 0 1 0
FOPSUM[2]
[1]
abs_FPSUM
Normalization +
Postnorm Shift
11 00 11 00
ShiftR(1)
21 LL F_NEAR[0:52] 15 LL IS_R2
Figure 7. Detailed block diagram of the N-path annotated with timing estimates.
26
EA[10:0]
EA[10:0]
EA[10:0]
EB[10:0]
EB[10:0]
EB[10:0]
EA[1:0]
FA[0:52]
FB[0:52]
FA[0:52]
FB[0:52]
FA[0:52] FB[0:52]
EB[1:0]
FA[0:52]
FB[0:52]
1 2LL
11 00
1 0
Alignment Sft(53) 8LL 1 swap 0 large sig
exp pred
11 00 11 11 00 00s.eff 11 00
sft dst ovf
1 0 1 0
1 11 11 11 0 00 00 00 1 11 11 11 0 00 00 00
L1P L0/1P L1P
11 002LL 11 00
10LL 1 large sft dist sel 0 11LL Half Adder Line(53) 12LL Compound Adder(53) sum+1 21LL sum 20LL
Compound Adder(53)
sum 12LL
13LL PENC
1 0
1111 0000
11 00
Figure 8. Block diagram of the AMD FP-adder implementation according to [17] adopted to accept double precision operands and to implement all IEEE rounding modes.
27
[1:0]
[10:0]
[10:0]
[10:0]
[0:52]
[0:52]
[0:52]
[0:52]
[10:0]
[0:52]
[0:52]
[1:0]
[0:52]
s.eff sa,sb,ea,eb,fa,fb
1s compl 1s compl 3LL SWAP small 7LL Shift(55) 14LL HA line 15LL Adder(55) rnd decicions Ps,Gs incl rnd sel 25LL
[-1:49]
eb-ea ea-eb 1 Sticky Sticky for for ea>eb ea<eb Sticky sel
11 00 11 00 11 1 0
0
ea-eb pred
SWAP large
6LL
align_sft_dist[5:0]
11 00
sign( )
SWAP&Align small
SWAP large
11 00 11 00
LZA
rmode
complement sel
[50:54]
Shift(54)
lzero[5:0]
[-1]
Norm-Sft by 1,0 or -1
[-1:0]
Post-normshift
11 00
Figure 9. Block diagram of the SUN FP-adder implementation according to [10] adopted to work only on unpacked normalized double precision operands and to implement all IEEE rounding modes.
28
[0:52]
sa sop sb
fa
fb
fa
fb
ea eb
fa ea eb fb
fa
fb
ea eb
fa
fb
pre-computation of post-normalization
implementation naive design(sec3) Farmwald87 [9] INTEL91 [24] Toshiba91 [12] Stanford Rep91 [21] Weitek92 [15] NEC93 [14] Park etal96 [19] Hitachi97 [27] SNAP97 [18] Seidel/Even98 [23] AMD98 [25] IBM98 [6] SUN98 [10] NEC99 [13] Adelaide99 [3] AMD00 [17] Seidel/Even00(sec5) Seidel/Even00*
X X X X X X X X X X X X
1 1 2 2 1 2 3 1 1 2 2 4 2 2 1 2 2 2 2
X X X X
X X X
X X X X X X X X X X X
X X X X X X X X X X X X X
X X X X X X X X X X X X
X -
X X X
X X X
X X X
X X -
X X -
X X
1 1 3 3 3 1 4 3 1 4 3 1 1 3 1 4 4 2 2
28 24
28 28 26 24 23
29
&
two alignment shifters for