Design of An Ultra High-Speed Voltage Comparator

Jian-feng Wang1 Ji-hai Duan2 School of Information & Communication, Guilin University of Electronic Techno olgy, Gui iln China Abstract-A high speed voltage comparator which can be used in high-speed Flash ADC is designed after considering the speed, offset voltage and other factors. The structure of the preamplifier and compare-Iatch circuit are analyzed .The high speed voltage comparator which consists of a preamplifiera decision stage and an output buffer is based on SMIC 0.18m CMOS process with 1.8V power supply. The simulations result show that the comparator proposed can distinguish 0.3 mV at 1 GHz with a power consumption of only 53.6W. The circuit apply to the high-speed Flash ADC Circuit. Keywords-high-speed ADC, preamplifier; offsets voltage; positive feedback;

1. Introduction
High-speed A / D converter in the signal processing system is an important part of the radar. high-speed broadband digital receivers, and high-speed hard drive is widely used. The highspeed important voltage comparator circuit for factors, directly affects the high speed analog-digital conversion is speed the analog other important modules, it was decided to analog signal processing speed and accuracy of one of the performance of the conversion converter, differential nonlinearity (DNL) and integral nonlinearity (INL) and

key indicators. Therefore, the design of the comparator is the key to high-speed ADC design [1]. Usually are latched comparator comparator ask it through the positive feedback mechanism, the input analog signal and then generate digital signals. CMOS latched comparator can achieve a high conversion rate, but there are a large offset voltage, the converter will limit the accuracy of A/D. Therefore, the speed and latch comparator offset is a contradiction, in order to improve the performance of the comparator requires a compromise between them. This input offset voltage offset by the addition of circuits and low kick back chatter noise reduction circuit, the use of pre-amplification stage, determine the level, the output buffer stage of the structural design of the comparator to reduce the input offset voltage and low kick back chatter sound,

focusing

on analysis

and

optimization and

comparison

of pre-amplifier circuit, Greatly

improves the performance and speed comparator for high-speed Flash ADC circuit [3].

2. Comparator Circuit Design

High-speed comparator used in this structure includes pre-amplification stage, latch and output buffer stage comparative. In order to improve the speed of the comparator, usually preamplifier input signal, to reduce the comparison time, thereby enhancing the sensitivity of the input signal. Comparative amplified latch on to compare the input analog signal, the output buffer stage output compare results. The following sections discuss the specific circuit structure.

2.1 Pre-amplifier stage circuit

In order to improve the conversion rate of the comparator, while reducing the offset voltage, compared with pre-amplifier input signal. In the ultra high-speed comparator, in order to reduce the transmission delay and improve the comparison of the comparator rate, requiring a high bandwidth of the preamplifier, and in order to obtain a certain gain, usually associated with multiple differential amplifier stage. Due to the increased number of amplifiers, will increase the offset voltage of the comparator, but also increase chip area and power consumption, the paper considering the use of two common-source amplifier. Differential amplifier shown in Figure l (a) shows, M1 and M2 form a differential input circuit, can be a strong common-mode rejection to improve the comparator noise suppression capabilities. M5, M6 constitute a diodeconnected load, the amplifier gain:

In the design of the comparator, the differential amplifier does not require a large initial gain, otherwise it will affect the differential amplifier bandwidth, small size of the pipe can be

designed so that the gain is very low, this can save the area and the odd layout of health capacitors. From the formula that the amplifier gain and M1 and M3 of the width to length ratio (W/L) is capacitance Cgs, the directly related to the ratio. This will lead to increased input speed of the comparator. Optimize the circuit in Figure 1

(b) below. Then the differential amplifier gain can be changed to [4]:

By the formula can be obtained after optimization,

the gain can be is proportional to the gain in the same, the lower the ratio of width to length M1 and M2 and M5 and M6 the ratio of width to length ratio, thereby reducing the input capacitance and improve the comparator operating speed. The design by optimizing the differential amplifier, the gain in a certain request, increasing the bandwidth pre-amplifier circuit, thereby reducing the delay, making the comparator speed. The simulation results shown in Figure 2.

2.2 comparative circuit

Latch comparator is the core of the comparison circuit. In this paper, the comparison with the hysteresis effect of the circuit, this circuit can be very good the sound of butterflies on the inhibitory signals of the circuit through the gate of M10 and M9 pipe cross-connected to achieve positive feedback to improve the gain of the circuit judge[5 ]. Circuit shown in Figure 3. Small-signal equivalent model obtained by the comparator propagation delay time constant [6].

Where C is the

= RC, Iss is the tail current source current, gm for the M9, M10 the transconductance, gate-drain capacitance of M9. It can be seen, you can increase

the transconductance gm and gate-drain

capacitance decreased to

reduce

the delay

of the

comparator. In addition, the minimum size can increase the channel length and the tail current.

(a) Differential Amplifiers

(b) After optimization of the differential amplifier Figure1. Differential amplifier before and after optimization

Figure 2: The frequency response of the differential amplifier In this design, the use of parallel latch comparator, the comparator in the clk clock signal under the control of work. Preamplifier output signal into the comparator M7 and M8, M13 is controlled by the clock switching; M9, M10, M11and M12 constitute a positive feedback unit. When the clock signal CLK is high, a relatively state of the comparator to compare the results clock signal CLK is directly from low, the preamplifier output and can decision. When the M13 transistor cut-off, effectively latch output

signal, comparing this time to stop comparing, in the latch state, note the comparison of CLK is low, the input state. Circuit structure shown in Figure 4.

2.3 The output buffer stage circuit design

In this paper, self-biased differential amplifier (self-biasing differential amplifier) as the output buffer stage, while the amplifier output plus four inverter structure, used as an additional gain stage, and the load capacitance and the self bias differential isolation between the amplifier and effectively reduce the bubble errors and comparator metastability effects.

2.4 Overall schematic

Design of the overall high-speed comparator circuit shown in Figure 5. Including pre-amplifier stage, comparative, and the output buffer stage. Pre-amplifier stage amplified differential input signal makes the comparison of comparative time reduction circuit to reduce the overall latency, and reduce the comparator offset voltage.Comparative to pre-amplifier stage compares the input signal and output: the output buffer stage to compare the results of amplification to the digital logic levels.

(a) Comparison of the positive feedback circuit schematic

(b) Small signal equivalent model Figure 3: Compares the circuit schematic and small-signal equivalent model

Figure 4: Comparison of level latch circuit

Figure 5: Compares the overall circuit device

Table 1 compares the reactor core part of the transistor width to length ratio Transistor W / L m / m Transistor W / L m / m

Figure 6: Simulation waveforms

Figure 7 Enter the last bad signal simulation charts

Figure 8: Layout of the comparator

3 Simulation results
Through the above analysis and calculation, simulation and optimization using cadence, and ultimately determine the core part of the comparator transistor width to length ratio (Table 1). In the SMIC 0.18m CMOS process, 1.8 V supply voltage, the comparator designed to cadance true imitation. To test the accuracy of the comparator output, the simulation of a magnitude and polarity of the input time-varying sinusoidal signals shown in Figure 6, the first column is the work of the clock 1 GHz, the input end of the second column is a strong signal v(t):

Other

end

of

the DC in

reference level Figure 7.

is 0.8V. In order

The to

third column verify the

is

the simulation the

waveform output shown

comparator in

worst conditions, functional correctness. Enter a enjoyed the extreme signal change, in the baseline reference voltage 1V, the input signal amplitude of 0.998V, 0.99V, 1.01V, 1.002V case, the minimum accuracy of the comparator 0.3mV, compare the simulation results (Figure. 7) to verify the correctness of the comparator.

4 layout
This layout design is the use of SMIC 0.18m CMOS process in order to effectively inhibit the drift voltage and the even harmonic distortion, and minimize the offset voltage, the comparator comparing the pre-amplifier and latch-level positive feedback MOS mass. Comparator layout shown in Figure 8. transisitor and positive feedback control of the camp with a total of more than painting the center of

5 Conclusion
Based on the SMIC 0.18m CMOS process, the analysis and discussion of the structure of highspeed comparator, and each part of the circuit is optimized. The final design of a clock frequency of high-speed voltage comparator 1GHz. Imitation by cadance true, the clock frequency 1GHz, the input signal for the 150MHz, 20mV signal, the comparator to stabilize the work in time to meet the design specifications, and in the worst conditions, also verified the correctness of the comparator This design can be used in high-speed Flash ADC circuit.

References
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