Te c h n o l o g i e s

Serial ATA IP
Device Controller

SATA Device Controller Integrated with Optional DMA

The Sibridge Technologies Serial ATA (SATA) Device Controller is designed to interface between a host system and a storage device with either solid state or rotating media. The SATA Device Controller decodes incoming host commands and sets up the proper interrupts and status for the local microprocessor to handle ATA and ATAPI commands. The controller can be programmed to automatically transfer the data with minimal firmware support interfaces: a control interface and a direct memory access (DMA) interface. This SATA Device Controller supports either the CoreFrame or the AMBAAHB 2.0 bus interface.

Functional Description
The SATA Device Controller is designed to interface to a device CPU and DMA interface on one end, and the SATA Physical Layer on the other end. The Application Layer Controller, the Transport Layer Controller, and the Link Layer Controller are the three core submodules that control the overall operation. The three controllers coordinate their actions and utilize resources to transfer data between a device system and a SATA Physical Layer such as the MSATA PHY product from Sibridge Technologies. The Link Controller interacts directly with the SATA PHY to coordinate serial transfers. It generates and checks CRC, scrambles/descrambles data, performs encoding/decoding, and manages primitive transmission and receipt. The Transport Layer is used to store the headers of incoming and outgoing packets. Data, Status, and Vendor-specific Packet

SATA Device Core

ABH Slave Interface

AHB Slave Bridge

Paimbus Interface

SATA Host Reset Application Layer (sata_ata)

Headers sent to and from the device are stored in the FIS buffers, which are part of the Transport Layer. The Application Layer decodes incoming host commands and sets

Interrupt Line

Interrupt Controller

AHB Master ABH Master Interface Bridge

DMA Controller

Transport Layer

Link Layer

PHYI Interface

up the proper interrupts and status for the local microprocessor to handle the ATA commands. The hardware will automatically perform the initial handshake with the host during read and write commands.

Serial ATA Device Controller with optional direct memory access controller (DMA). When auto-transfer mode is enabled, read and write transfers can be fully handled by hardware with minimal firmware interaction. Reference Technology Gate Count: 25,000 gates

Major product features:

Compliant with the Serial ATA specification version 2.6 Supports 1.5 Gb/s (150 MB/s) or 3 Gb/s (300 MB/s) speeds Software-compatible with parallel ATA Supports Native Command Queuing (NCQ) Support for Spread Spectrum Clocking (SSC) Auto-read and auto-write Integrated DMAcontroller Supports 20-bit SATA standard PHY interface Asynchronous Notification Supports either CoreFrame or AMBAAHB 2.0 bus interface

Deliverables
Verilog RTL source code Example synthesis scripts Verilog functional verification environment with tasked-based verification and PHY model Detailed specifications including user guide, product specification, verification guide, and programmers guide

Signal Descriptions:
System Interface Signals
Signal SYS_CLK SATA_CLK TESTMODE RST_N SPD_CONF ATA_INTR AHB_ERROR HRST_N Output Type Input Input Input Input Input Output Output Output Description System Clock SATA Clock (75Mhz or 150Mhz) Scan Test mode Power on Reset Interface Speed Configuration AHB Interface Error Flag (debug) Interrupt Signal Hard Reset Interrupt

AHB Master Interface Signals

HRDATA_M[31:0] HREADY HGRANT_M HRESP_M[1:0] HBUSREQ_M HADDR_M[31:0] HWDATA_M[31:0] HWRITE_M HSIZE_M[2:0] HBURST_M[2:0] HTRANS_M[1:0] HLOCK_M Input Input Input Input Output Output Output Output Output Output Output Output AHB Master Read Data Bus AHB Master Ready AHB Master Bus Grant AHB Master Transfer Response AHB Master Bus Request AHB Master Address Bus AHB Master Write Data Bus AHB Master Write Signal AHB Master Burst Size AHB Master Burst Type AHB Master Transfer Type AHB Master Bus Request Lock

AHB Slave Interface Signals

HADDR_S[31:0] HWDATA_S[31:0] HTRANS_S[1:0] HSEL_S HWRITE_S HSIZE_S[2:0] HRDATA_S[31:0] HREADY_OUT HRESP_S[1:0] Input Input Input Input Input Input Output Output Output AHB Slave Address Bus AHB Slave Write Data Bus AHB Slave Transfer Type AHB Slave Select Line AHB Slave Write Signal AHB Slave Burst Size AHB Slave Read Data Bus AHB Slave Output Ready Line AHB Slave Transfer Response

PHY Interface Signals

RXCLOCK PL_DATA [19:0] PHYRDY COMWAKE COMINIT SPDMODE LP_DATA [19:0] PHYRESET_N SPDSEL FARAFELB PARTIAL SLUMBER Input Input Input Input Input Input Output Output Output Output Output Output Receive Data Clock Receive Data PHYRDY Signal Detected COMWAKE Detected COMINIT Detected Speed Setting Transmit Data PHY Reset Signal Speed Setting Output Serial Loopback Enable Partial Power Mode Enable Slumber Power Mode Enable

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sales@sibridgetech.com
*M/S = Master/Secondary

Te c h n o l o g i e s

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