The Keys to Cost-Effective Custom IC Design By Shimon Raviv - VP, Engineering EquipIC supply chain

The costs involved with custom ASICs are more attractive than ever, but insightful project management holds the key to delivering the result on time and on budget.

Increasing competition and capacity in the fab services market, combined with the availability of mature sub-micron processes, is bringing down financial barriers to custom ASIC design. Time to completion, however, can influence everything from the market impact of the product to demand for investment capital. Keeping the project moving forward is vital, but ensuring each element completes on time can be difficult for smaller or less experienced companies. Depending upon the process and design complexity, a custom chip design can today be considered from a budget of around $500,000, compared to closer to $1 million just five years ago for the same technology node. As a benefit of the rapid advances in leading-edge process technologies, now reaching below 40nm, geometries in the 0.35m to 180nm range are now mature and reliable and accessible at much lower cost. The prices suppliers will quote are strongly influenced by risks associated with the services required. In the full ASIC model, the supplier takes responsibility for managing the design house and ensuring adequate yield before the decision is taken to ramp into high-volume production. If the customer already has tooling and databases the COT-based (Customer Owned Tooling) turnkey model the customer has control of all IC production costs, including chip size, yields, test time and assembly. The COT route should provide a very attractive unit price, although initial NRE costs tend to be higher. Initial Decisions Selecting a fab partner and process node are key decisions before the chip design can begin, and are dependent on several variables. Contrary to some perceptions in the marketplace, more or less all fabs are able to offer reliable

processes at more mature nodes such as 0.35m. Below 100nm, however, the availability of suitable IP may direct certain designs towards one specific fab. The process must have adequate digital libraries supporting the functions called by the system design, as well as mixed-signal functions such as ADCs as required, and an adequate analogue Process Design Kit (PDK). In addition, the requirements for integrated memory should also be taken into consideration at this stage, to determine the optimum process node. The anticipated production volume, after ramp-up, also has an important influence on node selection. At 0.35m, for example, an ASIC design can be viable from a production volume in the region of 100 wafers per annum. Progressively higher volumes are required at finer geometries. By the time the design is completed, including place & route, the budget commitment can be from $150,000 upwards. From this point, the cost to complete tapeout and complete the mask set is highly process dependent, and can cost from less than $100,000 in 0.35m or 0.18m to over $1 million at a more advanced nodes such as 40nm. Collecting the available IP is not necessarily easy. Several sources may be required, in addition to the fabs own, to secure access to all the functions necessary to create the design. This can require relationships with independent IP vendors. In some cases the team may be forced to engage a chip design house, which may add unexpected extra costs to the project. To avoid these costs, independent IP-search expertise can make a valuable contribution helping to achieve timely and cost-effective design completion. When targeting the most advanced nodes, custom IP may well be needed to be developed; this is only viable at high production volumes sufficient to amortise the high engineering (NRE) costs this incurs. Design for Packaging The design of the package, as well as silicon, has a considerable effect on the final cost of the custom IC. In the search for the lowest cost per pin, techniques such as managing the number of individual power and ground connections required, and optimising the number of substrate layers necessary to connect the die to external solder ball can realise valuable savings. In this context, co-

developing the chip and the package can help achieve the lowest cost solution. This is understood among experienced chip developers. However, start ups or system houses may not fully appreciate the potential impact on the overall delivered cost of the ASIC. Invest in Test A company new to commissioning a custom ASIC can be tempted to try and cut down the cost of test engineering, which is typically around $100K-$200K. However, it is essential to commit the proper resources for the resulting chip to meet the quality and performance targets. One way to reduce the cost may be to work with offshore test engineers, such as a fabs in-house team. However, appreciable hidden costs can be incurred; for example, one or more engineers may need to be assigned to work on site at the fab throughout test development. For this reason, working with a regional test partner is usually faster and more cost effective, particularly in the early stages of the project. EquipIC usually recommends developing test programs in partnership with a professional test house close to the design team. When initial production lots are available, it is then cost effective to validate and optimise the test programs by testing these lots in the test house. Later in the project, after test time and yields stabilise, it can be economical to port the test programs to the foundry and package house for mass production. First Silicon After the test strategy is finalised the project typically moves into the building of first prototypes, resulting in the first actual hardware being delivered to systems teams for evaluation. Prototyping usually calls for several thousands of units to be built. With the build costs for these included, the total budget for the project may lie between $500,000 and $1 million for ICs fabricated using a mature process, rising as high as $2-3 million if a more advanced process is used (it should be noted that it is the mask tooling and high performance IPs that are the primary cost drivers here). If the design includes complex IP such as a 32-bit processor core, the cost could be higher still.

When the first prototypes are ready the systems team can begin evaluating the chip, culminating in a decision to go ahead or to make changes to the design. Assuming the go-ahead is given, thorough qualification and characterisation are necessary before the decision to ramp up into full production is taken. Preparing for Production Characterisation is carried out with reference to the chip specification, which must be known to the body performing the characterisation. Hence a customer can only characterise their devices independently if the design is their own responsibility; for instance in a full ASIC model, the designing company is responsible for characterising the chip. The project must demonstrate satisfactory figures for chip performance and yield before the decision can be taken to move forward to ramp up to full production. This is usually a difficult part of the project, and can benefit from the involvement of an independent supply-chain consultant to work with the fab and use acquired knowledge of the systems and cultures to ensure that any changes are made correctly as requested and on time. For customers who cannot commit large resources to project management tasks, the extra bandwidth provided at this stage by a consultant can be invaluable. Project Successful As a rule, the key to managing an ASIC project successfully is to set realistic goals and then to do everything possible to ensure those goals are met. The skill lies in setting the right targets at each stage. These must be achievable, as far as the supply-chain partners are concerned, while also enabling the customer to secure acceptable chip performance, development cost, unit price and time to market.

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