Low Power and High Speed Digital Filter Design Using VLSI Technique for Solar Power Inverter

A DISSERTATION SUBMITTED TO GUJARAT TECHNOLOGICAL UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE AWARD OF THE DEGREE OF MASTER OF ENGINEERING IN INSTRUMENTATION & CONTROL (APPLIED INSTRUMENTATION) BY PRADEEP.N.PATEL UNDER THE GUIDANCE OF Prof. Deepali .H. Shah

SUBMITTED TO DEPARTMENT OF INSTRUMENTATION & CONTROL ENGINEERING L. D. COLLEGE OF ENGINEERING, AHMEDABAD - 380 015. GUJARAT UNIVERSITY, INDIA APRIL-2011

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L. D. COLLEGE OF ENGINEERING

Certificate
This is to certify that the work presented in the dissertation entitled

Low Power and High Speed Digital Filter

Design Using VLSI Technique for Solar Power Inverter

has been carried out by

PATEL PRADEEP NAVINBHAI

En. No. 090280703007 Seat No. 07 Year 2011 In a manner sufficiently satisfactory to warrant its acceptance As a partial fulfillment of the requirement for award of the Degree of

Master of Engineering in Applied Instrumentation Engineering

This is a bonafide work done by the student and has not been Submitted to any other University / Institute for the award of Any other Degree / Diploma

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Guide: _______________ Prof. Deepali. H. Shah IC Dept, L.D. Engg. College, Ahmedabad ________________ Prof. N. N. Bhuptani N. Patel Head of IC Dept, L. D. College of Engineering. Engineering. ________________ Prof. M. Principal, L. D. College of

DISSERTATION APPROVAL SHEET

The Dissertation entitled

Low Power and High Speed Digital Filter Design Using VLSI Technique for Solar Power Inverter
is Submitted by

Patel Pradeep Navinbhai

Of L. D. College of Engineering, Ahmedabad is Approved for the Award of the Degree of Master of Engineering in Applied Instrumentation by Gujarat Technological University.

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INTERNAL EXAMINER(S):

EXTERNAL EXAMINER(S):

Date: Place:

Acknowledgement
Apart from my efforts, the success of this project depends largely on the encouragement and guidance of several other important individuals. I hereby get the opportunity to humbly express my gratitude towards all people whose contribution was very much important for establishment of my project. First of all I am thankful to almighty GOD for their blessings and everything. I like to convey my heart felt gratitude to my project guide Prof. Deepali .H. Shah whose co-operation and precious guidance have been very conductive to the preparation of the project. He had been always with me throughout my dissertation. His constant support has been a key factor in overcoming challenges I faced during the course of this period. I thank to Prof. N. N. Bhuptani (HOD) for support and who has given me the opportunity to do dissertation work at L.D. Engineering College, Ahmedabad. I also like to express my gratitude to all members of the Instrumentation and Control Department of L. D. College of Engineering, Ahmedabad, for their willingness to help me at any time. I feel proud in expressing my sincere gratitude to Babubhai Solanki for providing excellent laboratory facility during this project. I hereby show my gratefulness to all my M.E. class fellows and for their continuous moral support, co-operation and help throughout the tenure of my course.

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I feel proud in expressing my sincere gratitude to my parents, my brother and my sister who not only has inspired, sacrificed and helped me at every phase of my study but also stood with me during the period of stress. I strongly believe that I could not complete this work without them Cooperation and motivation. At last but not least I extend my sincere thanks to everyone who have directly or indirectly helped and encouraged me in completion of my dissertation work. Thank You All Pradeep Patel

Chapter 1 Introduction
With the increasing concern about global environmental protection and energy demand due to rapid growth of population in developing countries and the diminishing of resources of grid supply, the need to produce freely available pollution free natural energy such as solar energy has been drawing increasing interest in every corner of the world. In an effort to utilize the solar energy effectively through power converter, a great deal of research is being carried out by different researchers/scientist and engineers at different places in the world to meet the increasing demand for load.

1.1

Objective of thesis

The study presents a methodology to integrate a PV power source with energy storage battery backup device and generate power by an innovative Solar Power Inverter with an objective to supplement the utility power in a grid connected houses during its cut off or restricted supply period. The system can also be used as a standalone power

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supply in a grid deprived house especially in remote rural sectors by adding more PV pane and/or battery to the system. The research objectives are: 1. The use of software based Direct PWM modulation Strategy and its Soft Control feature extend the flexibility to control converter parameters like voltage , frequency number of PWM pulses etc..
2. The system simulation of PWM Pulse generation has been done on a XLINIX

based Sparton 3E board using Verilog code. The test on simulation of PWM generation program after synthesis and compilation were recorded and verified on a prototype sample
3. Optimal design of solar power converter module consisting of PV array, Battery,

PWM Inverter etc. 4. Prototype development of utility interface solar adaptive Power converter unit.

1.2

Report Overview

Chapter 2 Literature Overview

This Chapter include number of Papers introduction which I use for my Dissertation thesis.

Chapter 3 Introduction of the FPGA

Field programmable Gate Arrays (FPGAs) are digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks. Design engineers can configure such devices to perform a tremendous variety of tasks.

Chapter 4 Introduction to Spartan 3E Kit

The Spartan 3E Starter Board provides a powerful and highly advanced self-contained development platform for designs targeting the Spartan 3E FPGA from Xilinx. It features a 500K gate Spartan 3E FPGA with a 32 bit RISC processor and DDR interfaces.

Chapter 5 Introduction of Xilinx ISE web Pack 11.1

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The most popular trend currently is to design in HDL at an RTL level, because logic synthesis tools can create gate level net lists from RTL level design .behavioral synthesis allowed engineers to design directly in terms of algorithms and the behavior of the circuit, and then use EDA tools to do the translation and optimization in each phase of the design. However, behavioral synthesis did not gain widespread acceptance. Today, RTL design continues to be very popular. Verilog HDL is also being constantly enhanced to meet of new verification methodology.

Chapter 6 Introduction of Solar Power Inverter

Chapter 2 Literature Overview

1. FPGA-Based PWM Intelligent Adaptive Solar Inverter as a Utility Interface for Use in Agro-Based Application by S. N. SINGH and A.K. SINGH Department of Electrical Engineering, NIT, Jamshedpur, INDIA Department of Electronics Engineering, NIT, Jamshedpur, INDIA With the increasing concern about global environmental protection and energy demand due to rapid growth of population in developing countries and the diminishing of resources of grid supply, the need to produce freely available pollution free natural energy such as solar energy has been drawing increasing interest in every corner of the world. In an effort to utilize the solar energy effectively through power converter, a great deal of research is being carried out by different researchers/scientist and engineers at different places in the world to meet the

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increasing demand for load. The study presents a methodology to integrate a PV power source with energy storage battery backup device and generate power by an innovative Solar Power Converter with an objective to supplement the utility power in a grid connected houses during its cut off or restricted supply period. The system can also be used as a standalone power supply in a grid deprived house specially in remote rural sectors by adding more PV pane and/or battery to the system. The use of software based Direct PWM modulation strategy and its soft control feature extend the flexibility to control converter parameters like voltage, frequency number of PWM pulses etc without changing any hardware circuit. The system simulation of PWM Pulse generation has been done on a XLINIX based Sparton 3E board using VHDL code. The test on simulation of PWM generation program after synthesis and compilation were recorded and verified on a prototype sample

2. FPGA Based Sinusoidal Pulse Width Modulated Waveform Generation for

Solar (PV) Rural Home Power Inverter by S.N.Singh and A.K.Singh , Journal of Telecommunications , Volume 1 , Issue 1 , February 2010 The basic need of an electrical energy is increasing with the rapid growth of population in urban, sub-urban and rural sectors. On the other end, the conventional grid supply in a grid connected area has become standstill due to diminishing trend of raw material resources and its further extension is not possible due to various technical, political and economic reasons. To meet the excess energy demand, alternative renewable energy sources like solar/wind etc with energy storage device i.e. Battery are being used to work as a standalone power source or in sharing mode with Grid or DG power source. Among these two sources solar energy is preferred as it is easily available in every part of the country in the world where as wind energy is restricted to the coastal area only. A purely solar power converter, if used alone, may become very expensive as far as initial investment is concerned. Further, due to varying solar insolation, the battery barely gets time to fully charge from a single PV source due to varying sun radiation or from the limited available grid source especially in rural sector to its full extent. Hence the solar power system needs to be

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integrated with supplementary additional DG back up sources in order to deliver 24 hour power. The system can also work as a standalone power source in a grid deprived area in remote rural sectors by adding more number of PV modules and battery bank. The optimal utilization of these sources is possible with efficient smart adaptive Power converter and adopting optimal load management. In the present study, the Pulse width modulated (PWM) adaptive intelligent Power converter (inverter) has been designed and developed where the input DC power stored in the battery bank, obtained through PV and /or Grid sources, has been digitized to produce a sequence of PWM pulses (approximated to a sine wave) at the output of power converter and deliver power to the load. The traditional analog SineTriangular method for generating PWM pulses adopt the technology where a high frequency carrier signal is compared with sinusoidal wave as reference signal, set at desired output frequency. In the present scheme, the PWM pulses are directly generated using a new technique through software program coded with VHDL and downloaded in FPGA Spartan 3E starter kit to produce base drive signals for inverter power device switches. The FPGA VLSI technology offers a fast system with many more advantages as compared to other conventional technology including DSP based controller etc. The software program can easily be changed to optimize and control the inverter parameters like frequency, voltage amplitude, number of PWM pulses in half cycle etc. without changing the hardware circuit. The PWM output waveform designed with high number of PWM pulses in a half cycle can produce a low value of THD content (less than 3-5% THD) and approximate very near to a sine wave which is comparable with the quality of the sine wave of the grid supply.
3. DESIGN AND DEVELOPMENT OF UTILITY INTERFACE ADAPTIVE

SOLAR POWER CONVERTER FOR WATER PUMPING SYSTEM IN INDIAN VILLAGES by S. N. Singh, Snehlata Mishra & Vandana Neha Tigga in IJRRAS2(3) , March 2010

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The paper presents development of a utility interface solar power converter to supplement deficit in Grid power supply for a water pumping system used in rural home of Indian villages. The power supply system comprises of solar (PV) array, PWM converter incorporating PWM control strategy, energy storage battery devices, submersible pump and water storage tank(s) etc. The model of the system has been designed for its optimal operation and a prototype solar power converter unit has been developed to drive a hp pump motor. The Life cycle cost evaluation of the solar power converter has been done and compared with conventional DG set. This has resulted in a cost effective system with a 60% - 70% grid power saving. Water is the basic need of all living being. Approximately 30% of world population lack access to water for drinking, livestock and irrigation. Traditional technology used to access the water from available sources like bore well or open well employ water pump to lift water and store it in an overhead tank(s). These pumps are either powered by conventional grid supply or alternative Diesel Generating (DG) set etc. but higher cost of fuel consumed by DG set and non availability of adequate grid supply have forced scientist and engineer to think for either a supplementary or alternative renewable energy source to produce electrical power. Solar photovoltaic energy is one of the potential source is preferred due to availability of free sun fuel ,straight forward technology, lower maintenance with reliable operation etc. Though the solar modules (cells) are expensive but efforts are being made to use it not only for power conversion but also for building the exterior wall or covering the roof of pump farm houses or water pump Houses. Further, the demand of electricity is increasing day by day by the growing population where as grid supply extension has almost become standstill due to its limited resources like fossil fuel etc. and its further expansion is not possible due to various technical and economic reasons. This has motivated the researchers to develop utility interface solar power converter to generate power which can meet the increasing energy demand of houses located specially in rural sector of the country connected to weak grid supply sources. The system can work even as a standalone device in the grid less village areas. Data acquisition of demand based load profile were accessed .The computational analysis for optimal design of the component has been done and prototype Inverter model has been developed and tested for its dynamic Performance. The proposed system is able to bring an energy

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saving up to a maximum value of 60-80% of power drawn from utility supply in these rural houses. The modeling and design of components of water pumping system include the following modules PV cell Battery back-up source PWM Inverter Intelligent power controller Pump for water storage in an overhead tank etc.

The present study highlights the following: Study of user demand of pump and lightening load profile in a rural house of Indian villages. Optimal design of solar power converter module consisting of PV array, Battery, PWM Inverter and Pump-Motor etc. Prototype development of utility interface solar adaptive Power converter unit. Life Cycle Cost Analysis of the prototype solar converter system and its cost comparison with DG set. Social Impact of use of solar powered converter on rural development in Indian Villages.
4. Simulation of grid-assisted solar power converter: an effective solution for

power crisis in rural India S.N.Singh* and A.K.Singh , Asian Journal and Environment This paper presents integration of the grid distribution network in Indian scenario with solar power converter to meet the additional electrical energy demand of households in urban as well as rural sectors which are both rapidly expanding. A simulation approach using PSIM software has been adopted to explore the feasibility of

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developing such system to work as a supplementary source. The SPWM conversion technique used in the development of the proposed solar power converter produces a grid quality usable AC power supply from PV and/or battery source. The optimal design of system components such as PV, battery and inverter etc. has resulted in a cost effective system and offers a stabilized consistent power supply for household loads. The PV converter system can also work as a standalone system in remote areas of Indian villages where the grid is either not existing or its availability is very poor and grid extension or expansion is not possible due to various technical and economic reasons. Electrical energy is the basic need of human beings. The demand for electrical energy is increasing day by day with rapid growth of population. On the other hand, power generation through conventional sources of energy is being limited due to diminishing trend of its raw material such as coal etc. and is expected to be exhausted in near future. This has forced engineers and scientists to look for alternative nonconventional energy sources like solar, wind, biomass, etc. which can supplement the existing grid power source and thus reduce over burdening of the grid supply An investigation has been carried out to search for an effective solution towards the present power crises which has arisen especially in rural sector of India and solar energy was found to be the most appropriate solution for the same. Simulation approach has been adopted to develop a cost effective solar power converter which can produce pollution free green electricity and can have a better socio- economic impact on the society. The system comprises the following components: PV array Battery bank Bi-directional inverter Intelligent solar charger

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5. Design Methodology of VLSI Power Electronics digital controller based on Matlab-Modelsim Co-Simulation by Juliano KATRIB1, Philippe POURE1, Shahram KARIMI and Shahrokh Saadate This paper presents a methodology to design Very Large Scale Integration (VLSI) fully digital controller for Power Electronics. Step by step, the proposed Top-down methodology based on Very high speed integrated circuits Hardware Description Language (VHDL) and on Matlab-Modelsim cosimulation is presented. It is used to study and validate the digital adaptation and the architecture implementation of the control algorithm. Modelling, Matlab-Modelsim co-simulation and virtual prototyping are achieved in a unique design environment managed by Matlab computer aided design tools. An application using the proposed methodology was studied: a digital controller for three-phase Shunt Active Power Filter (SAPF). The power circuit has been modelled in the Matlab/Simulink environment, using the dedicated Power System Blockset (PSB) toolbox. The digital controller is modelled in VHDL code in the Modelsim environment. Then, this VHDL model is imported into Matlab environment and co-simulated using the Link-For-Modelsim toolbox. A high level VHDL model for the controller using real data format has been first designed and validated by cosimulation. Then, an optimized VLSI architecture for the controller using a specific data binary format has been modelled in VHDL code at Register Transfert Level and successfully validated by Matlab-Modelsim co-simulation.

6. FPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision Gating by A. Senthilkumar, A.M. Natarajan ,Department of ECE,Department of CSE, Kongu Engineering College, Perundurai, Erode,Tamil Nadu, India-638052 With the emergence of portable computing and communication system, power awareness is one of the major objectives of VLSI Design. This is its ability to scale power consumption based on the time-varying nature of inputs. Even though the system is not designed for being power aware, systems display variations in power

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consumption as conditions change. This implies, by the definition above, that all systems are naturally power aware to some extent. However, one would expect that Some systems are more power aware than others. Equivalently, the system should be able to re designed to increase their power awareness. This research proposes a pipelined Variable precision gating scheme to improve the power awareness of the system. This research illustrates this technique by applying it to FPGA Implementation of multipliers and digital FIR filters. This proposed technique is to clock gating to registers in both data flow direction and vertical to data flow direction within the individual pipeline stage based on the input data precision. For signed multipliers using 2s complement representation, sign extension, which wastes power and causes longer delay, could be avoided by implementing this technique. Very little additional area is needed for this technique. The designed circuit is simulated, synthesized and implemented in Xilinx Spartan 3e FPGA. The Power is analyzed for the designed circuit and the power saving of 18 % obtained for the proposed FIR Filter with 3 % increase in area compared to the existing pipeline gating design 7. Solar Cell Single Measurement Maximum Power Point Tracking by Raul Rabinovici Dept. of Electrical and Computer Engineering Ben Gurion University of the Negev Beer Sheva, Israel It is possible to give a valuable estimation for an entire solar array IV curve, based only on a single working point (current and voltage) measurement, on panels of solar cells, when several of their parameters are known and environmental parameters also known. The estimations were performed using Matlab/Simulink and the simulation is based on the 10 parameter solar cell model. The estimated curves only slightly deviate from the actual measured curves of real solar panels. The average short circuit current error is less than 5%, when the worst case simulated of just 33% of full lighting is also included in that average. When the open circuit voltage drops in error, the short circuit current grows in error and vice verse, so the MPP error is smaller. It is shown that this approach could be used to evaluate, on line, the Maximum Power Point (MPP) of solar panels, while even two or more local maxima could exist. The average relative MPP errors seem to be less than 2% with a full illumination (1 sun), less than 2.5% for 2/3 illumination and less than 3% for less than 1/3 illumination. After the MPP of

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solar cells, which are not in their optimal working point, has been evaluated, then by this new MPP, they can be classified for re-meandering. Such a procedure would require evaluation of the entire I/V and I/P curves of the cell/panels. It would effectively eliminate the problem of local maxima on the I/P curve. Once the MPP has been evaluated for each panel, it is possible to evaluate the MPP of an entire solar field after re-meandering. Once this is knows, the inverter could be controlled to project the MPP voltage towards the solar field, thus eliminating the need to use a MPPT module (dc/dc converter).

Chapter 3
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Introduction of the FPGA

3.1 Introduction of FPGAs
Field programmable Gate Arrays (FPGAs) are digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks. Design engineers can configure such devices to perform a tremendous variety of tasks. Gate Array a type of logic chip that can be programmed at the field level there devices can be re-configured to change logic function while resident in the system. Fully fabricated FPGA chips containing tend to hundreds of thousands or even more, of logic gates with programmable interconnects. Programmable interconnects are available to users for their custom hardware programming to realize desired functionality. This design style provides a mean for fast prototyping and also for cost effective chip design, especially for low applications. FPGAs are programmable digital logic chips. What that means is that you can program them to do almost any digital function.

Here's The General Workflow When Burning the FPGAs:

1) You use a computer to describe a "logic function" that you want. You might draw a schematic, or create a text file describing the function, doesnt matter. 2) You compile the "logic function" on your computer, using software (ISE WEBPACK 11.1) provided by the FPGA vendor. That creates a binary file that can be downloaded into the FPGA. 3) You connect a cable from your computer to the FPGA, and download the binary file (.bit file)to the FPGA .That's it! Your FPGA behaves according to your "logic function".

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Always Remember These Points:

1) You can download FPGAs as many time as you want - no limit with different functionalities every time if you want. If you make a mistake in your design, just fix your "logic function", re-compile and re download it. No PCB, solder or component to change. 2) The designs can run much faster than if you were to design a board with discrete components, since everything runs within the FPGA, on its silicon die. 3) FPGAs loose their functionality when the power goes away (like RAM in a computer that looses its content). You have to re-download them when power goes back up to restore the functionality

3.2 Spartan-3E FPGA Family Introduction:

The Spartan-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The five-member family offers densities ranging from100, 000 to 1.6 million system gates, as shown in Table 1. Table 3.1 summary of Spartan- 3E FPGA

The Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. These Spartan-3E enhancements, combined with advanced 90 nm process technology,

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deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. Because of their exceptionally low cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment. The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.

3.3 Features of XC3S500E FPGA:

Very low cost, high-performance logic solution for high-volume, consumeroriented applications. Multi-voltage, multi-standard Select IO interface pin Up to 376 I/O pins or 156 differential signal pairs LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling 622+ Mb/s data transfer rate per I/O True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O Enhanced Double Data Rate (DDR) support. DDR SDRAM support up to 333 Mb/s.

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Abundant, Flexible Logic Resources

Densities up to 33,192 logic cells, including optional shift register or distributed RAM Support. Efficient wide multiplexers, wide logic. IEEE 1149.1/1532 JTAG programming/debug port.

Hierarchical Select ram Memory Architecture

Up to 648 Kbits of fast block RAM. Up to 231 Kbits of efficient distributed RAM. Up to eight Digital Clock Managers (DCMs). Frequency synthesis, multiplication, division. High-resolution phase shifting. Wide frequency range (5 MHz to over 300 MHz). Eight global clocks plus eight additional clocks per each half of device, Plus abundant low- skew routing. Configuration interface to industry-standard PROMs. Low-cost, space-saving SPI serial Flash PROM. Parallel NOR Flash PROM. Low-cost Xilinx Platform Flash with JTAG. Fully supported by Xilinx ISE development system. Synthesis, mapping, placement and routing. Pb-free packaging options.

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3.4 Architectural Overview:

The Spartan-3E family architecture consists of five fundamental programmable functional elements:

3.4.1 Configurable Logic Blocks (CLBs):Contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data.

3.4.2 Input /Output Blocks (IOBs) :Control the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus3-state operation. Supports a variety of signal standards, including four high-performance differential standards. Double Data-Rate (DDR) registers are included.

3.4.3 Block RAM:Provides data storage in the form of18-Kbit dual-port blocks.

3.4.5 Multiplier:Blocks accept two 18-bit binary numbers as inputs and calculate the product.

3.4.6 Digital Clock Manager (DCM):Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. These elements are organized as shown in Figure 3.1. A ring of IOBs surrounds a regular array of CLBs. Each device has two columns of block RAM except for the XC3S100E, which has one column. Each RAM column consists of several18-Kbit RAM blocks. Each block RAM is associated with dedicated multiplier.

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Fig.3.1 Configuration Logic Block The DCMs are positioned in the centre with two at the top and two at the bottom of the device. The XC3S100E has only one DCM at the top and bottom, while the XC3S1200E and XC3S1600E add two DCMs in the middle of the left and right sides. The Spartan-3E family features a rich network of traces that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing. Each functional element has an associated switch matrix that permits multiple connections to the routing. A typical FPGA chip consists of I/O buffers, an array of configurable logic blocks (CLBs) and programmable interconnect structures. The programming of the interconnects is accomplished by programming of RAM cells whose output terminals are connected to the gates of MOS pass transistors. Thus the signal routing between the CLBs and the I/O blocks is accomplished by setting the configurable switch matrices by setting the configurable switch matrices accordingly.

Configuration:
Spartan-3E FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control

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all functional elements and routing resources. The FPGAs configuration data is stored externally in a PROM or some other non-volatile medium, either on or off the board. After applying power, the configuration data is written to the FPGA using any of seven different modes:

Configuration Modes:1) 2) 3) Master Serial from a Xilinx Platform Flash PROM. Serial Peripheral Interface (SPI) from an industry-standard SPI serial Flash. Byte Peripheral Interface (BPI) Up or Down from an industry-standard x8 or X8 / X16 parallel NOR Flash. 4) 5) 6) 7) Slave Serial, typically downloaded from a processor. Slave Parallel, typically downloaded from a processor. Boundary Scan (JTAG), typically downloaded from a processor or system . FPGA contains a big number at basic logic-functions (logic-cells). The General architecture of the FPGA chip.

I/O CapabilitiesThe Spartan-3E FPGA Select IO interface supports many popular single-ended and differential standards. Table 2shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination.Spartan-3E FPGAs support the following single-ended standards:

3.3V low-voltage TTL (LVTTL) Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,1.5V, or 1.2V 3V PCI at 33 MHz, and in some devices, 66 MHz HSTL I and III at 1.8V, commonly used in memory applications SSTL I at 1.8V and 2.5V, commonly used for memory applications

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Spartan-3E FPGAs support the following differential standards: LVDS Bus LVDS Mini-LVDS RSDS Differential HSTL (1.8V, Types I and III) Differential SSTL (2.5V and 1.8V, Type I) 2.5V LVPECL inputs

Table 3.2: Available User I/Os and Differential (Diff) I/O Pairs

IOB OverviewThe Input /Output Block (IOB) provide a programmable, unidirectional or bidirectional interface between a package pin and the FPGAs internal logic. The IOB is similar to that of the Spartan-3 family with the following differences: Input-only blocks are added

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Programmable input delays are added to all blocks DDR flip-flops can be shared between adjacent IOBs

The unidirectional input-only block has a subset of the full IOB capabilities. Thus there are no connections or logic for an output path. The following paragraphs assume that any reference to output functionality does not apply to the input-only blocks. The number of input-only blocks varies with device size, but is never more than 25% of the total IOB count. Figure 5, is a simplified diagram of the IOBs internal structure. There are three main signal paths within the IOB: the output path, input path, and 3-state path. Each path has its own pair of storage elements that can act as either registers or latches. For more information, see Storage Element Functions. The three main signal paths areas follow:

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Figure 3.2: Simplified IOB Diagram The input path carries data from the pad, which is bonded to a package pin, through an optional programmable delay element directly to the I line. After the delay element, there are alternate routes through a pair of storage elements to the IQ1 and IQ2 lines. The IOB outputs I, IQ1, and IQ2 lead to the FPGAs internal logic. The delay element can be set to ensure a hold time of zero (see Input Delay Functions).

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The output path, starting with the O1 and O2 lines, carries data from the FPGAs internal logic through a multiplexer and then a three-state driver to the IOB pad. In addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. The 3-state path determines when the output driver is high impedance. The T1 and T2 lines carry data from the FPGAs internal logic through a multiplexer to the output driver. In addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. All signal paths entering the IOB, including those associated with the storage elements, have an inverter option. Any inverter placed on these paths is automatically absorbed into the IOB.

Double-Data-Rate TransmissionDouble-Data-Rate (DDR) transmission describes the technique of synchronizing signals to both the rising and falling edges of the clock signal. Spartan-3E devices use register pairs in all three IOB paths to perform DDR operations. The pair of storage elements on the IOBs Output path (OFF1 and OFF2), used as registers, combine with a special multiplexer to form a DDR D-type flip-flop (ODDR2). This primitive permits DDR transmission where output data bits are synchronized to both the rising and falling edges of a clock. DDR operation requires two clock signals (usually 50% duty cycle), one the inverted form of the other. These signals trigger the two registers in alternating fashion, as shown in Figure 3.3. The Digital Clock Manager (DCM) generates the two clock signals by mirroring an incoming signal, and then shifting it 180 degrees. This approach ensures minimal skew between the two signals. Alternatively, the inverter inside the IOB can be used to invert the clock signal, thus only using one clock line and both rising and falling edges of that clock line as the two clocks for the DDR flip-flops. The storage-element pair on the Three-State path (TFF1 and TFF2) also can be combined with a local multiplexer to form a DDR primitive. This permit

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synchronizing the output enable to both the rising and falling edges of a clock. This DDR operation is realized in the same way as for the output path. The storage-element pair on the input path (IFF1 and IFF2) allows an I/O to receive a DDR signal. An incoming DDR clock signal triggers one register, and the inverted clock signal triggers the other register. The registers take turns capturing bits of the incoming DDR data signal. The primitive to allow this functionality is called IDDR2. Aside from high bandwidth data transfers, DDR outputs also can be used to reproduce, or mirror, a clock signal on the output. This approach is used to transmit clock and data signals together (source synchronously). A similar approach is used to reproduce a clock signal at multiple outputs. The advantage for both approaches is that skew across the outputs is minimal.

Figure 3.3: Two Methods for Clocking the DDR Register

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Register Cascade FeatureIn the Spartan-3E family, one of the IOBs in a differential pair can cascade its input storage elements with those in the other IOB as part of a differential pair. This is intended to make DDR operation at high speed much simpler to implement. The new DDR connections that are available are shown in Figure 3.2 (dashed lines), and are only available for routing between IOBs and are not accessible to the FPGA fabric. Note that this feature is only available when using the differential I/O standards LVDS, RSDS, and INI_LVDS.

IDDR2As a DDR input pair, the master IOB registers incoming data on the rising edge of ICLK1 (= D1) and the rising edge of ICLK2 (= D2), which is typically the same as the falling edge of ICLK1. This data is then transferred into the FPGA fabric. At some point, both signals must be brought into the same clock domain, typically ICLK1. This can be difficult at high frequencies because the available time is only one half of a clock cycle assuming a 50% duty cycle. See Figure 3.4 for a graphical illustration of this function. In the Spartan-3E device, the signal D2 can be cascaded into the storage element of the adjacent slave IOB. There it is re-registered to ICLK1, and only then fed to the FPGA fabric where it is now already in the same time domain as D1. Here, the FPGA fabric uses only the clock ICLK1 to process the received data. See Figure 3.5 for a graphical illustration of this function.

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Figure 3.4: Input DDR (without Cascade Feature)

Figure3.5: Input DDR Using Spartan-3E Cascade Feature

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ODDR2As a DDR output pair, the master IOB registers data coming from the FPGA fabric on the rising edge of OCLK1 (= D1) and the rising edge of OCLK2 (= D2), which is typically the same as the falling edge of OCLK1. These two bits of data are multiplexed by the DDR mix and forwarded to the output pin. The D2 data signal must be re-synchronized from the OCLK1 clock domain to the OCLK2 domain using FPGA slice flip-flops. Placement is critical at high frequencies, because the time available is only one half a clock cycle. See Figure 3.6 for a graphical illustration of this function.

Figure 3.6: Output DDR

Select IO Signal Standards:The Spartan-3E I/Os feature inputs and outputs that support a wide range of I/O signaling standards (Table 3 and Table 4). The majority of the I/Os also can be used to form differential pairs to support any of the differential signaling standards (Table 4). To define the I/O signaling standard in a design, set the IOSTANDARD attribute to the appropriate setting. Xilinx provides a variety of different methods for applying the IOSTANDARD for maximum flexibility. For a full description of different methods of applying attributes to control IOSTANDARD, refer to Entry Strategies for Xilinx Constraints in the Xilinx Software Manuals and Help. Spartan-3E FPGAs provide additional input flexibility by allowing I/O standards to be mixed in different banks. For a particular VCCO voltage, Table 3 and Table 4
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list all of the IOSTANDARDs that can be combined and if the IOSTANDARD is supported as an input only or can be used for both inputs and outputs. Table 3.3: Single-Ended IOSTANDARD Bank Compatibility

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Table 3.4: Differential IOSTANDARD Bank Compatibility

HSTL and SSTL inputs use the Reference Voltage (VREF) to bias the input- switching threshold. Once a configuration data file is loaded into the FPGA that calls for the I/Os of a given bank to use HSTL/SSTL, a few specifically reserved I/O pins on the same bank automatically convert to VREF inputs. For banks that do not contain HSTL or SSTL, VREF pins remain available for user I/Os or input pins The optional pull-up and pull-down resistors are intended to establish High and Low levels, respectively, at unused I/Os. The pull-up resistor optionally connects each IOB pad to VCCO. A pull-down resistor optionally connects each pad to GND. Each I/O has an optional keeper circuit that retains the last logic level on a line after all drivers have been turned off. This is useful to keep bus lines from floating when all connected drivers are in a high impedance state. Clamp diodes protect all device pads against damage from Electro-Static Discharge (ESD) as well as excessive voltage transients. Each I/O has two clamp diodes: One diode extends Pto-N from the pad to VCCO and a second diode extends N-to-P from the pad to GND. During operation, these diodes are normally biased in the off state. All Spartan-3 IOBs support boundary-scan testing compatible with IEEE1149.1 standards.

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Digitally Controlled Impedance (DCI):

When the round-trip delay of an output signali.e., from output to input and back again exceeds rise and fall times, it is common practice to add termination resistors to the line carrying the signal. These resistors effectively match the impedance of a devices I/O to the characteristic impedance of the transmission line, thereby preventing reflections that adversely affect signal integrity.

CLB OverviewThe Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits. Each CLB contains four slices, and each slice contains two Look-Up Tables (LUTs) to implement logic and two dedicated storage elements that can be used as flip-flops or latches. The LUTs can be used as a 16x1 memory (RAM16) or as a 16-bit shift register (SRL16), and additional multiplexers and carry logic simplify wide logic and arithmetic functions. Most general-purpose logic in a design is automatically mapped to the slice resources in the CLBs. Each CLB is identical, and the Spartan-3E family CLB structure is identical to that for the Spartan-3 family.

Figure 1.7: CLB Locations

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CLB ArrayThe CLBs are arranged in a regular array of rows and columns ach density varies by the number of rows and columns of CLBs (see Table5). Table 3.5: Spartan-3E CLB Resources

SlicesEach CLB comprises four interconnected slices, as shown in Figure 1.8. These slices are grouped in pairs. Each pair is organized as a column with an independent carry chain. The left pair supports both logic and memory functions and its slices are called SLICEM. The right pair supports logic only and its slices are called SLICEL. Therefore half the LUTs support both logic and memory (including both RAM16 and SRL16 shift registers) while half support logic only, and the two types alternate throughout the array columns. he SLICEL reduces the size of the CLB and lowers the cost of the device, and can also provide a performance advantage over the SLICEM.

Figure 3.8: Arrangement of Slices within the CLB

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Slice Location DesignationsThe Xilinx development software designates the location of a slice according to its X and Y coordinates, starting in the bottom left corner. The letter X followed by a number identifies columns of slices, incrementing from the left side of the die to the right. The letter Y followed by a number identifies the position of each slice in a pair as well as indicating the CLB row, incrementing from the bottom of the die. Figure 3.9 shows the CLB located in the lower left-hand corner of the die. The SLICEM always has an even X number, and the SLICEL always has an odd X number.

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Figure 3.9: Simplified Diagram of the Left-Hand SLICEM

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Slice OverviewA slice includes two LUT function generators and two storage elements, along with additional logic, as shown in Figure 3.10. Both SLICEM and SLICEL have the following elements in common to provide logic, arithmetic, and ROM functions: Two 4-input LUT function generators, F and G Two storage elements Two wide-function multiplexers, F5MUX and FiMUX Carry and arithmetic logic

The SLICEM pair supports two additional functions: Two 16x1 distributed RAM blocks, RAM16 Two 16-bit shift registers, SRL16

Each of these elements is described in more detail in the following sections.

Figure 1.10: Resources in a Slice

Logic CellsThe combination of a LUT and a storage element is known as a Logic Cell. The additional features in a slice, such as the wide multiplexers, carry logic, and arithmetic gates, add to the

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capacity of a slice, implementing logic that would otherwise require additional LUTs. Benchmarks have shown that the overall slice is equivalent to 2.25 simple logic cells. This calculation provides the equivalent logic cell count shown in Table 5.

Slice DetailsIt is a detailed diagram of the SLICEM. It represents a superset of the elements and connections to be found in all slices. The dashed and gray lines (blue when viewed in color) indicate the resources found only in the SLICEM and not in the SLICEL .Each slice has two halves, which are differentiated as top and bottom to keep them distinct from the upper and lower slices in a CLB. The control inputs for the clock (CLK), Clock Enable (CE), Slice Write Enable (SLICEWE1), and Reset/Set (RS) are shared in common between the two halves. The LUTs located in the top and bottom portions of the slice are referred to as "G" and "F", respectively, or the "G-LUT" and the "F-LUT". The storage elements in the top and bottom portions of the slice are called FFY and FFX, respectively. Each slice has two multiplexers with F5MUX in the bottom portion of the slice and FiMUX in the top portion. Depending on the slice, the FiMUX takes on the name F6MUX, F7MUX, or F8MUX, according to its position in the multiplexer chain. The lower SLICEL and SLICEM both have an F6MUX. The upper SLICEM has an F7MUX, and the upper SLICEL has an F8MUX. The carry chain enters the bottom of the slice as CIN and exits at the top as COUT. Five multiplexers control the chain: CYINIT, CY0F, and CYMUXF in the bottom portion and CY0G and CYMUXG in the top portion. The dedicated arithmetic logic includes the exclusive-OR gates XORF and XORG (bottom and top portions of the slice, respectively) as well as the AND gates FAND and GAND (bottom and top portions, respectively).

Block RAM Overview:Spartan-3E devices incorporate 4 to 36 dedicated block Rams, which are organized as dualport configurable 18 Kbit blocks. Functionally, the block RAM is identical to the Spartan-3 architecture block RAM. Block RAM synchronously stores large amounts of data while distributed RAM, previously described, is better suited for buffering small amounts of data anywhere along signal paths. This section describes basic block RAM functions. Each block RAM is configurable by setting the contents initial values, default signal value of the output

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registers, port aspect ratios, and write modes. Block RAM can be used in single-port or dualport modes.

Arrangement of RAM Blocks on Die:The block RAMs are located together with the multipliers on the die in one or two columns depending on the size of the device. The XC3S100E has one column of block RAM. The Spartan-3E devices ranging from the XC3S250E to XC3S1600E have two columns of block RAM. Table 6 shows the number of RAM blocks, the data storage capacity, and the number of columns for each device. Row(s) of CLBs are located above and below each block RAM column. Immediately adjacent to each block RAM is an embedded 18x18 hardware multiplier. The upper 16 bits of the block RAM's Port A Data input bus are shared with the upper 16 bits of the A multiplicand input bus of the multiplier. Similarly, the upper 16 bits of Port B's data input bus are shared with the B multiplicand input bus of the multiplier. Table 3.6: Number of RAM Blocks by Device

The Internal Structure of the Block RAMThe block RAM has a dual port structure. The two identical data ports called A and B permit independent access to the common block RAM, which has a maximum capacity of 18,432 bits, or 16,384 bits with no parity bits. Each port has its own dedicated set of data, control, and clock lines for synchronous read and write operations. There are four basic data paths, as shown in Figure 3.11: 1. Write to and read from Port A 2. Write to and read from Port B

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3. Data transfer from Port A to Port B 4. Data transfer from Port B to Port A

Figure 3.11: Block RAM Data Paths

Number of PortsA choice among primitives determines whether the block RAM functions as dual- or singleport memory. A name of the form RAMB16_S[wA]_S[wB] calls out the dual-port primitive, where the integers wA and wB specify the total data path width at ports A and B, respectively. Thus, a RAMB16_S9_S18 is a dual-port RAM with a 9-bit Port A and an 18-bit Port B. A name of the form RAMB16_S[w] identifies the single-port primitive, where the integer w specifies the total data path width of the lone port A. A RAMB16_S18 is a singleport RAM with an 18-bit port. Dedicated Multipliers: The Spartan-3E devices provide 4 to 36 dedicated multiplier blocks per device. The multipliers are located together with the block RAM in one or two columns depending on device density. Operation:-

The multiplier blocks primarily perform twos complement numerical multiplication but can also perform some less obvious applications, such as simple data storage and barrel shifting. Logic slices also implement efficient small multipliers and thereby supplement the dedicated multipliers.

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The Spartan-3E dedicated multiplier blocks have additional features beyond those provided in Spartan-3 FPGAs. Each multiplier performs the principle operation P = A B, where A and B are 18-bit words in twos complement form, and P is the full-precision 36-bit product, also in twos complement form. The 18-bit inputs represent values ranging from -131,07210 to +31,07110 with a resulting product ranging from -17,179,738,11210 to +17,179,869,18410. Use the MULT18X18SIO primitive Connect the appropriate signals implement multipliers with inputs less than 18 bits by sign-extending the inputs (i.e., replicating the most-significant bit). Wider multiplication operations are performed by combining the dedicated multipliers and slice-based logic in any viable combination or by time-sharing a single multiplier. Perform unsigned multiplication by restricting the inputs to the positive range. Tie the most-significant bit Low and represent the unsigned value in the remaining 17 lesser-significant bits.

(a) Asynchronous 18-bit Multiplier

(b) 18-bit Multiplier with Register

Figure-1.12 multiplier

Digital Clock Manager (DCM)

Spartan-3E FPGAs have two, four, or eight DCMs, depending on device size. The variable phase shifting feature functions differently on Spartan-3E FPGAs than from Spartan-3 FPGAs. The Spartan-3E DLLs support lower input frequencies, down to 5 MHz. Spartan-3 DLLs support down to18 MHz.

Overview of DCM:Spartan-3E Digital Clock Managers (DCMs) provide flexible, complete control over clock frequency, phase shift and skew. To accomplish this, the DCM employs a Delay-Locked Loop (DLL), a fully digital control system that uses feedback to maintain clock signal
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characteristics with a high degree of precision despite normal variations in operating temperature and voltage. This section provides a fundamental description of the DCM.The XC3S100E FPGA has two DCMs, one at the top and one at the bottom of the device. The XC3S250E and XC3S500E FPGAs each include four DCMs, two at the top and two at the bottom. The XC3S1200E and XC3S1600E FPGAs contain eight DCMs with two on each edge. The DCM in Spartan-3E FPGAs is surrounded by CLBs within the logic array and is no longer located at the top and bottom of a column of block RAM as in the Spartan-3 architecture. The Digital Clock Manager is instantiated within a design using a DCM primitive. The DCM supports three major functions:

Figure1.13: DCM Functional Blocks and Associated Signals

Clock-skew Elimination:Clock skew within a system occurs due to the different arrival times of a clock signal at different points on the die, typically caused by the clock signal distribution network. Clock skew increases setup and hold time requirements and increases clock-to-out times, all of which are undesirable in high frequency applications. The DCM eliminates clock skew by phase-aligning the output clock signal that it generates with the incoming clock signal. This mechanism effectively cancels out the clock distribution delays.

Frequency Synthesis:

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The DCM can generate a wide range of different output clock frequencies derived from the incoming clock signal. This is accomplished by either multiplying and/or dividing the frequency of the input clock signal by any of several different factors.

Phase Shifting:
The DCM provides the ability to shift the phase of all its output clock signals with respect to the input clock signal. The CM as four functional components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), the Phase Shifter (PS), and the Status Logic. Each component has its associated signals, as shown in Figure 3.13.

ConfigurationDifferences from Spartan-3 FPGAs In general, Spartan-3E FPGA configuration modes are a superset to those available in Spartan-3 FPGAs. Two new modes added in Spartan-3E FPGAs provide a glue-less configuration interface to neither industry-standard parallel NOR Flash and SPI serial Flash memories. Unlike Spartan-3 FPGAs, nearly all of the Spartan-3E configuration pins become available as user I/Os after configuration.

Configuration ProcessThe function of a Spartan-3E FPGA is defined by loading application-specific configuration data into the FPGAs internal, reprogrammable CMOS configuration latches (CCLs), similar to the way a microprocessors function is defined by its application program. For FPGAs, this configuration process uses a subset of the device pins, some of which are dedicated to configuration; other pins are merely borrowed and returned to the application as generalpurpose user I/Os after configuration completes. Spartan-3E FPGAs offer several configuration options to minimize the impact of configuration on the overall system design. In some configuration modes, the FPGA generates a clock and loads itself from an external memory source, either serially or via a byte-wide data path. Alternatively, an external host such as a microprocessor downloads the FPGAs configuration data using a simple synchronous serial interface or via a byte-wide peripheral-style interface. Furthermore, multiple-FPGA designs share a single configuration memory source, creating a structure called a daisy chain. Three FPGA pinsM2, M1, and M0select the desired configuration

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mode. The mode pin settings appear in Table 7. The mode pin values are sampled during the start of configuration when the FPGAs INIT_B output goes High. After the FPGA completes configuration, the mode pins are available as user I/Os.

Table 3.7: Spartan-3E Configuration Mode Options and Pin Settings

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3.5 Merits, demerits and comparison of FPGA: Merits of FPGA:

FPGA- based design is the very short turn-around time, i.e., the time required from the start of the design process until a functional chip is available. No physical manufacturing step is necessary for customizing the FPGA chip. FPGA offers very valuable option. A tightly integrated design environment for high-complexity FPGA design. Easy to learn and use

Demerits of FPGA:
The typical price of FPGA chips is usually higher than other alternatives of the same design, but for small volume production of chips and for fast prototyping. FPGA chip is volatile.

Chapter -4 Introduction to Spartan-3E Kit

4.1 Overview of Spartan 3e The Spartan 3E Starter Board provides a powerful and highly advanced self-contained development platform for designs targeting the Spartan 3E FPGA from Xilinx. It features a 500K gate Spartan 3E FPGA with a 32 bit RISC processor and DDR interfaces. The board also features a Xilinx Platform Flash, USB and JTAG parallel programming interfaces with numerous FPGA configuration options via the onboard Intel Strata Flash and ST Microelectronics Serial Flash. The board is fully compatible with all versions of the Xilinx ISE tools including the free Web Pack. The board ships with a power supply and USB

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cable for programming so designs can be implemented immediately with no hidden costs. The Spartan 3E Starter board is also compatible with the Micro Blaze Embedded Development Kit (EDK) and Pico Blaze from Xilinx.

Key Components and Features The key features of the Spartan-3E Starter Kit board are: Xilinx XC3S500E Spartan-3E FPGA Up to 232 user-I/O pins 320-pin FBGA package Over 10,000 logic cells

Xilinx 4 Mbit Platform Flash configuration PROM Xilinx 64-macrocell XC2C64A CoolRunner CPLD 64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)

FPGA configuration storage MicroBlaze code storage/shadowing 16 Mbits of SPI serial Flash (STMicro)

FPGA configuration storage MicroBlaze code shadowing 2-line, 16-character LCD screen PS/2 mouse or keyboard port VGA display port

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10/100 Ethernet PHY (requires Ethernet MAC in FPGA) Two 9-pin RS-232 ports (DTE- and DCE-style) On-board interface USB-based FPGA/CPLD download/debug

50 MHz clock oscillator SHA-1 1-wire serial EEPROM for bit stream copy protection

Hirose FX2 expansion connector Three Diligent 6-pin expansion connectors Four-output, SPI-based Digital-to-Analog Converter (DAC) Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain pre-amplifier

Chip Scope Soft Touch debugging port Rotary-encoder with push-button shaft Eight discrete LEDs Four slide switches

4.1.1 Design Trade-Offs

A few system-level design trade-offs were required in order to provide the Spartan-3E Starter Kit board with the most functionality. Configuration Methods Galore A typical FPGA application uses a single non-volatile memory to store configuration images. To demonstrate new Spartan-3E capabilities, the starter kit board has three different configuration memory sources that all need to function well together. The extra configuration functions make the starter kit board more complex than typicalSpartan-3E applications. The starter kit board also includes an on-board USB-based JTAG programming interface. The onchip circuitry simplifies the device programming experience. In typical applications, the
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JTAG programming hardware resides off-board or in a separate programming module, such as the Xilinx Platform USB cable.

Voltages for all Applications The Spartan-3E Starter Kit board showcases a triple-output regulator developed by Texas Instruments, the TPS75003 specifically to power Spartan-3 and Spartan-3E FPGAs. This regulator is sufficient for most stand-alone FPGA applications. However, the starter kit board includes DDR SDRAM, which requires its own high-current supply. Similarly, the USBbased JTAG download solution requires a separate 1.8V supply.

4.2 Switches, Buttons and Knobs 4.2.1 Slide Switches Locations and Labels

The Spartan-3E Starter Kit board has four slide switches, as shown in Figure 2.1.1. The Slide switches are located in the lower right corner of the board and are labeled SW3 through SW0. Switch SW3 is the left-most switch, and SW0 is the right-most switch.

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Fig.4.2.1 Four Slide Switches Operation When in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic High. When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active de bouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board.

UCF Location Constraints Figure 4.2.2 provides the UCF constraints for the four slide switches, including the I/O pin assignment and the I/O standard used. The PULLUP resistor is not required, but it defines the input value when the switch is in the middle of a transition.

Fig.4.2.2 UCF Constraints for Slide Switches Push-Button Switches Locations and Labels

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The Spartan-3E Starter Kit board has four momentary-contact push-button switches, shown in Figure 2.2.3. The push buttons are located in the lower left corner of the board and are labeled BTN_NORTH, BTN_EAST, BTN_SOUTH, and BTN_WEST. The FPGA pins that connect to the push buttons appear in parentheses in Figure 2.2.3 and the associated UCF appears in Figure 4.2.5.

Fig.4.2.3 Four Push-Button Switches Surround Rotary Push-Button Switch

Operation

Pressing a push button connects the associated FPGA pin to 3.3V, as shown in Figure 4.2.4.Use an internal pull-down resistor within the FPGA pin to generate a logic Low when the button is not pressed. Figure 2-5 shows how to specify a pull-down resistor within the UCF. There is no active de bouncing circuitry on the push button.

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Fig.4.2.4 Push-Button Switches Require an Intternal Pull Down Resistor in FPGA input pin UCF Location Constraints

Figure 4.2.5 provides the UCF constraints for the four push-button switches, including the I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each input.

Fig.4.2.5 UCF Constraints for Push Button Switches Rotary Push-Button Switch Locations and Labels

The rotary push-button switch is located in the center of the four individual push-button switches, as shown in Figure 2.1.3. The switch produces three outputs. The two shaft encoder outputs are ROT_A and ROT_B. The center push-button switch is ROT_CENTER.

Operation

The rotary push-button switch integrates two different functions. The switch shaft rotates and outputs values whenever the shaft turns. The shaft can also be pressed, acting as a pushbutton switch. Push-Button Switch Pressing the knob on the rotary/push-button switch connects the associated FPGA pin to 3.3V, as shown in Figure 2.2.6. Use an internal pull-down resistor within the FPGA pin to generate a logic Low. Figure 2.2.9 shows how to specify a pull-down resistor within the UCF. There is no active de bouncing circuitry on the push button.

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Fig.4.2.6 Push-Button Switches Require an Intternal Pull Up Resistor in FPGA input pin Rotary Shaft Encoder In principal, the rotary shaft encoder behaves much like a cam, connected to central shaft. Rotating the shaft then operates two push-button switches, as shown in Figure 2.2.7. Depending on which way the shaft is rotated, one of the switches opens before the other. Likewise, as the rotation continues, one switch closes before the other. However, when the shaft is stationary, also called the detent position, both switches are closed.

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Fig.4.2.7 Basic example of rotary shaft encoder circuitry Closing a switch connects it to ground, generating a logic Low. When the switch is open, a pull-up resistor within the FPGA pin pulls the signal to a logic High. The UCF constraints in Figure 4.2.9 describe how to define the pull-up resistor. The FPGA circuitry to decode the A and B inputs is simple, but must consider the mechanical switching noise on the inputs, also called chatter. As shown in Figure 2.1.8, the chatter can falsely indicate extra rotation events or even indicate rotations in the opposite direction! See the Rotary Encoder Interface reference design in Related Resources for an example.

Fig. 4.2.8 Outputs from Rotary Shaft Encoder May Include Mechanical Chatter UCF Location Constraints Figure 4.2.9 provides the UCF constraints for the four push-button switches, including the I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each input. Discrete LEDs Locations and Labels

The Spartan-3E Starter Kit board has eight individual surface-mount LEDs located above the slide switches as shown in Figure 2-10. The LEDs are labeled LED7 through LED0. LED7 is the left-most LED, LED0 the right-most LED.

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Fig.4.2.10 Eight Discrete LEDs UCF Location Constraints

Figure 4.2.11 provides the UCF constraints for the four push-button switches, including the I/O pin assignment, the I/O standard used, the output slew rate, and the output drive current.

Figure 4.2.11: UCF Constraints for Eight Discrete LED

4.3 Clock Sources Overview As shown in Figure 4.3.1, the Spartan-3E Starter Kit board supports three primary clock input sources, all of which are located below the Xilinx logo, near the Spartan-3E logo. The board includes an on-board 50 MHz clock oscillator. Clocks can be supplied off-board via an SMA-style connector. Alternatively, the FPGA can generate clock signals or other high-speed signals on the SMA-style connector.

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Optionally install a separate 8-pin DIP-style clock oscillator in the supplied socket.

Fig.4.3.1 Available Clock Inputs Clock Connection

Each of the clock inputs connect directly to a global buffer input in I/O Bank 0, along the top of the FPGA. As shown in Table 3-1, each of the clock inputs also optimally connects to an associated DCM. Voltage Control

The voltage for all I/O pins in FPGA I/O Bank 0 is controlled by jumper JP9. Consequently, these clock resources are also controlled by jumper JP9. By default, JP9 is set for 3.3V. The on-board oscillator is a 3.3V device and might not perform as expected when jumper JP9 is set for 2.5V.

50 MHz On-Board Oscillator

The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The oscillator is accurate to 2500 Hz or 50 ppm. Auxiliary Clock Oscillator Socket

The provided 8-pin socket accepts clock oscillators that fit the 8-pin DIP footprint. Use this socket if the FPGA application requires a frequency other than 50 MHz. alternatively, use the FPGAs Digital Clock Manager (DCM) to generate or synthesize other frequencies from the on-board 50 MHz oscillator. SMA Clock Input or Output Connector

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To provide a clock from an external source, connect the input clock signal to the SMA connector. The FPGA can also generate a single-ended clock output or other high-speed signal on the SMA clock connector for an external device. UCF Constraints

The clock input sources require two different types of constraints. The location constraints define the I/O pin assignments and I/O standards. The period constraints define the clock periodand consequently the clock frequencyand the duty cycle of the incoming clock signal. Location

Figure 2.3.2 provides the UCF constraints for the three clock input sources, including the I/O pin assignment and the I/O standard used. The settings assume that jumper JP9 is set for 3.3V. If JP9 is set for 2.5V, adjust the IOSTANDARD settings accordingly.

Fig.4.3.2 UCF Location Constraints for Clock Sources Clock Period Constraints

The Xilinx ISE development software uses timing-driven logic placement and routing. Set the clock PERIOD constraint as appropriate. An example constraint appears in Figure 3-3 for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is 50 MHz, which equates to a 20 ns period. The output duty cycle from the oscillator ranges between 40% to 60%.

Fig.4.3.3 UCF Clock PERIOD Constant 2.4 FPGA Configuration Options

The Spartan-3E Starter Kit board supports a variety of FPGA configuration options: Download FPGA designs directly to the Spartan-3E FPGA via JTAG, using the onboard

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USB interface. The on-board USB-JTAG logic also provides in-system programming for the on-board Platform Flash PROM and the Xilinx XC2C64A CPLD.

SPI serial Flash and Strata Flash programming are performed separately. Program the on-board 4 Mbit Xilinx XCF04S serial Platform Flash PROM, then configure the FPGA from the image stored in the Platform Flash PROM using Master Serial mode.

Program the on-board 16 Mbit ST Microelectronics SPI serial Flash PROM, then configure the FPGA from the image stored in the SPI serial Flash PROM using SPI mode.

Program the on-board 128 Mbit Intel StrataFlash parallel NOR Flash PROM, then configure the FPGA from the image stored in the Flash PROM using BPI Up or BPI

Down configuration modes. Further, an FPGA application can dynamically load two different FPGA configurations using the Spartan-3E FPGAs MultiBoot mode. See the Spartan-3E data sheet (DS312) for additional details on the MultiBoot feature. Figure 4.3.1 indicates the position of the USB download/programming interface and the onboard non-volatile memories that potentially store FPGA configuration images. Figure 4.3.2 provides additional details on configuration options.

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Fig. 4.3.1 Spartan -3E Starter Kit FPGA Configuration Options

Fig. 4.3.2 Detailed Configuration Objects The configuration mode jumpers determine which configuration mode the FPGA uses when power is first applied, or whenever the PROG button is pressed. The DONE pin LED lights when the FPGA successfully finishes configuration. Pressing the PROG button forces the FPGA to restart its configuration process. The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial mode. The 64-macrocell XC2C64A CoolRunner II CPLD provides additional programming capabilities and flexibility when using the BPI Up, BPI Down, or MultiBoot configuration

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modes and loading the FPGA from the Strata Flash parallel Flash PROM. The CPLD is user programmable. Configuration Mode Jumpers As shown in Table 4.3.1, the J30 jumper block settings control the FPGAs configuration mode. Inserting a jumper grounds the associated mode pin. Insert or remove individual jumpers to select the FPGAs configuration mode and associated configuration memory source.

Table 4.1 Spartan 3E Configuration Mode Jumper Settings

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PROG Push Button The PROG push button, shown in Figure 4-2, page 26, forces the FPGA to reconfigure from the selected configuration memory source. Press and release this button to restart the FPGA configuration process at any time. DONE Pin LED The DONE pin LED, shown in Figure 4-2, , lights whenever the FPGA is successfully configured. If this LED is not lit, then the FPGA is not configured. Programming the FPGA, CPLD, or Platform Flash PROM via USB

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As shown in Figure 4-1, page 25, the Spartan-3E Starter Kit includes embedded USB-based programming logic and an USB endpoint with a Type B connector. Via a USB cable connection with the host PC, the iMPACT programming software directly programs the FPGA, the Platform Flash PROM, or the on-board CPLD. Direct programming of the parallel or serial Flash PROMs is not presently supported. Connecting the USB Cable The kit includes a standard USB Type A/Type B cable, similar to the one shown in Figure 2.4.3. The actual cable color might vary from the picture

Fig4.3.3. Standard USB Type A /Type B The wider and narrower Type A connector fits the USB connector at the back of the computer. After installing the Xilinx software, connect the square Type B connector to the Spartan-3E Starter Kit board, as shown in Figure 4-4. The USB connector is on the left side of the board, immediately next to the Ethernet connector. When the board is powered on, the Windows operating system should recognize and install the associated driver software.

Fig.4.4.4 Connect the USB Type B Connector to the Starter Kit Board Connector

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When the USB cable driver is successfully installed and the board is correctly connected to the PC, a green LED lights up, indicating a good connection. Programming via iMPACT After successfully compiling an FPGA design using the Xilinx development software, the design can be downloaded using the iMPACT programming software and the USB cable. To begin programming, connect the USB cable to the starter kit board and apply power to the board. Then, double-click Configure Device (iMPACT) from within Project Navigator, as shown in Figure 2.4.5.

Fig.4.4.5 Double Click to Invoke iMPACT

2.5 VGA Display

The Spartan-3E Starter Kit board includes a VGA display port via a DB15 connector. Connect this port directly to most PC monitors or flat-panel LCDs using a standard monitor cable. As shown in Figure 6-1, the VGA connector is the left-most connector along the top of the board.

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Fig.2.5.1 VGA Connections from Spartan-3E Starter Kit The Spartan-3E FPGA directly drives the five VGA signals via resistors. Each color line has a series resistor, with one bit each for VGA_RED, VGA_GREEN, and VGA_BLUE. The series resistor, in combination with the 75 termination built into the VGA cable, ensures that the color signals remain in the VGA-specified 0V to 0.7V range. The VGA_HSYNC and VGA_VSYNC signals using LVTTL or LVCMOS33 I/O standard drive levels. Drive the VGA_RED, VGA_GREEN, and VGA_BLUE signals High or Low to generate the eight colors shown in Table 6-1.

Table 5.1 3-Bit Display Color Codes

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VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics Standards Association (VESA). The following VGA system and timing information is provided as an example of how the FPGA might drive VGA monitor in 640 by 480 mode. For more precise information or for information on higher VGA frequencies, refer to documents available on the VESA website or other electronics websites (see Related Resources, page 57).

Signal Timing for a 60 Hz, 640x480 VGA Display

CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCDs use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCDs have evolved to use the same signal timings as CRT displays. Consequently, the following discussion pertains to both CRTs and LCDs. Within a CRT display, current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a raster pattern, horizontally from left to right and vertically from top to bottom. As shown in Figure 6-2, information is only displayed when the beam is moving in the forward directionleft to right and top to bottomand not during the time the beam returns back to the left or top edge of the display. Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass.

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Fig2.5.2 CRT Display Timing Example The display resolution defines the size of the beams, the frequency at which the beam traces across the display, and the frequency at which the electron beam is modulated. Modern VGA displays support multiple display resolutions, and the VGA controller dictates the resolution by producing timing signals to control the raster patterns. The controller produces TTL-level synchronizing pulses that set the frequency at which current flows through the deflection coils, and it ensures that pixel or video data is applied to the electron guns at the correct time. Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location. The Spartan-3E Starter Kit board uses three bits per pixel, producing one of the eight possible colors shown in Table 5-1. The controller indexes into the video data buffer as the beams move across the display. The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel. As shown in Figure 2.5.2, the VGA controller generates the horizontal sync (HS) and vertical sync (VS) timings signals and coordinates the delivery of video data on each pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the refresh frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the displays phosphor and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz range. The number of horizontal lines displayed at a given refresh frequency defines the horizontal retrace frequency.
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VGA Signal Timing

The signal timings in Table 6-2 are derived for a 640-pixel by 480-row display using a 25 MHz pixel clock and 60 Hz 1 refresh. Figure 6-3 shows the relation between each of the timing symbols. The timing for the sync pulse width (TPW) and front and back porch intervals (TFP and TBP) are based on observations from various VGA displays. The front and back porch intervals are the pre- and post-sync pulse times. Information cannot be displayed during these times.

Fig.2.5.3 VGA Control Timing Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded counter values generate the HS signal. This counter tracks the current pixel display location on a given row. A separate counter tracks the vertical timing. The vertical-sync counter increments with each HS pulse and decoded values generate the VS signal. This counter tracks the current display row. These two continuously running counters form the address into a video display buffer. For example, the on-board DDR SDRAM provides an ideal display buffer. No time relationship is specified between the onset of the HS pulse and the onset of the VS pulse. Consequently, the counters can be arranged to easily form video RAM addresses, or to minimize decoding logic for sync pulse generation. UCF Location Constraints
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Figure 2.6.4 provides the UCF constraints for the VGA display port, including the I/O pin assignment, the I/O standard used, the output slew rate, and the output drive current.

Fig.2.5.4 UCF Constraints for VGA Display Port

2.6 RS-232 Serial Ports

Overview As shown in Figure 2.6.1, the Spartan-3E Starter Kit board has two RS-232 serial ports: a female DB9 DCE connector and a male DTE connector. The DCE-style port connects directly to the serial port connector available on most personal computers and workstations via a standard straight-through serial cable. Null modem, gender changers, or crossover cables are not required. Use the DTE-style connector to control other RS-232 peripherals, such as modems or printers, or perform simple loopback testing with the DCE connector.
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Fig.2.6.1 RS-232 Serial Ports Figure 2.6.1 shows the connection between the FPGA and the two DB9 connectors. The FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device, which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise, the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. A series resistor between the Maxim output pin and the FPGAs RXD pin protects against accidental logic conflicts. Hardware flow control is not supported on the connector. The ports DCD, DTR, and DSR signals connect together, as shown in Figure 7-1. Similarly, the ports RTS and CTS signals connect together. UCF Location Constraints Figure 2.6.2 and Figure 2.6.3 provide the UCF constraints for the DTE and DCE RS-232 ports, respectively, including the I/O pin assignment and the I/O standard used.

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Fig.2.6.2 UCF Location Constraints for DTERS-232 Serial Port

Fig.2.6.3 UCF Location Constraints for DCE RS-2323 Serial Port

2.7 Digital to Analog Converter (DAC)

The Spartan-3E Starter Kit board includes an SPI-compatible, four-channel, serial DigitaltoAnalog Converter (DAC). The DAC device is a Linear Technology LTC2624 quad DAC with 12-bit unsigned resolution. The four outputs from the DAC appear on the J5 header, which uses the Digilent 6-pin Peripheral Module format. The DAC and the header are located immediately above the Ethernet RJ-45 connector, as shown in Figure 2.7.1

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Fig. 2.7.1 Digital- to- Analog Converter and Associated Header SPI Communication As shown in Figure 2.7.2, the FPGA uses a Serial Peripheral Interface (SPI) to communicate digital values to each of the four DAC channels. The SPI bus is a full-duplex, synchronous, character-oriented channel employing a simple four-wire interface. A bus masterthe FPGA in this exampledrives the bus clock signal (SPI_SCK) and transmits serial data (SPI_MOSI) to the selected bus slavethe DAC in this example. At the same time, the bus slave provides serial data (SPI_MISO) back to the bus master.

Fig.2.7.2 Digital-to-Analog Connection Schematic Interface Signals Table 2.7.1 lists the interface signals between the FPGA and the DAC. The SPI_MOSI, SPI_MISO and SPI_SCK signals are shared with other devices on the SPI bus. The DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is the activeLow, asynchronous reset input to the DAC. Table 2.7.1 DAC Interface Signals

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The serial data output from the DAC is primarily used to cascade multiple DACs. This signal can be ignored in most applications although it does demonstrate full-duplex communication over the SPI bus. Disable Other Devices on the SPI Bus to Avoid Contention The SPI bus signals are shared by other devices on the board. It is vital that other devices are disabled when the FPGA communicates with the DAC to avoid bus contention. Table 2.7.2 provides the signals and logic values required to disable the other devices. Although the Strata Flash PROM is a parallel device, its least-significant data bit is shared with the SPI_MISO signal. Table 2.7.2 Disabled Devices on the SPI Bus

SPI Communication Details Figure2.7 .3 shows a detailed example of the SPI bus timing. Each bit is transmitted or received relative to the SPI_SCK clock signal. The bus is fully static and supports locks rate up to the maximum of 50 MHz. However, check all timing parameters using the LTC2624 data sheet if operating at or close to the maximum speed.

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Fig.2.7.3 SPI Communication Waveforms After driving the DAC_CS slave select signal Low, the FPGA transmits data on the SPI_MOSI signal, MSB first. The LTC2624 captures input data (SPI_MOSI) on the rising edge of SPI_SCK; the data must be valid for at least 4 ns relative to the rising clock edge. The LTC2624 DAC transmits its data on the SPI_MISO signal on the falling edge of SPI_SCK. The FPGA captures this data on the next rising SPI_SCK edge. The FPGA must read the first SPI_MISO value on the first rising SPI_SCK edge after DAC_CS goes Low. Otherwise, bit 31 is missed. After transmitting all 32 data bits, the FPGA completes the SPI bus transaction by returning the DAC_CS slave select signal High. The High-going edge starts the actual digital-to-analog conversion process within the DAC. Communication Protocol Figure 2.7.4 shows the communications protocol required to interface with the LTC2624 DAC. The DAC supports both a 24-bit and 32-bit protocol. The 32-bit protocol is shown. Inside the D/A converter, the SPI interface is formed by a 32-bit shift register. Each 32-bit command word consists of a command, an address, followed by data value. As a new command enters the DAC, the previous 32-bit command word is echoed back to the master. The response from the DAC can be ignored although it is a useful to confirm correct communication.

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Fig.2.7.4 SPI Communications Protocol to LTC2624 DAC The FPGA first sends eight dummy or dont care bits, followed by a 4-bit command. The most commonly used command with the board is COMMAND[3:0] = 0011, which immediately updates the selected DAC output with the specified data value. Following the command, the FPGA selects one or all the DAC output channels via a 4-bit address field. Following the address field, the FPGA sends a 12-bit unsigned data value that the DAC converts to an analog value on the selected output(s). Finally, four additional dummy or dont care bits pad the 32-bit command word. Specifying the DAC Output Voltage As shown in Figure 2.7.2, each DAC output level is the analog equivalent of a 12-bit unsigned digital value, D[11:0], written by the FPGA to the DAC via the SPI interface. The voltage on a specific output is generally described in Equation2.7..1. The reference voltage, VREFERENCE, is different between the four DAC outputs. Channels A and B use a 3.3V reference voltage and Channels C and D use a 2.5V reference. The reference voltages themselves have a 5% tolerance, so there will be slight corresponding variances in the output voltage. DAC Outputs A and B

DAC Outputs C and D

UCF Location Constraints Figure 2.7.5 provides the UCF constraints for the DAC interface, including the I/O pin assignment and the I/O standard used.

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Fig.2.7.5 UCF Location Constraints for the

2.8 Analog Capture Circuit The Spartan-3E Starter Kit board includes a two-channel analog capture circuit, consisting of a programmable scaling pre-amplifier and an analog-to-digital converter (ADC), as shown in Figure 2.8.1. Analog inputs are supplied on the J7 header.

Fig.2.8.1 Two-Channel Analog Capture Circuit The analog capture circuit consists of a Linear Technology LTC6912-1 programmable preamplifier that scales the incoming analog signal on header J7 (see Figure 2.8.2). The output of pre-amplifier connects to a Linear Technology LTC1407A-1 ADC. Both the preamplifier and the ADC are serially programmed or controlled by the FPGA.

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Fig. 2.8.2 Detailed View of Analog Capture Circuit Digital Outputs from Analog Inputs The analog capture circuit converts the analog voltage on VINA or VINB and converts it to a 14-bit digital representation, D[13:0], as expressed by Equation 10-1. The GAIN is the current setting loaded into the programmable pre-amplifier. The various allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs appear in Table 10-2. The reference voltage for the amplifier and the ADC is 1.65V, generated via a voltage divider shown in Figure 2.8.2. Consequently, 1.65V is subtracted from the input voltage on VINA or VINB. The maximum range of the ADC is 1.25V, centered around the reference voltage, 1.65V. Hence, 1.25V appears in the denominator to scale the analog input accordingly. Finally, the ADC presents a 14-bit, twos complement digital output. A 14-bit, twos complement number represents values between -213 and 213-1. Therefore, the quantity is scaled by 8192, or 213. See Programmable Pre-Amplifier to control the GAIN settings on the programmable preamplifier. The reference design files provide more information on converting the voltage applied on VINA or VINB to a digital representation (see Related Resources, page 79). Programmable Pre-Amplifier

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The LTC6912-1 provides two independent inverting amplifiers with programmable gain. The purpose of the amplifier is to scale the incoming voltage on VINA or VINB so that it maximizes the conversion range of the DAC, namely 1.65 1.25V. Interface Table 10-1 lists the interface signals between the FPGA and the amplifier. The SPI_MOSI,SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The AMP_CS signal is the active-Low slave select input to the amplifier. Fig.2.8.1 AMP Interface Signals

Programmable Gain Each analog channel has an associated programmable gain amplifier (see Figure 10-2). Analog signals presented on the VINA or VINB inputs on header J7 are amplified relative to 1.65V. The 1.65V reference is generated using a voltage divider of the 3.3V voltage supply. The gain of each amplifier is programmable from -1 to -100, as shown in Table 2.8.2.

Table 2.8.2Programmable Gain Settings for Pre-Amplifier

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The AMP_DOUT output from the amplifier echoes the previous gain settings. These values can be ignored for most applications. The SPI bus transaction starts when the FPGA asserts AMP_CS Low (see Figure 10-4). The amplifier captures serial data on SPI_MOSI on the rising edge of the SPI_SCK clock signal. The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK. SPI Control Interface Figure 10-3 highlights the SPI-based communications interface with the amplifier. The gain for each amplifier is sent as an 8-bit command word, consisting of two 4-bit fields. The mostsignificant bit, B3, is sent first.

Fig.2.8.3 SPI Serial Interface to Amplifier The AMP_DOUT output from the amplifier echoes the previous gain settings. These values can be ignored for most applications. The SPI bus transaction starts when the FPGA asserts AMP_CS Low (see Figure 10-4). The amplifier captures serial data on SPI_MOSI on the rising edge of the SPI_SCK clock signal. The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK.

Fig.2.8.4 .SPI Timing When Communicating with Amplifier The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency.
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UCF Location Constraints Figure 2.8.5 provides the User Constraint File (UCF) constraints for the amplifier interface, including the I/O pin assignment and I/O standard used.

Fig.2.8.5 UCF Location Constraints for the DAC Interface Analog to Digital Converter (ADC) The LTC1407A-1 provides two ADCs. Both analog inputs are sampled simultaneously when the AD_CONV signal is applied. Interface Table 2.8.3 lists the interface signals between the FPGA and the ADC. The SPI_MOSI, SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is the active-Low, asynchronous reset input to the DAC.

Table 2.8.3 ADC Interface Signals

SPI Control Interface Figure 2.8.6 provides an example SPI bus transaction to the ADC. When the AD_CONV signal goes High, the ADC simultaneously samples both analog channels. The results of this conversion are not presented until the next time AD_CONV is asserted, a latency of one

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sample. The maxim sample rate is approximately 1.5 MHz. The ADC presents the digital representation of the sampled analog values as a 14-bit, twos complement binary value.

Fig.2.8.7 Analog-to-Digital Conversion Interface Figure 2.8.7 shows detailed transaction timing. The AD_CONV signal is not a traditional SPI slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC leaves the SPI_MISO signal in the high-impedance state. Otherwise, the ADC blocks communication to the other SPI peripherals. As shown in Figure 2.8.6, use a 34-cycle communications sequence. The ADC 3-states its data output for two clock cycles before and after each 14-bit data transfer.

Fig.2.8.6 Detailed SPI Timing to ADC

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UCF Location Constraints Figure 2.8.7 provides the User Constraint File (UCF) constraints for the amplifier interface, including the I/O pin assignment and I/O standard used.

Fig.2.8.7 Detailed SPI Timing to ADC Disable Other Devices on the SPI Bus to Avoid Contention The SPI bus signals are shared by other devices on the board. It is vital that other devices are disabled when the FPGA communicates with the AMP or ADC to avoid bus contention. Table 10-4 provides the signals and logic values required to disable the other devices. Although the Strata Flash PROM is a parallel device, its least-significant data bit is shared with the SPI_MISO signal. The Platform Flash PROM is only potentially enabled if the FPGA is set up for Master Serial mode configuration.

Chapter-5 Introduction WEBPACK 11.1

The most popular trend currently is to design in HDL at an RTL level, because logic synthesis tools can create gate level net lists from RTL level design .behavioral synthesis allowed engineers to design directly in terms of algorithms and the behavior of the circuit, and then use EDA tools to do the translation and optimization in each phase of the design. However, behavioral synthesis did not gain widespread acceptance. Today, RTL design

of

Xilinx

ISE

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continues to be very popular. Verilog HDL is also being constantly enhanced to meet of new verification methodology.

3.1 Introduction
The newest version of ISE, version 11.1, adds more innovative technology to help lower logic development and production costs. ISE 11.1 delivers faster performance than any other PLD offering, unequaled high-speed design capabilities, and the easiest to use design software available. ISE slashes design and verification times; getting your customer to market first, ahead of the competition. Unparalleled ease-of-use is a big part of ISE 11.1. With the release of ISE 11.1, Xilinx is now able to offer customers an integrated simulation solution with the new ISE Simulator. Every ISE BaseX and ISE Foundation customer has access to a limited version called ISE Simulator Lite. ISE Foundation customers can upgrade to the ISE Simulator. Modelsim Xilinx Edition III offers extended capabilities in both MXE-III Starter Edition and the full version of MXE-III. MXE-III Starter Edition offers 50% more performance and 20X more capacity! The full version of MXEIII offers 25% more capacity than MXE-II. In addition, MXE-III offers Verilog 2001 support and an enhanced user interface for an even better user experience and faster debugging. ISE 11.1 provides support for the new, gate-optimized Spartan-3E FPGA family. Spartan-3E sets a new standard for the world's lowest cost FPGA. This family of industry-leading, low cost devices is the second generation on 90nm technology. Extending support for Virtex-4 FPGAs, ISE 11.1 offers additional device support in both ISE BaseX and ISE Web PACK. This new support makes it even easier for customers to begin designs targeting FPGAs with the most advanced logic, highest performance, highest density, and greatest memory capacity.

Configuration
The Xilinx ISE 11.1 software release offers three design configurations, all delivered under the Integrated Software Environment (ISE) design family: ISE Foundation 11.1 - ISE Foundation is the industry's most complete programmable logic design performance. This ISE configuration supports all of Xilinx lead logic families and provides everything needed to complete any Xilinx design, seamlessly integrating with the industry's most advanced verification products. Xilinx also offers optional productivity tools designed to work together with ISE Foundation.

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ISE BaseX 11.1 - ISE BaseX is the industries most cost-effective, full featured, PC-based programmable logic design environment for Xilinx leading CPLD and medium density FPGAs. The ISE BaseX configuration provides all of the capabilities contained within ISE Web PACK plus additional tools and device support to help designers complete their programmable logic design faster and help lower design costs. ISE WebPACK 11.1 - the easiest ISE configuration to obtain it's on the Web and free! ISE WebPACK provides everything needed to complete programmable logic designs targeting all leading Xilinx CPLDs and low-density FPGAs. ISE WebPACK combines HDL entry, synthesis, and verification capabilities with the industry's most powerful implementation tools. ISE Webpack is available for Microsoft Windows XP, Windows 2000, and now Red Hat Enterprise Linux 3. Chip Scope Pro On-chip Debugging Tools - The size, speed and board requirements of todays state-of-the-art FPGAs make it difficult to debug designs using traditional logic analysis methods. Chip Scope tools provide a powerful and accurate tool to help verify and debug FPGA designs on-chip, in real-time, and optionally works directly with Agilent Logic Analyzers for even deeper FPGA signal analysis. ChipScope Pro enables the insertion of lowprofile logic and bus analyzer cores into designs. These logic cores allow the user to view all the internal signals and nodes within an FPGA. Trigger conditions and setup are changeable in real-time via the JTAG port without affecting the user logic or requiring recompilation of the user design. Plan Ahead Hierarchical Floor planner - Plan Ahead provides a hierarchical, block-based and incremental design methodology, enabling designers to change only one part of the design and leave the rest intact, shortening design iterations. The hierarchical design planning capability of Plan Ahead includes an advanced graphical user interface (GUI) that makes it easy to use for even inexperienced designers. The intuitive display of device resources, connectivity, logical and physical hierarchy lets designers quickly visualize and fix problem areas. Designers can create and manipulate physical hierarchy independently from logical hierarchy, and simultaneously plan and analyze multiple physical implementations, maximizing design space exploration by more quickly identifying optimal implementations. Modelsim Xilinx Edition III - Modelsim XE III is a complete PC HDL simulation environment that enables designers to verify the HDL source code and functional and timing models of their designs. MXE III includes a complete HDL simulation and debugging
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environment providing 100% VHDL and Verilog language coverage, a source code viewer/editor, waveform viewer, design structure browser, list window, and a host of other features designed to enhance productivity. System Generator for DSP System Generator for DSP is the industrys premier software tool for designing, simulating, and implementing high performance FPGA-based DSP systems. Using System Generator greatly shortens the path from design concept to working hardware through Simplicity, Flexibility, Speed, Power, and Accuracy. The Embedded Development Kit (EDK) is an all-encompassing solution for designing embedded programmable systems and supports the design of processor sub-systems using the IBM PowerPC hard processor core and the Xilinx Micro Blaze soft processor core. The combination of hardware, software development tools and the advanced features of Xilinx FPGAs especially Virtex-II Pro the Platform for Programmable Systems, provides customers with a new level of system design, allowing them to optimize their design performance at any time during the design cycle to meet fast-changing design requirements. The kit includes the Micro Blaze Soft Processor Core that is very popular in a wide variety of embedded applications.

Support
Xilinx Support Services offers an extension of a company's design team. Xilinx delivers comprehensive support services including: o Support.xilinx.com: a designer-centric web site that is available 24 hours a day, 7 days a week o Worldwide phone-based support during working hours o XPERTS Certified Third Party Consultants Program o Customer Education Services o The IP Center: a web-based resource for Cores & IP o Local Field Application Engineers

Steps 1

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Figure 3.1.1 To write and run the verilog program in to the Xilinx project navigator.

Step-2

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Figure 3.1.2 first goes in to the FILE and selects the NEW PROJECT.

Step-3

Figure 3.1.3 Select device family and generated simulation language. In my project I have select Sparten3e and verilog HDL.

Step-4

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Figure 3.1.4 Choose verilog module for the specification language

Step-5

Figure-3.1.5 Input and Output File

Step- 6

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Figure 3.1.6 than we finish the procedure to to build the project and then write the whole code of project in to this screen.

Step-7

Figure 3.1.7 Than checks syntax for this code and launch Modelsim 6.3f for the testing purpos2e

Synthesizing the Circuit to the Xilinx FPGA

Now that you have a correctly simulating VERILOG HDL module, you will have the ISE Web PACK tool synthesize your VHDL to something that can be mapped to the Xilinx FPGA. That is, the VERILOG HDL code will be converted by ISE to some gates that are on the FPGA. To be even more specific, ISE will convert the schematic/Verilog HDL project description into a set of configuration bits that are used to program the Xilinx FPGA. Those configuration bits are in a .bit file and are downloaded to the Xilinx FPGA in this section of the tutorial. You will use your Spartan-3E board for this part of the tutorial. This is known as the Spartan 3E Starter Kit and is a board produced by Xilinx. It is a very feature-laden board with a Spartan 3e XC3S500E FPGA, 64Mbytes of SDRAM, 128Mbits of flash EPROM, A/D and D/A converters, RS232 drivers, VGA, PS/2, USB, and Ethernet connectors, a 16 character two-line LCD, and a lot more.

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Specifically we will need to:

Synthesize the Verilog HDL code into FPGA configuration Assign input and output signals to the correct pins on the FPGA that connect to the switches and LEDs on the S3E board Generate a programming file with all this information (.bit file) Use the impact tools from Xilinx (part of WebPACK) to configure the FPGA through the USB connection.

1. Back in the Sources pane, return to the Synthesis/Implementation view and select your PID CONTROLLER schematic. Now in the bottom (Processes) pane you will see some options including Synthesize XST. Double click on this to synthesize your circuit. After a while you will (hopefully) get the Process Synthesize completed successfully message in the console. If youve already simulated your circuit and found it to do what you want, theres every chance that this will synthesize correctly without problems. In any case, there is lots of interesting information in the synthesis report (the data in the console window). Its worth looking at, although for this amazingly simple example there isnt anything that fascinating. Make sure that you end the process with a green check for this process. If you get something else, especially a red X, youll need to fix errors and resynthesize.

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2. Now, because were headed towards putting this on the Xilinx FPGA on the Spartan-3E board, we need to set some constraints. In particular, we need to tell ISE which pins on the Xilinx chip we want A, B, Cin assigned to so that we can access those from switches, and where we want Cout and Sum so we can see those on the LEDs on the Spartan-3E board. Go to the Processes pane and select I/O Pin Planning Presynthesis from the User Constraints tab.

This will open a whole new tool called Plan Ahead which you can use to set your pin constraints. You may have to agree to add a UCF (Universal Constraints File) file to your project. You should agree to this.

3. The Plan Ahead tools lets you set a number of different types of constraints on how the circuit is mapped to the Xilinx part. For now well just use the pin

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constraints in the UCF file.

You can see a list of the I/O markers from your schematic in the I/O Pins pane. You can set their location in the Location field. How do you know which pins to assign the signals to in order to use the switches and LEDs on the Spartan-3E board? You look in the Spartan-3E Starter Kit Users Manual which is linked to the class web site, and also available from Xilinx . You can find that the four sliding switches on the Spartan-3E board are, from left to right as youre looking at the board with the LCD at the bottom, are on pins N17, H18, L14, and L13. Heres the diagram from the User Guide:

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and the UCF info is:

This tells you how to fill out the information in PlanAhead for the switches. Ill put Cin, A, and B on Sw3, Sw2, and Sw1. 3. The LEDs are also described in the User Guide:

4.

Save the settings. When you exit youll see that a fulladd.ucf file has been added to the project.

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You can also edit TOP.ucf by opening it in a text editor. Its just a text file. 6. With your source file selected (fulladder in this case), double click the Implement Design process in the Processes tab. This will translate the design to something that can physically be mapped to the particular FPGA thats on our board (the xc3s500e5fg320 in this case). You should see a green check mark if this step finishes without issues. If there are issues, you need to read them for clues about what went wrong and what you should look at to fix things. 7. If you expand this Implement Design tab (which is not necessary) you will see that the Implement Design process actually consists of three parts:

Translate: Translate is the first step in the implementation process. The Translate process merges all of the input netlists and design constraint information and outputs a Xilinx NGD (Native Generic Database) file. The output NGD file can then be mapped to the targeted FPGA device.

Map: Mapping is the process of assigning a designs logic elements to the specific physical elements that actually implement logic functions in a device. The Map process creates an NCD (Native Circuit Description) file. The NCD file will be used by the PAR process.

Place and Route (PAR): PAR uses the NCD file created by the Map process to place and route your design. PAR outputs an NCD file that is used by the bit stream generator (BitGen) to create a (.bit) file. The Bit file (see the next step) is whats used to actually program the FPGA.

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8.

At this point you can look at the Design Summary to find out all sorts of things about your circuit. One thing that you might want to check is to click on the Pinout Report and check that your signals were correctly assigned to the pins you wanted them to be assigned to.

9.

Now double click the process: Generate Programming File. This will generate the actual configuration bits into a .bit file that you can use to program your Spartan-3E board to behave like your circuit .

10.

Now that you have the programming file, you can program the Spartan-3E board using the iMPACT tool and the USB cable on your PC/laptop. First, make sure that the jumpers on your Spartan-3E board are installed correctly. In particular, check that the configuration options are correctly set. The configuration options are at the top of the board near the RS232 interfaces.

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The jumpers on the J30 headers must be set for JTAG programming. This means that only the middle pins of the header should have a jumper on them.

11.

Now that you have the jumpers set correctly, you can plug in the power to your Spartan-3E board, and connect the USB cable between the Spartan-3E and your PC. Then when you turn on the power, the PC should recognize the Xilinx cable/board and install the drivers.

12.

Once the PC has recognized the USB connection to the Spartan-3E board, you can use the Process Configure Target Device to start up the iMPACT tool to program the FPGA.

13.

The first time you Configure Target Device for a new project, youll get the following message about setting up an iMPACT file. You can click OK here and start up the iMPACT tool.

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14 tool.

Again, the first time you do this for a given project, youll get the iMPACT

15.

Select Boundary Scan in the iMPACT Flows pane. Right click to initiate the chain. You can continue to assign configuration file (.bit file) to each of the programmable chips on the Spartan-3E board. Note that there are three of them, but only xc3s500e is the only one you should program. The other two are already programmed with supporting tasks on the board. Choose the file that you want to program into the FPGA. In this case its TOP.bit.

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For each of the chips you can choose to open a file (attach a .bit file to that chip) or to bypass. You should choose bypass for the other two chips (the xcf04s and the xc2c64). 16. In the iMPACT screen you should now see the following window which shows the programmable chips and the associated bit files or bypass configurations.

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If you see the following screen, you can click OK without changing the default settings.

17.

Now you can select the Spartan-3E (the xc3s500e) and right click to get a dialog Select Program in this dialog to program the FPGA.

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You should see the following indication that the programming has succeeded. You should also see the xc-done LED (a little yellow LED underneath the J30 jumper on the board) light up if the programming is successful. 18. Your circuit should now be running on the Spartan-3E board. If youve followed this tutorial you should now be able to set the sw3, sw2, and sw1 switches and look for the full adder output on LDE1 and LED0. If you make changes and want to reload the bit file to the FPGA (after making changes, for example), you can restart the iMPACT tool using the Manage Configuration Project (iMPACT) option under Configure Target Device.

19.

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Chapter 6 Solar Power Inverter

1. System configuration The block schematic diagram of FPGA based PWM solar inverter is shown in Fig

The system works under three modes of operation namely: Charging Mode (PV/Grid during sun hour/ available Period) Inverting Mode (Grid Cut off or restricted (load shedding) Period

2. ADAPTIVE POWER CONTROLLER The system works on integration of input Power sources (i.e. PV, Battery) with the Grid/DG Power sources and delivers a consistent Power to varying Load(s) as per user demand. The adaptive power control action is governed by Energy balance equation as follows Load Power = (PV Power / Battery Power + Grid) The status of power flow and logical adaptive control action is shown in Table TABLE 2 STATUS OF INPUT POWER SOURCES AND LOGICAL OUTPUT (1)

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Energy Resources PV

Status Logical

output

12V

1 0

Battery

12 V

1 0

Grid

220V+/-10% Less

1 0

3. Solar Power Regulator: A charge controller, charge regulator or battery regulator limits the rate at which electric current is added to or drawn from electric batteries. It prevents overcharging and may prevent against overvoltage, which can reduce battery performance or lifespan, and may pose a safety risk. It may also prevent completely draining ("deep discharging") a battery, or perform controlled discharges, depending on the battery technology, to protect battery life. The terms "charge controller" or "charge regulator" may refer to either a stand-alone device, or to control circuitry integrated within a battery pack, battery-powered device, or battery recharger. Stand-alone charge controllers

Charge controllers are sold to consumers as separate devices, often in conjunction with solar or wind power generators, for uses such as RV, boat, and off-the-grid home battery storage systems. In solar applications, charge controllers may also be called solar regulators.

A series charge controller or series regulator disables further current flow into batteries when they are full. A shunt charge controller or shunt regulator diverts excess electricity to an auxiliary or "shunt" load, such as an electric water heater, when batteries are full.

Simple charge controllers stop charging a battery when they exceed a set high voltage level, and re-enable charging when battery voltage drops back below that level. Pulse width modulation (PWM) and maximum power point tracker (MPPT) technologies are more electronically sophisticated, adjusting charging rates depending on the battery's level, to allow charging closer to its maximum capacity. Charge controllers may also monitor battery

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temperature to prevent overheating. Some charge controller systems also display data; transmit data to remote displays and data logging to track electric flow over time.

V-I Characteristics INVERTER TOPOLOGY

Inverter is a device which converts the DC power source into AC power a centretap inverter topology has been configured to generate PWM sine wave pulses as shown in Fig .4. The semiconductor Power switches may be controlled to produce a multilevel three output voltage state: Vo = + Vdc Vo = - Vdc Vo = 0 ( T1 closed ) ( T2 closed ) ( Transition from Vcc to - Vcc)

The main switching signal (MSS) and polarity control signals (PCS) for N number of PWM base drive pulses is generated by software program. The PWM control base drive gate signals switch on and off the positive group and negative group of inverter power switching devices and thus produces PWM AC pulses approximated to sine wave as shown in Fig. 5. The PWM pulses as shown in fig.6 are generated by the software using following mathematical expression The PWM pulses as shown in fig.6 are generated by the software using following mathematical expression

Where i = 1 N (number of PWM pulses) Pi = Pulse width of PWM pulses K= (Voltage Regulating Factor (0-1)

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