ELECTRONICS CIRCUIT AND SIMULATION LAB

NIT KURUKSHETRA

ELECTRONICS DEPARTMENT

INDEX
EXPT. NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 NAME OF THE EXPERIMENT DATE TEACHERS SIGNATURE

Learning to capture schematic and use simulation commands To study simulation of Logic Gates To study simulation of Flip-Flops To study simulation of Single stage classA amplifier To study simulation of Phase shift oscillator To study simulation of Square wave generator using Op-Amp To study simulation of Low Pass, High Pass and Band Pass filter To study simulation of Bcd Adder To study simulation of Double stage class A amplifier Familiarization with EDA tools Simulation of 555 multivibrator To study simulation of Look ahead carry generator Simulation of CMOS inverter gate.

EXPERIMENT NO.1
AIM: - Learning to use capture schematic and simulation command
THEORY

ABOUT CAPTURE Captures session log records generated reports and net lists, as well as warning and message error. Capture has easy to use commands available through standard pull down menus and access keys. Customize your working environment through commands available on the option menu Get complete and detailed information through captures online help.

DESIGN AND SCHEMATICS A design stores schematic folders, schematic pages & parts in a single file. A schematic folder contains one or more schematic pages, & the design cache archives all parts & symbols used in the design. Hierarchical parts & pins establish hierarchical connectivity. Offpage connectors establish connectivity within a schematic folder. A complex hierarchy may map many hierarchical blocks to a single schematic folder. A simple hierarchy maps only one hierarchical block to a schematic folder.

PRINTING AND PLOTTING You can print out a schematic page or part from the schematic page editor,part editor,or project manager.

 Print multiple items at once by selecting them in the project manager before printing. Customize the look of your print output using the prefences command. Set ur printer options using the print setup command,or the setup button within the print dialog box.

PROCESSING YOUR DESIGN Use annotate to assign new part reference,or to update existing part reference. Use design rules check to look for design rule violations.Capture provides an ERC matrix to configure test criteria.Capture also places markers to help you locate errors and warnings in your schematic pages. Create a netlist using one of over 30 different formats. Use back annotate and a swap file to transfer packaging information to your schematic design from another tool. Use cross reference or bill of materials to create reports on your design. COMPATIBILITY WITH SDT Capture automatically translate your SDT designs and libraries as you open them . You can save your capture designs and libraries in SDT format using the Save as command on the file menu.

EDITING PROPERTIES Almost every object in capture has a set of properties that you can edit.

 You can edit properties like colors,grid styles,font styles and sizes and hatch patterns on objects.you can also customize these properties on a design by designing basis. Part properties for hierarchical designs can be changed on all part occurences or on a single part occurence. Create your own user defined properties to suit your specific needs.for example you can add a track width property for use with a PCB layout application.

MANAGING PARTS AND LIBRARIES Capture provides a project manager for both design and libraries Move an object from project manager to project manager using the cut and paste commands, or by dragging the object from one window to other. Copy an object from project manager to project manager using the cut and paste commands, or by dragging the object from one window to the other while pressing the CTRL key. You can store schematic folders in libraries for use in multiple designs.

MAKING PARTS Use one of the 20000+parts available in capture,or create your own. Create a part in a library by assigning a part name,part reference prefix,and a PCB footprint. Create a package of parts by choosing a package type and specifying the number of parts in the package. Draw the part using captures drawing tools. Then add and edit pins. Use the view menu to alternate between viewing one part or the entire package.

MAKING CONNECTIONS Use wires to connect parts and symbols directly to each other. End a wire by clicking on a pin, another wire, or by double clicking the left. Create junctions by ending a net on another net or by placing a junction over two crossing nets. Connect two nets that dont touch by placing an identical net alias on the nets. Connect wires to buses using bus entries. Use off page connectors to connect nets across pages in a schematic folder.

ADDING TEXT AND GRAPHICS Use captures drawing tools to create text, ellipses, rectangles, lines, arcs & polygons. Capture supports true type fonts for most visible text. Place bitmaps such as your companys logo, directly on parts or schematic pages. You can edit the size, & color of all graphic objects. You can also change the fill pattern of enclosed object like rectangles, ellipses & polygons. NAVIGATION DESIGNS Use captures project manager to easily navigate your design. Designs in the file view show instances of schematic pages and parts, but not hierarchy.

 Designs in hierarchy vies show occurrences of each instances of schematic pages and parts. The design hierarchy is shown in this view. Use the project manager to browse for and edit parts, nets hierarchical parts off-page connectors & DRC error markers. EDITING A SCHEMATIC PAGE Captures editing commands are easily accessible through standard menus, shortcut keys & pop-up menus. Select multiple objects at once by pressing the left mouse button & dragging the pointer across an area. Select multiple objects one at a time by pressing the CTRL key as you select each point. Drag objects using the mouse. Copy objects using copy & paste commands, or by dragging the objects with the CTRL key pressed. Move objects using the cut & paste commands, or by dragging the objects with the ALT key pressed. Group or ungroup objects to suit your needs. USING COMPONENT INFORMATION SYSTEM Orcad component information system provides an interface to your database of approved parts and other data. Use the part database explorer to display the database parts that are available. You can place parts from a local or client server database,or from resources on the internet.

EXPERIMENT NO. 2 AIM: Study of simulation of logic gates

THEORY: A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. Because the output is also a logic-level value, an output of one logic gate can connect to the input of one or more other logic gates. The logic normally performed is Boolean Logic and is most commonly found in digital circuits. There are 5 basic gates to be studied in this experiment.

NOT GATE: It acts as an inverter circuit whose output is complement of input. If the input is logic 1 then output is logic 0 and vice- versa. TRUTH A 0 1 Y 1 0 TABLE:

AND GATE: The output of AND gate is logic 1 only when both the inputs are at logic1 otherwise the output is logic 0. TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 Y 0 0 0 1

OR GATE: The output of OR gate is logic 1 when one or both the inputs are at logic1 otherwise the output is logic 0.

TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 Y 0 1 1 1

NAND GATE: The output of NAND gate is logic 1 when one or both the inputs are at logic 0 otherwise the output is logic 0. TRUTH TABLE: A B Y 0 0 1 0 1 1 1 0 1 1 1 0

NOR GATE: The output of NOR gate is logic 1 only when both the inputs are at logic 0 otherwise the output is logic 0. TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0

EX-OR GATE: The output of EX-OR gate is logic 1 only when any one of the inputs is at logic1 otherwise the output is logic 0. TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 Y 0 1 1 0

CIRCUIT DIAGRAM:
DSTM1
CLK

U1A 1 1
V

2 0 7404 U2A
V

NOT

DSTM2
CLK

1 3
V

2 7400 U3A 2 1 3 1 7402 U4A 1 3 2 7408 U5A 1 3 2 7432 U6A 1 3 2 7486 1

0
V

NAND

0
V

NOR

AND
V

1
V

OR

0
V

EXOR

INPUT AND OUTPUT WAVEFORMS:

OBSERRVATIONS:

When a particular pulse input was fed, the output was observed to be either high or low. In most cases, the output obtained was as expected from the truth tables shown above. High level (logic 1) was shown at a higher voltage level while low level (Logic 0) was shown at 0 voltage. The outputs can be seen in the graphs.

RESULT: Hence the logic gates have been realized ands studied.

EXPERIMENT-3

AIM: To study the simulation of flip flops. THEORY: FLIP- FLOP:In digital circuits, a flip-flop is a term referring to an electronic circuit that has two stable states and thereby is capable of serving as one bit of memory. A flip-flop is usually controlled by one or two control signals and/or a gate or clock signal. The output often includes the complement as well as the normal output. As flip-flops are implemented electronically, they require power and ground connections

SR FF: The fundamental latch is the simple SR flip-flop , where S and R stand for set and reset respectively. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high even after S returns low; similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low even after R returns low.

('X' denotes a Don't care condition; meaning the signal is irrelevant)

CIRCUIT DIAGRAM:
OFFTIME = 1us S ONTIME = 1us CLK DELAY = 0 STARTVAL = 0 OPPVAL = 1 OFFTIME = 2us CLK ONTIME = 2us CLK DELAY = 0 STARTVAL = 0 OPPVAL = 1 U21A 1 1
V

U13A 3 1 0 2 7400 7400

V

Q0

1 1 OFFTIME = .5us R ONTIME = .5us CLK DELAY = 0 STARTVAL = 0 OPPVAL = 1

U14A U22A 3 2 0 7400 7400 1 3 2

V

Q1

1
V

INPUT AND OU TPUT WAVEFORMS:

JK FF: The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 will hold the current state.

J-K FLIP-FLOP OPERATION:

CIRCUIT DIAGRAM:
X

U31A 1 OFFTIME = 1us K ONTIME = 1us CLK DELAY = 0 STARTVAL = 0 OPPVAL = 1 3 2 1

V

U25A 1 3 X 7400 2 7400 7400 X 2 1 3 Q0

V

U23A

OFFTIME = .5uSJ ONTIME = .5uS CLK DELAY = 0 STARTVAL = 0 OPPVAL = 1

1
V

OFFTIME = 2us CLK ONTIME = 2us CLK DELAY = 0 STARTVAL = 0 OPPVAL = 1 U32A 1 3 2 7400

1 U26A 1 3 X 2 7400 X 2 1

U24A 3 7400 Q1
V

INPUT AND OUTPUT WAVEFORM:

D FF:The Q output always takes on the state of the D input at the moment of a rising clock edge. (or falling edge if the clock input is active low). It is called the D flip-flop for this reason, since the output takes the value of the D input or Data input, and Delays it by one clock count.. Truth table: Clock D Q Qprev 0 1 X X

Rising edge 0 Rising edge 1

Non-Rising X Qprev

CIRCUIT DIAGRAM OF D FF:

OFFTIME = 1uS D ONTIME = 1uS CLK DELAY = 0 STARTVAL = 0 OPPVAL = 1
1

U6A 1 1
V

U5A 3 1 0 2 7400 7400 3 Q0

V

CLK
CLK

1 1
V

U4A 1

0 3

U7A 1 3 2 1

2 7400

Q1
V

0 7400

INPUT AND OUTPUT WAVEFORM:

RESULT: Hence the flip- flops have been simulated successfully.

EXPERIMENT NO. 4 AIM-Study and simulation of single stage Class-A amplifier. THEORY-The Class-A amplifier is simply a common emitter voltage divider amplifier. In this circuit the base terminal of the transistor serves as the input, collector as the output and the emitter is common to both. The input capacitor removes any constant component of the input, and the resistors R1 and R3 bias the transistor so that it will remain in active mode for the entire range of the input. The output is the inverted copy of the ACcomponent of the input that has been amplified by the ratio R2/R4 and shifted by an amount determine by all four resistors. ADVANTAGES OF CLASS-A AMPLIFIER1. It is small and inexpensive. 2. It has excellent frequency response. The gain is constant over the audio frequency range. 3. Its overall amplification is higher than that of other amplifiers. 4. It has minimum possible non-linear distortion because it does not use any coils or transformer which might pick up the undesired signal. Hence,no magnetic fields to interfere with the signal. CIRCUIT DIAGRAM OF SINGLE STAGE CLASS-A AMPLIFIERV3 22 V

R5 R7 90k 5.6k C7 C6 10u V5 R6 10k R8 1k C8 1n R9 100k Q1 16u 40237

INPUT WAVEFORM OF SINGLE STAGE CLASS-A AMPLIFIER

OUTPUT WAVEFORM OF SINGLE STAGE CLASS-A AMPLIFIER

RESULT- Single stage Class-A amplifier has been simulated

EXPERIMENT NO. 5 AIM: Simulation of phase shift oscillator. THEORY: PHASE SHIFT OSCILLATOR: The phase shift oscillator produces positive feedback by using an inverting amplifier and adding another 180 of phase shift with the three high-pass filter circuits. It produces this 180 phase shift for only one frequency:

at which the feedback fraction is B=1/29. CIRCUIT DIAGRAM OF PHASE SHIFT OSCILLATOR:

INPUT WAVEFORM:

OUTPUT WAVEFORM:

RESULT: Hence the phase of the input signal is shifted by 180 degrees.

EXPERIMENT NO. 6 AIM: Simulation of Square Wave Generator. THEORY: SQUARE WAVE GENERATOR: The circuit uses a comparator with both positive and negative feedback to control its output voltage. Because the negative feedback path uses a capacitor while the positive feedback path does not, however, there is a time delay before the comparator is triggered to change state. As a result, the circuit oscillates, or keeps changing state back and forth at a predictable rate. CIRCUIT DIAGRAM OF SQUARE WAVE GENERATOR:

INPUT WAVEFORM:

OUTPUT WAVEFORM:

RESULT: Hence the square wave has been successfully generated

EXPERIMENT NO. 7
AIM: Simulation of Low pass, High pass& Band pass filters. THEORY: Low Pass Filters:These filters reject all the frequencies above cutoff frequency fc.Thus, the pass band for the Low Pass filter is the frequency range 0 to fc and the stop band is frequency range above fc. The actual amount of attenuation for each frequency varies from filter to filter. The frequency response is depicted by,as higher gain run upwards,higher frequencies run to right. In phase response, it is seen Vout lags Vin by some phase angle.Below fc there is no phase shift.The frequency contents of the signal and their powers can be obtained through the fast fourier transform(FFT) of signal. High Pass Filters:These filters reject all frequencies below cut off frequency fc.Thus, the pass band for the High Pass Filter is the frequency range above fc and stop band is the frequency range below fc. The frequency response of a basic high pass filter is actually a mirror image of its low pass counterpart. In Phase Response,it is seen Vout leads Vin by some angle, exactly reverse of low pass filter.This phase angle depends on specific frequency of signal,as compared to cutoff frequency of the filter. The frequency contents of the signal and their powers can be obtained through the fast fourier transform(FFT) of signal. Band Pass Filters: These filters allow transmission of frequencies between two designated cut-off frequencies and reject all other frequencies.A band pass filter has two cut-off frequencies and will have pass band from fc1 to fc2.The fc1 is called as lower cut-off frequency and fc2 is called as the upper cut-off frequency. These can be created by combining a low pass and a high pass filter. The phase response is simply the combination of phase responses of two separate sections. In the case where the two filter sections have the same cutoff frequency, the phase lead from the high-pass section cancels the phase lag from the low-pass section at the cutoff frequency only, so that is the only frequency with no phase shift.The frequency contents of the signal and their powers can be obtained through the fast fourier transform(FFT) of signal.

CIRCUIT DIAGRAMS: (A) LOW PASS FILTER:

0 0 0

V3 C1 .01u
7

15V R1 U1 3 + 10k OS2 5 6 1

R4

15k 2 AD741 V1 5mV

4

V -

V+

OUT OS1

V2 15V R2 10k

0 R3
10k

(B) HIGH PASS FILTER:

0 0 0
V3 R4 15k
7

15V R1 U1 3 + 10k
V +

C1

OS2

5 6 1

.01u 2 4

OUT
V -

OS1

AD741 V1 5mV

V2 15V R2 10k

0 R3
10k

(C) BAND PASS FILTER:

0 0 0 0 0

R4 15k
7

V3 R5 C2 .01u R9 3 15k 2 AD741 U2 +

7

V7 15V R8 OS2 5 10k 6 1

C1 3 .01u 2

15V 10K OS2 5 6 1

U1 +

V+

OUT V-

OS1

V1 5mV V2 V9 15V 15V

0
R2 10k R3 10k R6 10k

V-

AD741

V+

OUT OS1

0
R7 10k

0 0 0

INPUT AND OUTPUT WAVEFORMS: Low pass filter

High pass filter

Band pass filter

RESULT: Filters have been simulated successfully.

EXPERIMENT NO. 8 AIM: To study the BCD adder THEORY: A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD. A BCD adder must include the correction logic in its internal construction. To add 0110 to the binary sum, we use a second 4-bit binary adder. The two decimal digits, together with the input carry, are first added in the top 4-bit binary adder to produce the binary sum. When the output carry is equal to zero, nothing is added to the binary sum. When it is equal to one, binary 0110 is added to the binary sum through the bottom 4bit binary adder. The output carry generated from the bottom binary adder can be ignored since it supplies information already available at the output carry terminal.

CIRCUIT DIAGRAM OF BCD ADDER :

INPU T SIGNAL S
HI

LO

U4 A
1 3 C 4A 4

2 U7 A 12 7410 1 2 13 7404

8 S UA 24 M 10 A1 16 S UB 43 M 4 B3 7 S UB 22 M 11 B1 13 S UC 0 M1

A3

U1 7483 A

14

15

U5 A 1 3 7400 U6 A 1 3 7400 2 2

LO

8 S UA 24 M 10 A1 16 S UB 43 M 4 B3 7 S UB 22 M 11 B1 13 S UC 0 M1

C 4A 4

A3

U2 7483 A

14

15

MSB Y1 Y4 Y3 Y2

OUTP UT SIGNALS

OUTPUT: Sum of 9 and 5.

Result: Hence the BCD adder circuit has been simulated.

EXPERIMENT NO.9 AIM-Study and simulation of double stage Class-A amplifier. THEORYThe Class-A amplifier is simply a common emitter voltage divider amplifier. In this circuit the base terminal of the transistor serves as the input, collector as the output and the emitter is common to both. The input capacitor removes any constant component of the input, and the resistors R1 and R3 bias the transistor so that it will remain in active mode for the entire range of the input. The output is the inverted copy of the AC-component of the input that has been amplified by the ratio R2/R4 and shifted by an amount determine by all four resistors. When two amplifiers are connected in such a way that the output signal of the first serves as the input signal to the second, the amplifier are said to be connected in cascade. Amplifiers are connected in cascade to extend the gains possible with single stage amplifier. From the figure in a double stage RC coupled amplifier, the signal developed across collector resistor R10 of the first stage is coupled to the base of second stage through the coupling capacitor C1. As the coupling from one stage to the next stage is obtained by a coupling capacitor followed by connection to a shunt resistor. Therefore, such amplifiers are called the resistance-capacitance coupled or RC coupled amplifiers. ADVANTAGES OF CLASS-A AMPLIFIER1. It is small and inexpensive. 2. It has excellent frequency response. The gain is constant over the audio frequency range. 3. Its overall amplification is higher than that of other amplifiers. 4. It has minimum possible non-linear distortion because it does not use any coils or transformer which might pick up the undesired signal. Hence,no magnetic fields to interfere with the signal.

CICUIT DIAGRAM AMPLIFIER

OF
0

DOUBLE

STAGE

RC
0

COUPLED

V8 V4 22V R7 22V R5 R2 R1 90k Q2 C3 40237 10u R3 10k R8 1k V5 R6 10k R4 1k C1 1n C5 1n 100k R10 16u 40237 5.6k C2 90k Q3 1.5k C4 16u

INPUT WAVEFORM OF DOUBLE STAGE CLASS-A AMPLIFIER

INPUT AND OUTPUT WAVEFORM OF DOUBLE STAGE AMPLIFIER

RESULT: Double stage amplifier has been simulated.

EXPERIMENT NO. 10

AIM: Familiarization with EDA Tools What are the EDA Tools? Electronic design automation (also known as EDA or ECAD) is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. EDA is often known as CAE (Computer Aided Engineering) and ECAD (Electronic Computer-Aided Design), acknowledging the crucial role EDA plays in the design phase. (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. While the public mostly focuses on the end products and is only moderately aware of the chips and circuits inside, without EDA, there would be nowhere near the number of electronic devices on the market today. The Electronic Design Automation (EDA) industry provides tremendous value to designers with its automated software and services to create and validate electronic designs. The unrelenting drive to produce ever-smaller and more complex electronic components and microprocessors -for use in computers, automobiles, household devices and in thousands of other areas of modern life -- has fueled the need for ultra-powerful EDA platforms to design these systems and subsystems. TYPES OF EDA TOOLS To design electronic devices and ICs, we need EDA tools. And for different electronic devices and ICs we need different types of EDA tools. Some of EDA tools are as follows: 1. Alliance: Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. Advanced verification tools for functional abstraction and static timing analysis are part of the system.Complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator and a data-path compiler.

2. StateCAD: StateCAD automates state machine development in VHDL and Verilog. Using the FSM wizard, complex, concurrent state machines are specified. Random logic and Mealy/Moore outputs are added to complete the design. To meet tough product requirements, StateCAD optimizes the code it generates for speed, area, loading and more. Vendor specific code generation guarantees the design will function, with your tools, as you expect. StateCAD had code generators for all top name products from Synopsys, Viewlogic, Altera, Xilinx, Mentor and more. 3. A|RT Builder: A|RT Builder generates fully synthesizable RT-level VHDL and Verilog HDL from a large subset of ANSI C. A|RT Designer 2.3 lets you interactively drive and explore multiple dedicated hardware architectures from software, using only ANSI-C or System C programs. When the design is optimized, the tool automatically generates a fully synthesizable Verilog or VHDL description. This latest version of the tool has enhancements geared specifically to FPGA architectures from Altera and Xilinx. Available for HP-UX, Sun Solaris and Windows NT platforms. 4. Active-HDL: Active-HDL is a completely integrated, powerful HDL design and simulation environment. Active-HDL is offered in three product configurations to adapt to all design styles. 5. TestBencher Pro: TestBencher Pro generates reactive VHDL and Verilog test benches and bus-functional models from language-independent timing diagrams. Benefits/Application of EDA Tools: 1. EDA tools help the system designer to use the latest technology and explore different design approaches. EDA programs allow the designer to model the systems performance and estimate its power needs. 2. It helps the ASIC logic designers put their logical design ideas into computer form. It also helps them handle the high complexity of integrated circuits.EDA helps the layout designer place and route millions of transistors on the IC. It helps check hundreds of physical and electrical design rules for all those transistors.

3. EDA helps product companies achieve more complex chips with lower cost, and shorter time to market. 4. It helps all of us, wherever we have electronic systemslike in cell phone and satellite communications, TV and personal entertainment products, smarter cars, and even in military systems. Where are EDA Tools used? Engineers use Electronic Design Automation (EDA) tools to design electronic products. Electronic products include just about anything that plugs into the wall or uses a battery for electric power, such as computers, cell phones, digital cameras and communication equipment. Electronics are used in houses, automobiles, aerospace products, and all kinds of industrial products. Neither the electronic products nor the ICs could be mae without the use of EDA tools. EDA is intimately bound to the semiconductor IC and electronic product design industries. Engineers use EDA tools to design electronic systems and ICs

EXPERIMENT NO. 11

AIM: Simulation of 555 multivibrator.

THEORY: The 555 Oscillator is another type of relaxation oscillator for generating stabilized square wave output waveforms of either a fixed frequency of up to 500kHz or of varying duty cycles from 50 to 100%. In the previous 555 Timer tutorial we saw that the Monostable circuit produces a single output one-shot pulse when triggered on its pin 2 Trigger input. In order to get the 555 Oscillator to operate as an AstableMultivibrator, it is necessary to continuously re-trigger the 555 IC after each and every timing cycle. This is basically achieved by connecting the Trigger input (pin 2) and the Threshold input (pin 6) together, thereby allowing the device to act as an astable oscillator. Then the 555 Oscillator has no stable states as it continuously switches from one state to the other. Also the single timing resistor of the previous Monostablemultivibrator circuit has been split into two separate resistors, R1 and R2 with their junction connected to the Discharge input (pin 7). In the 555 Oscillator above, pin 2 and pin 6 are connected together allowing the circuit to re-trigger itself on each and every cycle allowing it to operate as a free running oscillator. During each cycle capacitor, Ccharges up through both timing resistors, R1 and R2 but discharges itself only through resistor, R2 as the other side of R2 is connected to the Discharge terminal, pin 7. Then the capacitor charges up to 2/3Vcc (the upper comparator limit) which is determined by the 0.693(R1+R2)C combination and discharges itself down to 1/3Vcc (the lower comparator limit) determined by the 0.693(R2.C)combination. This results in an output waveform whose voltage level is approximately equal to Vcc - 1.5V and whose output "ON" and "OFF" time periods are determined by the capacitor and resistors combinations.

CIRCUIT DIAGRAM:

INPUT AND OUTPUT WAVEFORMS:

RESULT: Hence the 555 multivibrator has been simulated successfully.

EXPERIMENT NO-12 AIM: Study and simulation of look ahead carry generator. THEORY The sum and carry outputs of any stage cannot be produced until the input carry occurs:this leads to a time delay in the addition process. This delay is known as carry propagation delay. Addition of the LSB position produces a carry into the second position.This carry,when added to the bits of the second position(stage),produces a carry into the third position.The latter carry,when added to the bits of the third position,produces a carry into the last position.The key thing to notice in this example is that the sum bit generated in the last position (MSB) depends on the carry that was generated by the addition in the previous positions.This means that ,adder will not produce correct result until LSB carry has propagated through the intermediate full adders.This represents a time delay that depends on the propagation delay produced in an each full-adder.For example,if each full adder is considered to have a propagation delay of 30ns ,then S3 will not reach its correct value until 90ns after LSB carry is generated.Therefore,total time required to perform addition is 90+30=120ns. This situation becomes much worse if we extend the adder circuit to add a greater number of bits.If the adder were handling 16-bit numbers,the carry propagation delay could be 480ns. One method of speeding up this process by eliminating inter stage carry delay is called look ahead carry addition.This method utilizes logic gates to look at the lower-order bits of the augend and addend to see if a higher-order carry is to be generated.It uses two functions :carry generate and carry propagate.

Circuit diagram :

OUTPUT WAVEFORM :

RESULT:4-bit look ahead carry generator has been simulated.

EXPERIMENT NO. 13 AIM: Simulation of CMOS inverter gate. THEORY:An inverter circuit outputs a voltage representing the opposite logic-level to its input. Inverters can be constructed using a single NMOS transistor or a single PMOS transistor coupled with a resistor. Since this 'resistive-drain' approach uses only a single type of transistor, it can be fabricated at low cost. However, because current flows through the resistor in one of the two states, the resistive-drain configuration is disadvantaged for power consumption and processing speed. Alternately, inverters can be constructed using two complimentary transistors in a CMOS configuration. This configuration greatly reduces power consumption since one of the transistors is always off in both logic states. Processing speed can also be improved due to the relatively low resistance compared to the NMOS-only or PMOS-only type devices. Inverters can also be constructed with Bipolar Junction Transistors (BJT) in either a resistortransistor logic (RTL) or a transistor-transistor logic (TTL) configuration. Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1. An inverter circuit serves as the basic logic gate to swap between those two voltage levels. Implementation determines the actual voltage, but common levels include (0, +5V) for TTL circuits. CIRCUIT DIAGRAM:

INPUT AND OUTPUT WAVEFORMS:

RESULT: CMOS inverter gate has been simulated successfully.