Sunteți pe pagina 1din 25

Introduction to CMOS

Introduction to Circuit Design Lecture Series by Intel

2009 Intel India Pvt Limited. All rights reserved. The information provided in this presentation is intended for the sole use of the recipient and is for educational purposes only. No part of this presentation may be reproduced or transmitted in any form or by any means, including photocopying and recording, without written permission. Permission must also be obtained before any part of this presentation is stored in a retrieval system in any nature. No responsibility can be accepted by Intel India Pvt Limited, the Editorial Board or contributors for action taken as a result of information contained in this presentation. The views expressed in this presentation by the presenter are not necessarily those of the Editorial Board or Intel India Pvt Limited.

Lecture Series
Introduction to CMOS Static CMOS Design CMOS Logic Styles Sequentials & Memory APR 30th APR 30th MAY 21st MAY 21st

Lecture Series
Introduction to CMOS Static CMOS Design CMOS Logic Styles Sequentials & Memory APR 30th APR 30th MAY 21st MAY 21st

Introduction to CMOS
What will we learn? Evolution of Integrated Circuits Scaling trends MOS transistor fundamentals CMOS Inverter characteristics

The Journey
First transistor Bell Labs, 1948

The Journey
First Integrated Circuit Fairchild Semi, 1961

The Journey
Intel 4004 Microprocessor Intel, 1971 * ~2.3K transistors * ~700 Khz * 10um technology

The Journey
Intel Pentium 4 Processor Intel, 2005 * ~125,000K transistors * ~3.8 Ghz * 90nm technology

The Journey
Intel Core i7 Processor Intel, 2008 * ~730,000K transistors * ~3.5 Ghz * 45nm technology

Moores Law
1965, Gordon Moore # of transistors on a chip doubled every 2 years This trend has held true for more than half a century

Why Scaling?
Technology shrinks by 0.7 every generation We can integrate 2x more devices Translates into ~2x cost reduction of a function Hence semiconductors is one of those rare industries which gives us more for the same cost as time goes by There have been design challenges as we have scaled down technology

Design Abstraction Levels


SYSTEM

MODULE + GATE CIRCUIT


Vin Vout

DEVICE
G S n+ D n+

MOS Transistor

NMOS & PMOS


Symbols
p-ch n-ch

Physical Structure
Source
n+

Gate
n+

Drain

Source
p+

Gate
p+

Drain

channel
p-sub

channel
n-sub

Substrate

Substrate

n-ch MOS

p-ch MOS

Threshold Voltage

Modes of Operation
Vgs > Vt ; Vds=0V
Source n+ Gate Drain 0V n+

p-sub n-type channel Substrate depletion layer

n-ch MOS

Modes of Operation
Linear region: Vgs - Vt > Vds > 0V
Source n+ Gate Drain (Vds) n+

p-sub n-type channel Substrate depletion layer

n-ch MOS

Modes of Operation
Saturation region: Vds > Vgs - Vt
Source n+ Gate Drain (Vds) n+

p-sub n-type channel depletion layer Substrate pinch-off region

n-ch MOS

IV Curve
6 5 4 3
Linear Saturation VGS = 1.5V
1.07V
X 10 -4

VGS = 2.5V VDS = VGS - VT


2.07V

1.57V

VGS = 2.0V

2 1 0
cut-off
0.57V

VGS = 1.0V

0.5

1.5
VDS (V)

2.5

Short Channel Effects


Short channel device behavior is mainly due to
velocity saturation
10
5

10

0 0
c=

1.5

(V/m)

CMOS Inverter
VDD

Vin CL

Vout

CMOS Inverter Load Lines


PMOS Vin = 0V
X 10-4

NMOS Vin = 2.5V

Vin = 0.5V

Vin = 2.0V

Vin = 1.0V

Vin = 2V
Vin = 1.5V Vin = 2.0V

Vin = 1.5V

Vin = 1V Vin = 1.5V Vin = 0.5V


Vin = 1.0V Vin = 0.5V

Vin = 2.5V Vout (V)

Vin = 0V

CMOS Inverter VTC


2.5 2
NMOS off PMOS res NMOS sat PMOS res

Vout (V)

1.5 1 0.5 0 0 0.5 1

NMOS sat PMOS sat

NMOS res PMOS sat

NMOS res PMOS off

1.5

2.5

Vin (V)

Introduction to CMOS
What did we learn? Evolution of Integrated Circuits Scaling trends MOS transistor fundamentals CMOS Inverter characteristics

S-ar putea să vă placă și