CSO MODEL PAPER

UNIT 1 1. What is Von Neumann model of computer system? Explain the advantage of this model. 2. What you mean by addressing mode? Explain different addressing mode with suitable example. OR 1. What is instruction fetch decode EAG and execution? Draw instruction cycle flow diagram.

2. What you mean by instruction format? Explain memory reference

instruction. UNIT 2 1. What you mean by Hardwired control unit. Differentiate Hardwired & Micro programmed control unit. 2. How address sequencing is performed in control memory? Explain the working of Micro program Sequencer with the Diagram. OR 1. What is microinstruction format? Explain all fields of microinstruction format.

2. (A)Define the following terms

(a)Micro operation program (b) Microinstruction (c) Control memory (d) Micro

(B) Explain the Booth algorithm for multiplication. Multiply (-6) and 3 UNIT 3 1. What you mean by Data Transfer modes. Explain the working of DMA
HANDLER.

2. What is Asynchronous Transfer mode .explain the strobe and handshaking control?
OR 1. What you mean by input output processor. Explain the need of an Input

Output Interface 2. what is serial communication? Explain simplex half duplex and full duplex. Section 4 1. What you mean by virtual memory? Explain the procedure of converting virtual address into physical address. 2. What is cache memory? Explain the different mapping techniques. OR

2. A Set associative cache memory uses block of four words divided into two block sets. The cache can accommodate total of 2K words from main memory. Main memory size is 128K X 32. (a) Formulate word format for direct mapping, associative mapping and set associative mapping. OR 1. A virtual memory has an address space of 8K words, a memory space of 4k words, and page & block size of 1K words. The following page reference occur during a given interval of time 4 2 7 0 1 2 6 1 4 0 1 0 2 3 5

Determine the page fault if replacement algorithm is (1) FIFO (2) LRU (3) LFU 2. An address space is specified by 24 bits and the corresponding memory space by 16 bits. (a) How many words are there in address space? (b) How many words are there in the memory space? (c) If a page consists of 2K words, how many pages and blocks are there in the system? UNIT 5 1. A non pipeline system takes 100 ns to process a task. The same task can be processes in a six segment pipeline with a clock cycle of 20 ns. Determine the speedup factor for the pipeline for 200 tasks.

OR 2. Explain the space time diagram for a four segment pipeline showing the time it takes to process Eight Instruction. OR 1. What you mean by Pipeline conflicts? Explain the following conflicts with their respective solutions (a) Resource conflicts (b) Data Dependency conflicts (c) Branch conflicts 2. The time delay of the four segments in the pipeline are as follows t1=50 ns t2= 30 ns t3=95 ns t4=45 ns The interface register delay is 5 ns. (a) How long would it take to execute 100 instructions in the pipeline? (b) How can we reduce the total time to about one-half of the time calculated in part 1