Code No: 54102/MT

NR
M.Tech. – I Semester Supplementary Examinations,
September, 2008

ANALOG & DIGITAL IC DESIGN

(Common to Embedded Systems/ VLSI & Embedded Systems)

Time: 3hours Max. Marks:60

Answer any FIVE questions

All questions carry equal marks
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1.a) Derive an expression for ID in both linear and saturation region of a

MOSFET.
b) Derive an expression for the voltage gain of common source single
stage amplifier with resistive load. Draw the variation of gm with
the input voltage.

2.a) Design a two stage CMOS Op amplifier with the following

specifications.
A0 =55000, GBW = 1.2MHz, SR = 2.5v/µsec
b) Discuss the choice of selection of input stage.

3.a) Give a linear model for typeI PLL.

b) A cellular telephone incorporates a 900 MHz phase locked loop to
generate the carrier frequencies. If the low pass filter’s cut off
frequency is 2π × (20KHz) and the output frequency is to be
changed from 901MHz to 901.2MHz, how long does the PLL output
frequency take to settle within 100Hz of its final value?

4.a) Explain briefly about each basic building block of a switched

capacitor circuits.
b) Find the capacitance values needed for a first order switched
capacitor circuit such that its 3-dB point is at 10KHz when a clock
frequency of 100KHz is used. It is also desired that the filter have
zero gain at 50KHz and the dc gain be unity. Assume CA = 1pF.

5.a) Design a 3-input, 5bit multiplexer that fits in a 24-pin IC package.

Write the truth table and draw a logic diagram and logic symbol for
your multiplexer.
b) Show that a 4-bit ones’ – complement with end-around carry is a
feed back sequential circuit.

Contd..2.,
Code No: 54102/MT ::2::

6.a) Give the design flow for high-speed comparator.

b) Explain a simple CMOS non-inverting sample and hold circuit with
clock-feed through cancellation.

7.a) Define the following terms with reference to data converters.

Augment the explanation with the help of one example for each.
i) Accuracy
ii) Resolution
iii) Offset error
iv) Gain error
v) Integral non linearity error.
b) Consider a 3-bit DAC operating with Vref = 4v, with the following
measured voltage values.
{0.011, 0.507, 1.002, 1.501, 1.996, 2.495, 3.491}
i) Find the offset and gain errors in units of LSBs
ii) Find INL and DNL errors
iii) Find the effective number of bits of absolute accuracy.
Find the effective number of bits of relative accuracy.

8.a) Evaluate the average value of quantization error using stochastic

approach and hence deduce the signal to noise ratio for an ADC.
b) Explain the following terms in detail with respect to data
converters.
i) Sampling time uncertainty
ii) Dynamic Range.

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