322170

Intel 5 Series Chipset and Intel 3400 Series Chipset
Specification Update
June 2011
Notice: Intel 5 Series Chipset and Intel 3400 Series Chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
Document Number: 322170-019
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. This document contains information on products in the design phase of development. All products, platforms, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice. All dates specified are target dates, are provided for planning purposes only and are subject to change. This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local sales office that you have the latest datasheet before finalizing a design. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user. Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright 2011, Intel Corporation. All rights reserved.
Contents
Contents
Preface ...................................................................................................................... 7 Affected Documents/Related Documents ................................................................ 7 Nomenclature ..................................................................................................... 7 Summary Tables of Changes...................................................................................... 8 Codes Used in Summary Tables............................................................................. 8 Stepping ................................................................................................. 8 Page....................................................................................................... 8 Status .................................................................................................... 8 Row ....................................................................................................... 8 Errata ................................................................................................................ 9 Specification Changes ........................................................................................ 10 Specification Clarification.................................................................................... 10 Documentation Changes..................................................................................... 11 Identification Information ....................................................................................... 13 Markings .......................................................................................................... 13 PCH Device and Revision Identification ................................................................... 14 Errata ...................................................................................................................... 16 Specification Changes.............................................................................................. 27 Specification Clarification ........................................................................................ 30 Documentation Changes .......................................................................................... 36
Revision History
Revision History
Revision -001 Initial Release Updated Description Date September 2009
-002
Isochronous Packet Truncation Added
Identification Information Markings PCH Device and Revision Identification 6-Errata: Intel 5 Series Chipset and Intel 3400 Series Chipset Full-Speed USB Errata: 7-Intel 5 Series Chipset and Intel 3400 Series Chipset USB Port Stall
with Bulk and Control Traffic, 8-Intel 5 Series Chipset and Intel 3400 Series Chipset SATA SYNC Escape Erratum
January 7, 2010
-003
Added
Errata: 9 - Intel P55, PM55, 3400, and 3420 Chipsets May Not Fully Initialize Intel ME, 10 - Intel 5 Series Chipset and Intel 3400 Series Chipset USB End of Frame When Retrying Packets Issue, 11 - Intel 5 Series Chipset and Intel 3400 Series Chipset USB Transaction Priority Issue, 12 - Intel H55 Express Chipset and Intel 3420 Chipset May Report Incorrect Number of USB Ports, 13 - Intel HM55 Express Chipset May Report Incorrect Number of USB Ports
Added
January 13, 2010
-004
Errata: 14 - Intel 5 Series Chipset and Intel 3400 Series Chipset HPET Writing Timing Issue, 15 - Intel 5 Series Chipset and Intel 3400 Series Chipset USB Full-Speed Port Staggering
Added
February 13, 2010
-005
Errata: 16 - Intel 5 Series Chipset and Intel 3400 Series Chipset USB Device May Slow or Hang, 17- Intel 5 Series Chipset and Intel 3400 Series Chipset USB Low Speed Bulk/Control Transactions, 18- Intel 5 Series Chipset and Intel 3400 Series Chipset May Not Detect Unsolicited SATA COMIINITs, 19- Intel 5 Series Chipset and Intel 3400 Series Chipset SATA Hot Unplug. Specification Clarification: 1. GP_RST_SEL[95:0] Description Updated
Updated:
March 10, 2010
IntelQS57 Chipset High Definition Audio Device ID Updated

-006 Added Documentation Changes: 1. Correct Figure 8-2 S5 to S0 Timing Diagram Updated Errata 17 Removed Bulk Transtion Added Documentation Changes: 2. Update Table 3-1 to include SPI_CS0#. 3. Add Tj Mobile Thermal Junction Operating Temperature limits in Table 8-1. 4. Add sections 5.27.2.9 through 5.27.2.15 to section 5.27 PCH DisPlay Interface. 5. Remove Unit Interval DMI from Table 8-14 Edited Corrected typographical error in Documentation Changes, item #4. Added ACK Updated: Errata: 11- Intel 5 / 3400 Series Chipset Family USB Classic Device Removal Issue Removed Specification Clarification: 1; Documentation Changes: 1~5 that went into the updated datasheet 003 April 14, 2010
-007
May 12, 2010
-008
May 17, 2010
Errata: 20- Intel 5 Series Chipset and Intel 3400 Series Chipset USB Missing
June 9, 2010
-009
Revision History
Revision Added
Description
Date
-010
Revision 3.0 (SATA 6Gb/s) Device Detection , 22 - Intel 5 Series Chipset and Intel 3400 Series Chipset PCI Express* Link Disable Bit. Updated: Specification Clarification: 1- Host WOL Behavior Clarification. Documentation Changes: 1- Correct Table 5-58 PCH supported Audio formats over HDMI and DisplayPort*. Updated: Documentation Changes: 2 - Correct Table 8-8 DC Output Characteristics and Notes 1; 3 - Correct 21.1.2 HSFS-Hardware Sequencing Flash Status Register (SPI Memory Mapped Configuration Registers) ; 4 - Correct 21.4.2 HSFSHardware Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers) Added Chipset. Updated: Specification Clarification: 2 - Display Port Clarification
Errata: 21 - Intel 5 Series Chipset and Intel 3400 Series Chipset Serial ATA
July 14, 2010
-011
August 11, 2010
-012
Errata: 23 - Pixel Corruption Over Integrated LVDS Interface of Intel 5 Series
September 8, 2010
-013
Updated: Errata: 21 - Pixel Corruption Over Integrated LVDS Interface of Intel 5 Series Chipset Added Errata: 24- Intel 5 Series Chipset and Intel 3400 Series Chipset Family Highspeed USB Device False Disconnect. Specification Changes: 1 - SMLink0 Speed Change; 2 - VccVRM Min/Max Change Specification Clarification: 3 - PIRQ Sharing; 4 - t205 Vcc Reference; 5 - Table 227 Power and Ground Signals Documentation Changes: 5 - Correct 13.1.23 GEN1_DECLPC I/F Generic Decode Range 1 Register (LPC I/FD31:F0); 6 - Correct Table 2-28 Functional Strap Definitions; 7 - Correct Table 9-4 Memory Decode Ranges from Processor Perspective; 8 - Correct 10.1.43 OICOther Interrupt Control Register; 9 Miscellaneous Typographical and Omission Error Corrections; 10 - Update Table 28 USB Interface Signals; 11 - Update Note 2 of Table 9-1 PCI Devices and Functions; 12 - Correct 14.2.1 BMIC[P,S]Bus Master IDE Command Register (D31:F2); 13 - Correct 15.2.1 BMIC[P,S]Bus Master IDE Command Register (D31:F5); 14 - Update Table 4-1 PCH System Clock Inputs; 15 - Update Table 220 Clock Interface Signals; 16 - Display Interface Updates; 17 - Correct Table 1-4. Intel 5 Series Chipset Mobile SKUs; 18 - Correct Table 1-3. Intel 5 Series Chipset Desktop SKUs Added Errata: 25- USB Isoch In Transfer Error Issue; 26- USB Full-Speed / Low-Speed Device Removal Issue; 27- USB Babble Detected with SW Overscheduling; 28USB Low-Speed/Full-Speed EOP Issue; 29- USB PLL Control FSM Not Getting Reset on Global Reset; 30- Asynchronous Retries Prioritized Over Periodic Transfers; 31- Incorrect Data for LS or FS USB Periodic IN Transaction; 32- Intel 5 Series and 3400 Series Chipset Family Delayed Periodic Traffic Timeout Issue. Specification Clarification: 6- EHCI Function Numbers; 7- PCI Express* Root Port Function Numbers; 8- t212 Measurement Clarification; 9- Wake Event Causes Update; 10- SGPIO Reference Clock Speed. Documentation Changes: 19- Controller Link Updates; 20- Miscellaneous Typographical Error Corrections II; 21- Remove note 11 on Table 3-3; 22- Remove VccpNAND on Table 8-3 and Table 8-4; 23- Section 8.2 Updates. Update Errata: 14- Intel 5 Series Chipset and Intel 3400 Series Chipset HPET Writing Timing Issue; 21 - Intel 5 Series Chipset and Intel 3400 Series Chipset Serial ATA Revision 3.0 (SATA 6Gb/s) Device Detection Added Specification Clarification: 11- I2C Block Read/Write Buffer Documentation Changes: 24- TEMP_ALERT# Muxing; 25- Causes of Host and Global Resets Update; 26- GPIO18 Toggling Note; 27- Pre-fetch Based Pause Bit Definition; 28- Register Corrections; 29- Display BDF Register Additions; 30Miscellaneous Typographical Error Corrections III Update Errata: 21 - Intel 5 Series Chipset and Intel 3400 Series Chipset Serial ATA 6Gb/s Device Detection
October 13, 2010
-014
November 10, 2010
-015
December 8, 2010
-016
January 12, 2011
-017
February 16, 2011
Revision History
Revision -018 -019
Description Added Documentation Changes: 31- Chapter 8 Table Renumbering; 32- AC Characteristics Notes Additions and Corrections; 33- Table 8-22 Clock Timings Clean Up; 34- Miscellaneous Typographical Error Corrections IV Added Errata: 33- Intel 5 Series Chipset and Intel 3400 Series Chipset Not Responding to Cx Request when USB Async Advance Door Bell is Set; 34- Intel 5 Series Chipset LAN Tx/Rx Hang during heavy bi-directional traffic when Back-toBack
Date
March 16, 2011
April 13, 2011
-020
Added Specification change: 2- VccVRM Min/Max change; 3- determinate and define signal update; 4- AFTERG3 bit name change Specification Clarification: 12- Register and Bit Definition Clarification; 13- GPIO13 Voltage Tolerance; 14- Intel HD Audio Register Accesses; 15- SLP_LAN# Pin Behavior; 16- HDA_DOCK_RST#/GPIO13 Description Clarification Documentation Changes: 35- Absolute Maximum Ratings; 36- USB Register Corrections; 37- Revised Industry Specification; 38- Note Renumbering and Correction on Table 3-1; 39-Power Management Initialization Register updates; 40- chapter 9 Corrections; 41HD Audio Corrections
Jun 13, 2011
Preface
Preface
This document is an update to the specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published.
Affected Documents/Related Documents

Title Intel 5 Series Chipset and Intel 3400 Series Chipset Datasheet Document Number 322169
Nomenclature
Errata are design defects or errors. Errata may cause the behavior of the PCH to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present in all devices. Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification. Specification Clarifications describe a specification in greater detail or further highlight a specifications impact to a complex design situation. These clarifications will be incorporated in any new release of the specification. Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification.
Summary Tables of Changes

The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the PCH product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations:
Codes Used in Summary Tables

Stepping
X: (No mark) or (Blank box): This erratum is fixed in listed stepping or specification change does not apply to listed stepping. Errata exists in the stepping indicated. Specification Change or Clarification that applies to this stepping.
Page
(Page): Page location of item in this document.
Status
Doc: Plan Fix: Fixed: No Fix: Document change or update will be implemented. This erratum may be fixed in a future stepping of the product. This erratum has been previously fixed. There are no plans to fix this erratum.
Row
Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document.
Errata (Sheet 1 of 2)
Erratum Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Stepping Status B2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B3 X X X X X No Fix No Fix No Fix No Fix No Fix Fixed No Fix No Fix Fixed No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix Intel 5 Series Chipset and Intel 3400 Series Chipset High-Speed USB Test J/Test K Output Drive Level Intel 5 Series Chipset and Intel 3400 Series Chipset High-Speed USB 2.0 Vhsoh Intel 5 Series Chipset and Intel 3400 Series Chipset 1.5 Gb/s & 3.0 Gb/s SATA Signal Voltage Level Intel 5 Series Chipset and Intel 3400 Series Chipset SATA Low Power Device Detection Intel 5 Series Chipset and Intel 3400 Series Chipset Intel HD Audio Interface Intermittently Does Not Play Sound Intel 5 Series Chipset and Intel 3400 Series Chipset Full-Speed USB Isochronous Packet Truncation Intel 5 Series Chipset and Intel 3400 Series Chipset USB Port Stall with Bulk and Control Traffic Intel 5 Series Chipset and Intel 3400 Series Chipset SATA SYNC Escape Erratum. Intel P55, PM55, 3400, and 3420 Chipsets May Not Fully Initialize Intel Management Engine Intel 5 Series Chipset and Intel 3400 Series Chipset USB End of Frame When Retrying Packets Issue Intel 5 / 3400 Series Chipset Family USB Classic Device Removal Issue Intel H55 Express Chipset and Intel 3420 Chipset May Report Incorrect Number of USB Ports Intel HM55 Express Chipset May Report Incorrect Number of USB Ports Intel 5 Series Chipset and Intel 3400 Series Chipset HPET Writing Timing Issue Intel 5 Series Chipset and Intel 3400 Series Chipset USB Full-Speed Port Staggering Intel 5 Series Chipset and Intel 3400 Series Chipset USB Devices May Slow or Hang Intel 5 Series Chipset and Intel 3400 Series Chipset USB Low Speed Control Transactions Intel 5 Series Chipset and Intel 3400 Series Chipset May Not Detect Unsolicited SATA COMINITs Intel 5 Series Chipset and Intel 3400 Series Chipset SATA Hot Unplug Intel 5 Series Chipset and Intel 3400 Series Chipset USB Missing ACK Intel 5 Series Chipset and Intel 3400 Series Chipset Serial ATA 6Gb/s Device Detection Intel 5 Series Chipset and Intel 3400 Series Chipset PCI Express* Link Disable Bit Pixel Corruption Over Integrated LVDS Interface of Intel 5 Series Chipset Intel 5 Series Chipset and Intel 3400 Series Chipset Family High-speed USB Device False Disconnect USB Isoch In Transfer Error Issue USB Full-Speed / Low-Speed Device Removal Issue USB Babble Detected with SW Overscheduling USB Low-Speed/Full-Speed EOP Issue USB PLL Control FSM Not Getting Reset on Global Reset Asynchronous Retries Prioritized Over Periodic Transfers Incorrect Data for LS or FS USB Periodic IN Transaction ERRATA
Errata (Sheet 2 of 2)
Erratum Number 32 33 34 Stepping Status B2 X X X B3 X X X No Fix No Fix No Fix Intel 5 Series and 3400 Series Chipset Family Delayed Periodic Traffic Timeout Issue Intel 5 Series Chipset and Intel 3400 Series Chipset Not Responding to Cx Request when USB Async Advance Door Bell is Set Intel 5 Series Chipset LAN Tx/Rx Hang during heavy bi-directional traffic when Back-to-Back ERRATA
Specification Changes
Spec Change Number 1 2 3 4
Stepping
SPECIFICATION CHANGES B2 X X X X B3 X X X X SMLink0 Speed Change VccVRM Min/Max Change Determinate and Define Signals update AfterG3 bit name change
Specification Clarification
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Document Revision 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 SPECIFICATION CLARIFICATIONS Host WOL Behavior Clarification Display Port Clarification PIRQ Sharing t205 Vcc Reference Table 2-27 Power and Ground Signals EHCI Function Numbers PCI Express* Root Port Function Numbers t212 Measurement Clarification Wake Event Causes Update SGPIO Reference Clock Speed I2C Block Read/Write Buffer Register and bit Definition Clarification GPIO13 Voltage Tolerance Intel HD Audio Register Accesses SLP_LAN# Pin Behavior HDA_DOCK_RST#/GPIO13 Description Clarification
10
Documentation Changes (Sheet 1 of 2)

No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Document Revision 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 003 DOCUMENTATION CHANGES Correct Table 5-58 PCH supported Audio formats over HDMI and DisplayPort* Correct Table 8-8 DC Output Characteristics and Note 1 Correct 21.1.2 HSFS-Hardware Sequencing Flash Status Register (SPI Memory Mapped Configuration Registers) Correct 21.4.2 HSFSHardware Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers) Correct 13.1.23 GEN1_DECLPC I/F Generic Decode Range 1 Register (LPC I/FD31:F0) Correct Table 2-28 Functional Strap Definitions Correct Table 9-4 Memory Decode Ranges from Processor Perspective Correct 10.1.43 OICOther Interrupt Control Register Miscellaneous Typographical and Omission Error Corrections Update Table 2-8 USB Interface Signals Update Note 2 of Table 9-1 PCI Devices and Functions Correct 14.2.1 BMIC[P,S]Bus Master IDE Command Register (D31:F2) Correct 15.2.1 BMIC[P,S]Bus Master IDE Command Register (D31:F5) Update Table 4-1 PCH System Clock Inputs Update Table 2-20 Clock Interface Signals Display Interface Updates Correct Table 1-4. Intel 5 Series Chipset Mobile SKUs Correct Table 1-3. Intel 5 Series Chipset Desktop SKUs Controller Link Updates Miscellaneous Typographical Error Corrections II Remove note 11 on Table 3-3 Remove VccpNAND on Table 8-3 and Table 8-4 Section 8.2 Updates TEMP_ALERT# Muxing Causes of Host and Global Resets Update GPIO18 Toggling Note Pre-fetch Based Pause Bit Definition Register Corrections Display BDF Register Additions Miscellaneous Typographical Error Corrections III Chapter 8 Table Renumbering AC Characteristics Notes Additions and Corrections Table 8-22 Clock Timings Miscellaneous Typographical Error Corrections IV Absolute Maximum Ratings USB Register Corrections Revised Industry Specification Note Renumbering and Correction on Table 3-1
11
Documentation Changes (Sheet 2 of 2)

No. 39 40 41 Document Revision 003 003 003 DOCUMENTATION CHANGES Power Management Initialization Register updates Chapter 9 Corrections HD Audio Corrections
12
Identification Information
Identification Information
Markings
PCH Stepping B2 B2 B2 B2 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 S-Spec SLGWN SLGWV SLGWX SLGWW SLGZQ SLGZR SLGZS SLGZW SLGZL SLGZX SLH25 SLGZY SLGZV SLH23 SLH24 Top Marking 82PM55 82P55 3400 3420 82QM57 82HM57 82HM55 82Q57 82H57 82H55 3520 3450 82QS57 82PM55 82P55 Intel PM55 Chipset Intel P55 Chipset Intel 3400 Chipset Intel 3420 Chipset Intel QM57 Chipset Intel H57 Chipset Intel HM55 Chipset Intel Q57 Chipset Intel H57 Chipset Intel H55 Chipset Intel 3420 Chipset Intel 3450 Chipset Intel QS57 Chipset Intel PM55 Chipset Intel P55 Chipset Notes
13
PCH Device and Revision Identification

The Revision ID (RID) is traditionally an 8-bit register located at the offset 08h in the PCI header of every PCI device and function. The assigned value is based on the products stepping. Intel 5 Series Chipset and Intel 3400 Series Chipset Device and Revision ID Table (Sheet 1 of 2)
Device Function Description Dev ID1 3B02h 3B03h 3B06h 3B07h 3B08h D31:F0 LPC 3B09h 3B0Ah 3B0Bh 3B0Fh 3B12h 3B14h 3B16h 3B20h 3B21h 3B22h 3B23h D31:F2 SATA 3B25h 3B28h 3B29h 3B2Ch 3B2Eh 3B2Fh B2 Rev ID 05h 05h n/a n/a n/a n/a n/a n/a n/a 05h 05h n/a 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h B3 Rev ID 06h 06h 06h 06h 06h 06h 06h 06h 06h n/a 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h Comments Intel P55 Chipset Intel PM55 Chipset Intel H55 Chipset Intel QM57 Chipset Intel H57 Chipset Intel HM55 Chipset Intel Q57 Chipset Intel HM57 Chipset Intel QS57 Chipset Intel 3400 Chipset Intel 3420 Chipset Intel 3450 Chipset Desktop: Non-AHCI and Non-RAID Mode (Ports 0, 1, 2, 3) Desktop: Non-AHCI and Non-RAID Mode (Ports 0 and 1) Desktop: AHCI (Ports 0-5) Desktop: AHCI (Ports 0, 1, 4 and 5) Desktop RAID: 0/1/5/10 Mobile: Non-AHCI and Non-RAID Mode (Ports 0, 1, 4 and 5) Mobile: AHCI (Ports 0, 1, 4 and 5) Mobile: RAID: 0/1/5/10 Mobile: Non-AHCI and Non-RAID Mode (Ports 0, 1, 2, 3) Mobile: AHCI (Ports 0-5)
14
Intel 5 Series Chipset and Intel 3400 Series Chipset Device and Revision ID Table (Sheet 2 of 2)
Device Function Description Dev ID1 3B26h D31:F5 SATA 3B2Dh D31:F3 D31:F6 D30:F0 D30:F0 D29:F0 D26:F0 D27:F0 D27:F0 D28:F0 D28:F1 D28:F2 D28:F3 D28:F4 D28:F5 D28:F6 D28:F7 D25:F0 D22:F0 D22:F1 D22:F2 D22:F3 SMBus Thermal DMI to PCI Bridge DMI to PCI Bridge USB EHCI #1 USB EHCI #2 Intel High Definition Audio Intel High Definition Audio PCI Express* Port 1 PCI Express Port 2 PCI Express Port 3 PCI Express Port 4 PCI Express Port 5 PCI Express Port 6 PCI Express Port 7 PCI Express Port 8 LAN
3
B2 Rev ID 05h 05h 05h 05h A5h A5h

05h
B3 Rev ID 06h 06h 06h 06h A6h A6h

06h
Comments Desktop: Non-AHCI and Non-RAID Mode (Ports 4 and 5) Mobile: Non-AHCI and Non-RAID Mode (Ports 4 and 5)
3B30h 3B32h 244Eh 2448h 3B34h 3B3Ch 3B56h 3B57h 3B42h 3B44h 3B46h 3B48h 3B4Ah 3B4Ch 3B4Eh 3B50h 3B41h 3B64h 3B65h 3B66h 3B67h
Desktop Mobile
05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h
06h 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h Intel QS57 Chipset Only
Intel MEI #1 Intel MEI #2 IDE-R KT NOTES:

1. 2. 3.
The PCH contains two SATA controllers. The SATA Device ID is dependant upon which SATA mode is selected by BIOS and what RAID capabilities exist in the SKU. The SATA RAID Controller Device ID may reflect a different value based on Bit 7 of D31:F2:Offset 9Ch. LAN Device ID is loaded from EEPROM. If EEPROM contains either 0000h or FFFFh in the Device ID location, then 3B41h is used. Refer to the appropriate Intel GbE Physical Layer Transceiver (PHY) Datasheet for LAN Device IDs.
15
Errata
Errata
1.
Problem: Implication:
Intel 5 Series Chipset and Intel 3400 Series Chipset High-Speed USB Test J/Test K Output Drive Level
Pre-emphasis is not disabled on high-speed USB ports during Test J/Test K. J and K DC voltage levels may exceed USB 2.0 VHSOH-MAX and VHSOL-MAX during Test J/Test K testing and may not meet the USB 2.0 specification.
Workaround: Clear bit 1 of the USB Initialization Registers [0-13] prior to enabling Test J/Test K mode using a memory editing tool. This bit must be set back to 1 for each port after Test J/Test K testing is complete.
Port 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Offset: RCBA + Offset: 3500h 3504h 3508h 350Ch 3510h 3514h 3518h 351Ch 3520h 3524h 3528h 352Ch 3530h 3534h
Status:
No Fix. For steppings affected, see the Summary Table of Changes.
2.
Problem: Implication: Status:
Intel 5 Series Chipset and Intel 3400 Series Chipset High-Speed USB 2.0 Vhsoh
High-Speed USB 2.0 Vhsoh may not meet the USB 2.0 Specification. The maximum expected Vhsoh is 495 mV. Some motherboards may exceed specification limits during USB-IF compliance testing. No Fix. For steppings affected, see the Summary Table of Changes.
Workaround: None.
16
Errata
3.
Problem:
Intel 5 Series Chipset and Intel 3400 Series Chipset 1.5 Gb/s & 3.0 Gb/s SATA Signal Voltage Level
The Intel 5 Series Chipset and Intel 3400 Series Chipset 1.5 Gb/s & 3.0 Gb/s SATA transmit buffers have been designed to maximize performance and robustness over a variety of routing scenarios. As a result, the Intel 5 Series Chipset and Intel 3400 Series Chipset SATA 1.5 Gb/s & 3.0 Gb/s (Gen1i, Gen1m, Gen2i, and Gen2m) transmit signaling voltage levels may exceed the maximum motherboard TX connector and device RX connector voltage specifications (section 7.2.1 of the Serial ATA Specification, rev 2.5). None Known. No Fix. For steppings affected, see the Summary Table of Changes.
Implication: Status:
Workaround: None.
4. Problem:
Intel 5 Series Chipset and Intel 3400 Series Chipset SATA Low Power Device Detection
Intel 5 Series Chipset and Intel 3400 Series Chipset SATA Low Power Device Detection (SLPD) may not recognize, or may falsely detect, a SATA hot-plug event during a Partial or Slumber Link Power Management (LPM) state. On Systems which enable LPM, when a SATA device attached to the Intel 5 Series Chipset and Intel 3400 Series Chipset is configured as External or hot-plug capable, one of the following symptoms may occur: Symptom #1: A hot-plug or External SATA device removal which is not detected results in the OS and Intel Matrix Storage Manager/Intel Rapid Storage Technology console falsely reporting the device present, or incorrectly identifying an eSATA device. Symptom#2:A false hot-plug removal detection may occur resulting in OS boot hang or ODD media playback hang
Implication:
Workaround: A driver workaround is available. Status: No Fix. For steppings affected, see the Summary Table of Changes.
5.
Intel 5 Series Chipset and Intel 3400 Series Chipset Intel HD Audio Interface Intermittently Does Not Play Sound
The Intel 5 Series Chipset and Intel 3400 Series Chipset Intel HD Audio controller logic may not be gated by DMI L1 entry. Systems may intermittently not play sound on the Intel HD Audio interface Following a DMI L1 exit. No Fix. For steppings affected, see the Summary Table of Changes.
Workaround: BIOS workaround available. Status:
17
Errata
6.
Problem:
Intel 5 Series Chipset and Intel 3400 Series Chipset Full-Speed USB Isochronous Packet Truncation
Full-Speed isochronous-out transactions with multi-frame packets may be truncated, in the presence of Full or Low-Speed USB asynchronous transactions. For this to occur, two devices, one performing Full-Speed isochronous-out transactions and one performing asynchronous transactions must be connected to the same USB controller (Ports 0-7 and 8-13).
Implication: Note:
In the case of a USB audio device this issue may result in no audible impact or audible artifacts such as pops and clicks.
High-Speed and Low-Speed USB devices are not impacted by this issue. Only devices supporting Full-Speed isochronous-out transactions that Intel is aware of are audio devices, such as sound adapters, speakers, and headphones. Intel has only observed the issue when a Full-Speed audio devices and Full-Speed USB web camera are connected to the same USB controller. Workaround: None. Status: Fixed For steppings affected, see the Summary Table of Changes.
7.
Problem:
Intel 5 Series Chipset and Intel 3400 Series Chipset USB Port Stall with Bulk and Control Traffic
When a single USB bulk device is active on an EHCI controller, and the device has pending control and bulk traffic the PCH may not be able to resolve which traffic type is a priority and the associated with the device may stall. The processor must be in C0 for an extended period of time such as when Cx states are disabled, or if system traffic prevents the system from leaving C0.
Implication: Note:
The USB device may appear unresponsive. If Cx states are enabled the device may recover a short time later. Intel has only observed this failure on a limited number of devices. Failure only occurs if software associated with a USB device programs the Nak Count Reload bits defined in the EHCI Specification for USB Rev 1.0 to 0.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum. Status: No Fix. For steppings affected, see the Summary Table of Changes.
8.
Problem:
Intel 5 Series Chipset and Intel 3400 Series Chipset SATA SYNC Escape Erratum
When SYNC Escape by a SATA device occurs on a D2H FIS, the PCH does not set the PxIS.IFS bit to 1. This deviates from section 6.1.9 of the Rev 1.3 Serial ATA Advanced Host Controller Interface (AHCI). There is no known observable impact. Instead of detecting the IFS bit, software will detect a timeout error caused by the SYNC escape and then respond. No Fix. For steppings affected, see the Summary Table of Changes.
Implication:
Workaround: None. Status:
18
Errata
9.
Problem:
Intel P55, PM55, 3400, and 3420 Chipsets May Not Fully Initialize Intel ME
Some Intel P55, PM55, 3400, and 3420 based systems with Intel ME Ignition 6.0.0.1126 PV firmware may fail to correctly initialize the Intel ME subsystem during boot at colder temperatures. Failures may occur during BIOS update. Systems fans may run continuously at full speed and the system may have increased power consumption.
Implication:
Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum. Status: Fixed. For steppings affected, see the Summary Table of Changes.
10.
Problem:
Intel 5 Series Chipset and Intel 3400 Series Chipset USB End of Frame When Retrying Packets Issue
If the PCH encounters a Full-Speed or Low-Speed USB transaction with errors, the PCH may retry the transaction without considering if the transaction can finish before the end of the current frame. The implication is dependant on the USB device. The PCH will attempt to recover per error handling specified in Section 4.5.2 of the USB Specification 2.0. The device may hang and require cycle to resume normal functionality. Intel has only observed this behavior on a limited number of USB devices. The implication only occurs if a USB device does not correctly respond to error handling as specified Section 4.5.2 of the USB Specification 2.0. No Fix. For steppings affected, see the Summary Table of Changes.
Implication:
Note:
11.
Problem:
Intel 5 / 3400 Series Chipset Family USB Classic Device Removal Issue
If two or more USB Full-Speed / Low-Speed devices are connected to the same USB controller, the devices are not suspended, and one device is removed, one or more of the devices remaining in the system may be affected by the disconnect. The implication is device dependant. A device may experience a delayed transaction, stall and be recovered via software, or stall and require a reset such as a hot plug to resume normal functionality. No Fix. For steppings affected, see the Summary Table of Changes.
Implication:
Workaround: None Status:
12.
Problem: Implication: Note:
Intel H55 Express Chipset and Intel 3420 Chipset May Report Incorrect Number of USB Ports
The Intel H55 Express Chipset and Intel 3420 Chipset support 6 ports on RMH #1 and may incorrectly report 8 USB ports in the bNbrPorts field of the RMH hub descriptor. If AC power is removed while the system is in hibernate, when the system resumes new USB devices may not be detected, and all devices on RMH #1 may not function. AC power removal while a system is in S4 is not a common occurrence.
19
Errata
13.
Intel HM55 Express Chipset May Report Incorrect Number of USB Ports
The Intel HM55 Express Chipset supports 6 ports on RMH #1 and will incorrectly report 8 USB ports in the bNbrPorts field of the RMH hub descriptor. There are no known functional implications due to this issue on production Intel HM55 chipsets. No Fix. For steppings affected, see the Summary Table of Changes.
14.
Intel 5 Series Chipset and Intel 3400 Series Chipset HPET Writing Timing Issue
A read transaction that immediately follows a write transaction to the HPET register space may return an incorrect value. Implication is dependent on the usage model as noted below: For the HPET TIMn_COMP Timer 0 Comparator Value Register and HPET MAIN_CNTMain Counter Value Register the issue could result in the software receiving stale data. This may result in undetermined system behavior. Note: Timers [1:7] are not affected by this issue. For TIMERn_VAL_SET_CNF bit 6 in the TIMn_CONFTimer n Configuration there is no known usage model for reading this bit and there are no known functional implications. A write to the High Precision Timer Configuration (HPTC) register followed by a read to HPET register space may return all 0xFFFF_FFFFh.
Workaround: A workaround is available. Status: No Fix. For steppings affected, see the Summary Table of Changes.
15.
Problem:
Intel 5 Series Chipset and Intel 3400 Series Chipset USB Full-Speed Port Staggering
When USB full-speed/low-speed port staggering is enabled, the PCH may not wait for the bus to return to an idle state after an End of Packet (EOP) and may incorrectly acknowledge bus noise as a data packet. Some full-speed/low-speed devices may fail to enumerate and function. This issue has been seen with a minimum number of devices on some motherboard ports with certain cable and trace lengths.
Implication: Note:
16.
Intel 5 Series Chipset and Intel 3400 Series Chipset USB Devices May Slow or Hang
When the processor is in C0, and a single bulk High-Speed USB device is active the port associated with the active device may hang. The implication is device driver dependant. Intel has observed some USB devices may have decreased performance, or the device may hang.
20
Errata
17.
Intel 5 Series Chipset and Intel 3400 Series Chipset USB Low Speed Control Transactions
If the USB control buffers in the PCH Rate Matching Hub(s) are saturated with pending transactions the buffers may not be serviced in round robin order. Some low-speed endpoints may not receive their pending control transactions. This issue has only been observed in synthetic test environment. The implication will be Device, driver and operating system specific. No Fix. For steppings affected, see the Summary Table of Changes.
18.
Intel 5 Series Chipset and Intel 3400 Series Chipset May Not Detect Unsolicited SATA COMINITs
Intel 5 Series Chipset and Intel 3400 Series Chipset may not detect an unsolicited COMINIT from a SATA device The SATA device may not be properly detected and configured resulting in the device Not functioning as expected.
19.
Intel 5 Series Chipset and Intel 3400 Series Chipset SATA Hot Unplug
Intel 5 Series Chipset and Intel 3400 Series Chipset may not detect the unplug of a SATA 3.0 Gb/s device on a hot-plug enabled SATA port. Unplugged SATA device may temporarily appear to be available.
20.
Problem:
Intel 5 Series Chipset and Intel 3400 Series Chipset USB Missing ACK
Following system power cycling or S3-S5 resume, if both HS and LS/FS devices are attached to the same controller, the host controller may not respond to a HS device ACK during a Get Descriptor request from the host SW to a USB HS port. USB high-speed devices may not be detected after a power cycling or S3-S5 resume. Intel has only observed this failure on a limited number of platforms. On a failing platform, the issue occurs infrequently. Full-speed and low-speed USB devices are not impacted by this issue.
Implication:
Workaround: None. Status: No Fix. For steppings affected, see the Summary Table of Changes.
21
Errata
21.
Problem:
Intel 5 Series Chipset and Intel 3400 Series Chipset Serial ATA 6Gb/s Device Detection
Intel 5 Series Chipset and Intel 3400 Series Chipset may not be able to complete SATA Out Of Band (OOB) signaling with SATA 6Gb/s devices and down-shift to SATA 3Gb/s speed. Intel 5 Series Chipset and Intel 3400 Series Chipset may not detect a SATA 6Gb/s device upon power up or resume form S3, S4 or S5 State, resulting in indeterminate system behavior. No Fix. For steppings affected, see the Summary Table of Changes.
Implication:
22.
Problem:
Intel 5 Series Chipset and Intel 3400 Series Chipset PCI Express* Link Disable Bit
Intel 5 Series Chipset and Intel 3400 Series Chipset PCI Express Ports may not exit the disable state when the Link Control Register Link Disable bit is set and PCIe Device Electrical Idle Exit is detected. Port Specific Software Directed Hot Plug or Power Management support using the Link Disable bit may cause an Intel 5 Series Chipset and Intel 3400 Series Chipset PCI Express Port to be stuck in the Link Disable state until a Host Reset with Power Cycling occurs.
Implication:
Workaround: For Intel 5 Series Chipset and Intel 3400 Series Chipset PCI Express Port Specific Software Directed Hot Plug or Power Management support, use PCI Power Management Control register D3HOT bits instead of Link Disable bit. Status: No Fix. For steppings affected, see the Summary Table of Changes.
23.
Pixel Corruption Over Integrated LVDS Interface of Intel 5 Series Chipset

Pixel corruption may be observed over integrated LVDS interface on Mobile Intel 5 Series Platforms. Display artifacts may be seen upon mode sets (resolution changes, screen rotation) and/or system boot on the platforms that use integrated LVDS. Visual artifacts observed in LVDS dual channel mode with panels supporting maximum native resolution of 1920 x1080 and higher.
Workaround: VBIOS and Intel Graphics Media Accelerator driver change has been identified and may be implemented as a workaround for this erratum. Status: No Fix. For steppings affected, see the Summary Table of Changes.
22
Errata
24.
Problem:
Intel 5 Series Chipset and Intel 3400 Series Chipset Family High-speed USB Device False Disconnect
Intel 5 Series Chipset and Intel 3400 Series Chipset may falsely detect a USB high-speed (HS) device has been disconnected. False detection is dependent upon: HS USB devices with termination impedance at the high-end or greater than USB2.0 specification. And USB ports routed with high motherboard trace impedance.
Implication: Note:
HS USB device will appear to be disconnected and no longer accessible until a device reset, such as a hot plug, to resume normal functionality. This issue has only been observed on a limited number of HS USB devices. This issue does not affect full-speed or low-speed USB devices No Fix. For steppings affected, see the Summary Table of Changes.
25.
Problem:
USB Isoch In Transfer Error Issue

If a USB Full-Speed inbound isochronous transaction with a packet length 190 bytes or greater is started near the end of a micro-frame the PCH may see more than 189 bytes in the next micro-frame. If the PCH sees more than 189 bytes for a micro-frame an error will be sent to software and the isochronous transfer will be lost. If a single data packet is lost no perceptible impact for the end user is expected. Intel has only observed the issue in a synthetic test environment where precise control of packet scheduling is available, and has not observed this failure in its compatibility validation testing. Isochronous traffic is periodic and cannot be retried thus it is considered good practice for software to schedule isochronous transactions to start at the beginning of a micro-frame. Known software solutions follow this practice. To sensitize the system to the issue additional traffic such as other isochronous transactions or retries of asynchronous transactions would be required to push the inbound isochronous transaction to the end of the micro-frame.
Implication:
Note:
Workaround: None. Status: No Plan to Fix.
26.
Problem:
USB Full-Speed / Low-Speed Device Removal Issue

If two or more USB Full-Speed / Low-Speed devices are connected to the same USB controller, the devices are not suspended, and one device is removed, one or more of the devices remaining in the system may be affected by the disconnect. The implication is device dependent. A device may experience a delayed transaction, stall and be recovered via software, or stall and require a reset such as a hot plug to resume normal functionality. No Plan to Fix.
Implication:
23
Errata
27.
Problem:
USB Babble Detected with SW Overscheduling

If software violates USB periodic scheduling rules for Full-Speed isochronous traffic by overscheduling, the RMH may not handle the error condition properly and return a completion split with more data than the length expected. If the RMH returns more data than expected, the endpoint will detect packet babble for that transaction and the packet will be dropped. Since overscheduling occurred to create the error condition, the packet would be dropped regardless of RMH behavior. If a single isochronous data packet is lost, no perceptible impact to the end user is expected. USB software overscheduling occurs when the amount of data scheduled for a microframe exceeds the maximum budget. This is an error condition that violates the USB periodic scheduling rule. This failure has only been recreated synthetically with USB software intentionally overscheduling traffic to hit the error condition. No Plan to Fix.
Implication:
Note:
Note:
28.
Problem:
USB Low-Speed/Full-Speed EOP Issue

If the EOP of the last packet in a USB Isochronous split transaction (Transaction >189 bytes) is dropped or delayed 3 ms or longer the following may occur: If there are no other pending Low-Speed or Full-speed transactions the RMH will not send SOF, or Keep-Alive. Devices connected to the RMH will interpret this condition as idle and will enter suspend. If there is other pending Low-Speed or Full-Speed transactions, the RMH will drop the isochronous transaction and resume normal operation.
Implication: If there are no other transactions pending, the RMH is unaware a device is entered suspend and may start sending a transaction without waking the device. The implication is device dependent, but a device may stall and require a reset to resume functionality. If there are other transactions present, only the initial isochronous transaction may be lost. The loss of a single isochronous transaction may not result in end user perceptible impact. Note: Intel has only observed this failure when using software that does not comply with the USB specification and violates the hardware isochronous scheduling threshold by terminating transactions that are already in progress No Plan to Fix.
29.
USB PLL Control FSM not Getting Reset on Global Reset

Intel 5 Series Chipset and Intel 3400 Series Chipset USB PLL may not lock if a Global Reset occurs early during a cold boot sequence. USB interface would not be functional an additional cold boot would be necessary to recover. No Plan to Fix.
24
Errata
30.
Asynchronous Retries Prioritized Over Periodic Transfers

The integrated USB RMH incorrectly prioritizes Full-Speed asynchronous retries over dispatchable periodic transfers. and Low-Speed
Periodic transfers may be delayed or aborted. If the asynchronous retry latency causes the periodic transfer to be aborted, the impact varies depending on the nature of periodic transfer: If a periodic interrupt transfer is aborted, the data may be recovered by the next instance of the interrupt or the data could be dropped. If a periodic isochronous transfer is aborted, the data will be dropped. A single dropped periodic transaction should not be noticeable by end user.
Note:
This issue has only been seen in a synthetic environment. The USB spec does not consider the occasional loss of periodic traffic a violation. No Plan to Fix.
31.
Problem:
Incorrect Data for LS or FS USB Periodic IN Transaction

The Periodic Frame list entry in DRAM for a USB LS or FS Periodic IN transaction may incorrectly get some of its data from a prior Periodic IN transaction which was initiated very late into the preceding Micro-frame. It is considered good practice for software to schedule Periodic Transactions at the start of a Micro-frame. However Periodic transactions may occur late into a Micro-frame due to the following cases outlined below: Asynchronous transaction starting near the end of the proceeding Micro-frame gets Asynchronously retried
Note:
Transactions getting Asynchronous retried would only occur for ill behaved USB device or USB port with a signal integrity issue Or Two Periodic transactions are scheduled by software to occur in the same Micro-frame and the first needs to push the second Periodic IN transaction to the end of the Micro-frame boundary
Implication: Note: Status:
The implication will be device, driver or operating system specific. This issue has only been observed in a synthetic test environment No Plan to Fix.
Workaround: None.
25
Errata
32.
Problem:
Intel 5 Series and 3400 Series Chipset Family Delayed Periodic Traffic Timeout Issue
If an interrupt transaction is pushed to the x+4 micro-frame boundary due to asynchronous retries, the RMH may not wait for the interrupt transaction to timeout before starting the next transaction. IF RMH TT reaches a discard boundary, a timeout may be ignored.
Implication:
If the next transaction is intended for the same device targeted by the interrupt, the successful completion of that transaction is device dependent and cannot be guaranteed. The implication may differ depending on the nature of transaction: (only impacts TT FS / LS). If the transaction is asynchronous and the device does not respond, it will eventually be retried with no impact. If the transaction is periodic and the device does not respond, the transfer may be dropped. A single dropped periodic transaction should not be noticeable by end user. NOTE: This issue has only been seen in a synthetic environment
Workaround: None. Status: No Plan to Fix.
33.
Problem:
Intel 5 Series Chipset and Intel 3400 Series Chipset Not Responding to Cx Request when USB Async Advance Door Bell is Set
The Intel 5 Series Chipset and Intel 3400 Series Chipset may prevent the Processor from returning to C0 if the USB Async Advance Doorbell gets set just prior to the Processor transition into Cx and EHCI Host controller is not able to completely process the USB Async Advance Doorbell event prior to a Cx wake event occurring. The susceptibility window for this issue to occur is very low, as the alignment of Async Advance doorbell event completion and Cx to C0 State transition event need to intersect within a 64ns or less window. System may hang. Intel has only observed this failure with a single proprietary devices GUI application.
Note:
Implication: Note:
Workaround: A workaround is available. Contact your local Intel representative for workaround information. Status: No Plan to Fix.
34.
Problem:
Intel 5 Series Chipset LAN Tx/Rx Hang during heavy bi-directional traffic when Back-to-Back
When two systems with Intel 82577 or 82578 Gigabit Network Connection and Intel 5 Series Chipset are connected back-to-back, a network hang might occur during simultaneous Transmit and Receive file transfers of heavy network traffic. A connection with any other link partner is not impacted. The Intel 82577 or 82578 Gigabit Network Connection does not respond to a ping and no traffic can be transferred between the link partner even though the link is maintained and LEDs are on.
Implication:
Workaround: A workaround exists starting in the 11.8.72.0 version of the e1k Windows* driver and starting in 1.0.2.5 of the e1000e Linux driver. Status: No Plan to Fix.
26
1. SMLink0 Speed Change
a. The text of section 5.14.2.2 is updated as shown: The PCH supports the Advanced TCO mode in which SMLink0 and SMLink1 are used in addition to the host SMBus. See Figured 5-6 for more details. In this mode, the Intel ME SMBus controllers must be enabled by soft strap in the flash descriptor. See SPI Flash Programming Guide Application Note for more detail. SMLink0 is dedicated to integrated LAN use and when an Intel PHY 82579 is connected to SMLink0, a soft strap must be set to indicate that the PHY is connected to SMLink0. The interface will be running at the frequency of 300 KHz - 400 KHz depending on different factors such as board routing or bus loading when the Fast Mode is enabled via a soft strap (See SPI Flash Programming Guide Application Note for more detail). SMLink1 is dedicated to Embedded Controller (EC) or Baseboard Management Controller (BMC) use. In the case where a BMC is connected to SMLink1, the BMC communicates with Management Engine through Intel ME SMBus connected to SMLink1. The host and TCO slave communicated with BMC through SMBus. b. SMlink0 clock timings when operating in fast mode are added Table 8-22:
Sym Parameter Min Max Unit Notes Figure
SMLink0 Clock (SML0CLK) (See note 15) fsmb t22_SML t23_SML t24_SML t25_SML Operating Frequency High time Low time Rise time Fall time 0 0.6 1.3 400 50 300 300 KHz s s ns ns 2 8-18 8-18 8-18 8-18
c. Note 13 is added to table 8-22 as When SMLink0 is configured to run in Fast Mode via a soft strap, the operating frequency is in the range of 300 KHz-400 KHz. d. Table 8-26 is updated as follows:
27
Table 8-26 SMBus and SMLink Timing

Sym t130 t130SM
LFM
Parameter Bus Free Time Between Stop and Start Condition Bus Free Time Between Stop and Start Condition Hold Time after (repeated) Start Condition. After this period, the first clock is generated. Hold Time after (repeated) Start Condition. After this period, the first clock is generated. Repeated Start Condition Setup Time Repeated Start Condition Setup Time Stop Condition Setup Time Stop Condition Setup Time Data Hold Time Data Hold Time Data Setup Time Data Setup Time Device Time Out Cumulative Clock Low Extend Time (slave device) Cumulative Clock Low Extend Time (master device)
Min 4.7 1.3
Max
Units s s
Notes
Fig 8-18
8-18
t131
4.0
8-18
t131SM
LFM
0.6 4.7 0.6 4.0 0.6 0 0 250 100 25
35 25 10
s s s s s ns ns ns ns ms ms ms
8-18 8-18
t132 t132SM
LFM
8-18 8-18
t133 t133SM
LFM
5 4 4, 5
8-18 8-18 8-18 8-18
t134 t134SM
LFM
t135 t135SM
LFM
5 1 2 3
8-18
t136 t137 t138
8-19 8-19
e. Note 5 is added to table 8-26 as Timings with the SMLFM designator apply only to SMLink0 and only when SMLink0 is operating in Fast Mode.
28
2.
VccVRM Min/Max Change

a. Table 8-9 is changed as shown:
Symbol VccVRM VccVRM Parameter Internal PLL and VRMs (1.5V for Mobile) 1.8 V Internal PLL and VRMs (1.8 V for Desktop) Min 1.455 1.746 Nom 1.5 1.8 Max 1.545 1.854 Unit V V Notes 1, 3 1, 3
b. Note 3 is added to table 8-9 as Includes only DC tolerance. AC tolerance will be 2% in addition to this range.
3.
Determinate and Defined Signals Update

a.GPIO24 and GPIO29 are determinate and defined prior to RSMRST# deassertion. They are included with the other suspend well signals in section 3.2.
4.
AFTERG3 bit name change

Change the AFTERG3 bit name to AFTERG3_EN to make it more consistent with the bit function. a. Table 5-22 is replaced as follows:
State/ Substates G0/S0/C0 Legacy Name / Description Full On: Processor operating. Individual devices may be shut down or be placed into lower power states to save power. Cx State: Cx states are processor power states within the S0 system state that provide for various levels of power savings. The processor initiates C-state entry and exit while interacting with the PCH. The PCH will base its behavior on the processor state. S1: The PCH provides the S1 messages and the S0 messages on a wake event. It is preferred for systems to use C-states than S1. Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is shut off to non-critical circuits. Memory is retained and refreshes continue. All external clocks stop except RTC. Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume. Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking. Mechanical OFF (MOFF): System context not maintained. All power is shut off except for the RTC. No Wake events are possible. This state occurs if the user removes the main system batteries in a mobile system, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the waking logic. When system power returns, transition will depend on the state just prior to the entry to G3 and the AFTERG3_EN bit in the GEN_PMCON3 register (D31:F0, offset A4). Refer to Table 5-29 for more details.
G0/S0/Cx
G1/S1 G1/S3 G1/S4 G2/S5
G3
29
1. Host WOL Behavior Clarification
The following note add to Section 5.3.4.1.1 and 5.3.4.1.2 5.3.4.1.1 Advanced Power Management Wake Up
Note: APM wake up settings will be restored to NVM default by the PCH when LAN connected Device (PHY) power is turned off and subsequently restored. Some example host WOL flows are: When system transitions to G3 after WOL is disabled from the BIOS, APM host WOL would get enabled. Anytime power to the LAN Connected Device (PHY) is cycled while in S4/S5 after WOL is disabled from the BIOS, APM host WOL would get enabled. Anytime power to the LAN Connected Device (PHY) is cycled while in S3, APM host WOL configuration is lost.
5.3.4.1.2 ACPI Power Management Wake Up

Note: ACPI wake up settings are not preserved when the LAN Connected Device (PHY) power is turned off and subsequently restored. Some example host WOL flows are: Anytime power to the LAN Connected Device (PHY) is cycled while in S3 or S4, ACPI host WOL configuration is lost.
2.
DisplayPort Clarification
The following note add to Section 5.27.2.8 5.27.2.8 Display Port
Note: DisplayPort includes support for Dual-Mode operation, refer to the Platform Design Guide for more details on Dual-mode implementation.
3.
PIRQ Sharing
A note is added to table 2-7 as PIRQ Interrupts can only be shared if it is configured as level sensitive. They cannot be shared if configured as edge triggered.
4.
t205 Vcc Reference

Table 8-35 is changed as shown below:
Sym t205 Parameter Vcc active to PWROK high Min 10 Max Units ms Notes 5 Fig 8-2, 8-3
30
5.
Table 2-27 Power and Ground Signals

Name DcpSusByp Description Decoupling: 1.05 V Suspend well supply that is supplied internally by Internal VRs. This signal requires decoupling.
6.
EHCI Function Numbers

The following note is added to table 9-1 and section 16.1: Prior to BIOS initialization of the PCH USB subsystem, the EHCI controllers will appear as Function 7. After BIOS initialization, the EHCI controllers will be Function 0.
7.
PCI Express* Root Port Function Numbers

a. The following note is added to table 9-1: This table shows the default PCI Express Function Number-to-Root Port mapping. Function numbers for a given root port are assignable through the Root Port Function Number and Hide for PCI Express Root Ports register (RCBA+0404h). b. The following note is added to the first paragraph of section 5.2 and section 19.1: This section assumes the default PCI Express Function Number-to-Root Port mapping is used. Function numbers for a given root port are assignable through the Root Port Function Number and Hide for PCI Express Root Ports registers (RCBA+0404h).
8.
t212 Measurement Clarification

The following note is added to table 8-35: 18. LAN_RST# high to SPI Soft-Start Read is an internal PCH timing. The timing cannot be measured externally and included here for general power sequencing reference.
9.
Wake Event Causes Update

The following replaces table 5-27:
Table 5-27 Causes of Wake Events (Sheet 1 of 2)

Wake from S1, Sx Wake from S1, Sx After Power Loss (Note 1)
Y Y Y
Cause
How Enabled
Wake from Reset Types (Note 2)
RTC Alarm Power Button
Set RTC_EN bit in PM1_EN register. Always enabled as Wake event. GPE0_EN register Note: GPIs that are in the core well are not capable of waking the system from sleep states when the core well is not powered. Set GP27_EN in GPE0_EN Register. Will use PME#. Wake enable set with LAN logic.
Y Y
GPI[15:0]
GPIO27 LAN
Y Y
Y Y
31
Table 5-27 Causes of Wake Events (Sheet 2 of 2)

Wake from S1, Sx Wake from S1, Sx After Power Loss (Note 1)
Y
Cause
How Enabled
Wake from Reset Types (Note 2)
RI#
Set RI_EN bit in GPE0_EN register.
Event sets PME_B0_STS bit; PM_B0_EN must be enabled. Intel High Can not wake from S5 state if it Definition Audio was entered due to power failure or power button override. Primary PME# Secondary PME# PME_B0_EN bit in GPE0_EN register. Set PME_EN bit in GPE0_EN register.
Y Y Y S1
Y Y Y S1
PCI_EXP_WAKE PCI_EXP_WAKE bit. (Note 3) # SATA Set PME_EN bit in GPE0_EN register. (Note 4) Must use the PCI Express* WAKE# pin rather than messages for wake from S3, S4, or S5. Always enabled as Wake event. Wake/SMI# command always enabled as a Wake event. Note: SMBus Slave Message can wake the system from S1S5, as well as from S5 due to Power Button Override. HOST_NOTIFY_WKEN bit SMBus Slave Command register. Reported in the SMB_WAK_STS bit in the GPEO_STS register. Always enabled as a wake event.
PCI_EXP PME Message SMBALERT#
S1
S1
SMBus Slave Wake Message (01h)
SMBus Host Notify message received Intel ME Non-Maskable Wake
Integrated WOL WOL Enable Override bit (in Enable Override Configuration Space).
NOTES:
1. 2. 3. 4. This column represents what the PCH would honor as wake events but there may be enabling dependencies on the device side which are not enabled after a power loss. Reset Types include: Power Button override, Intel ME initiated power button override, Intel ME initiated host partition reset with power down, Intel ME Watchdog Timer, SMBus unconditional power down, Processor thermal trip, PCH catastrophic temperature event. When the WAKE# pin is active and the PCI Express device is enabled to wake the system, the PCH will wake the platform. SATA can only trigger a wake event in S1, but if PME is asserted prior to S3/S4/S5 entry and software does not clear the PME_B0_STS, a wake event would still result.
32
10.
SGPIO Reference Clock Speed

SCLOCK Description in table 2-5 is updated as follows:
Name Type Description SGPIO Reference Clock: The SATA controller uses rising edges of this clock to transmit serial data, and the target uses the falling edge of this clock to latch data. The SCLOCK frequency supported is 32 kHz. If SGPIO interface is not used, this signal can be used as GPIO22.
SCLOCK/GPIO2 2
OD O
11.
I2C Block Read/Write Buffer

In section 5.20.1.1, the following note is added after the Block Read/Write description as shown: The PCH contains a 32-byte buffer for read and write data which can be enabled by setting bit 1 of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a single byte of buffering. This 32-byte buffer is filled with write data before transmission, and filled with read data on reception. In the PCH, the interrupt is generated only after a transmission or reception of 32 bytes, or when the entire byte count has been transmitted/received. When operating in I2C mode (I2C_EN bit is set), the PCH will never use the 32-byte buffer for any block commands.
12.
Register and Bit Definition Clarifications

a. Bit and register attributes of the type R/WL are defined as follows. This is added to the beginning of chapter 9: R/WL} Read/Write Lockable. A register bit with the attribute can be read at any time but writes may only occur if the associated lock bit is set to unlock. If the associated lock bit is set to lock, this register bit becomes RO unless otherwise indicated. b. The definition for Default in the beginning of chapter 9 is changed to: Default}When the PCH is reset, it sets its registers to predetermined default states. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software to determine configuration, operating parameters, and optional system features that are applicable, and to program the PCH registers accordingly. (Review note: the strikethrough text will only appear in the draft of the Spec Update for review purposes.)
13.
GPIO13 Voltage Tolerance

GPIO13 is powered by VccSusHDA well and therefore, the voltage tolerance value varies according to the voltage connected to VccSusHDA. The following clarifications are made: a. Table 2-24, GPIO13 Tolerance is change from 3.3 V to 3.3 V or 1.5 V and the following note is added to table 2-4: GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Voltage tolerance on the signal is the same as VccSusHDA. b. The following note is added to GPIO13 in table 3-2 as note 14: GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Pin tolerance is determined by VccSusHDA voltage.
33
14.
Intel HD Audio Register Accesses

The first note in section 17.1 Intel High Definition Audio Controller Registers (D27:F0) is changed as shown: All registers in this function (including memory-mapped registers) must be addressable in byte, word, and DWord quantities. The software must always make register accesses on natural boundaries (that is, DWord accesses must be on DWord boundaries; word accesses on word boundaries, etc.) Register access crossing the DWord boundary are ignored. In addition, the memory-mapped register space must not be accessed with the LOCK semantic exclusive-access mechanism. If software attempts exclusive-access mechanisms to the Intel High Definition Audio memory-mapped space, the results are undefined.
15.
SLP_LAN# Pin Behavior

a. The signal description for SLP_LAN# in table 2-9 is updated as shown:
Name Type Description LAN Sub-System Sleep Control: When SLP_LAN# is deasserted it indicates that the PHY device must be powered. When SLP_LAN# is asserted, power can be shut off to the PHY device. SLP_LAN# will always be deasserted in S0 and anytime SLP_A# is deasserted. O A SLP_LAN#/GPIO Select Soft-Strap can be used for systems NOT using SLP_LAN# functionality to revert to GPIO29 usage. When soft-strap is 0 (default), pin function will be SLP_LAN#. When soft-strap is set to 1, the pin returns to its regular GPIO mode. The pin behavior is summarized in Section 5.13.10.5.
SLP_LAN# / GPIO29
b. The following section is added as section 5.13.10.4: 5.13.10.5 SLP_LAN# Pin Behavior The following table summarizes SLP_LAN# pin behavior. Table. SLP_LAN# Pin Behavior
Pin Functionality (Determined by soft strap) SLP_LAN Default Value Bit GPIO29 Input / Output (Determined by GP_IO_SEL bit) In (Default) 0 (Default) SLP_LAN# 1 Out In (Default) Out In In Out Pin Value In S0 or M3 1 1 1 1 Z (tri-state) Z (tri-state) Depends on GPIO29 output data value Value in S3-S5/Moff 0 Depends on GPIO29 output data value 1 Depends on GPIO29 output data value 0 1 Depends on GPIO29 output data value
0 (Default) 1 GPIO29 N/A
34
16.
HDA_DOCK_RST#/GPIO13 Description Clarification

The signal description for HDA_DOCK_RST#/GPIO13 is updated as shown:
Name Type Description Intel High Definition Audio Dock Reset: This signal is a dedicated HDA_RST# signal for the codec(s) in the docking station. Aside from operating independently from the normal HDA_RST# signal, it otherwise works similarly to the HDA_RST# signal. This signal is shared with GPIO13. This signal defaults to GPIO13 mode after PLTRST#. BIOS is responsible for configuring GPIO13 to HDA_DOCK_RST# mode.
HDA_DOCK_RST# / GPIO13
35
Documentation Changes
1. Correct Table 5-58 PCH supported Audio formats over HDMI and DisplayPort*
The following changes applies to Table 5-58 Table 5-58 PCH supported Audio formats over HDMI and DisplayPort*
Audio Formats AC-3 - Dolby Digital Dolby* Digital Plus DTS-HD* LPCM, 192 KHz/24 bit, 8 Channel Dolby True HD, DTS HD Master Audio (Losses Blu-Ray Audio Format) HDMI Yes Yes Yes Yes Yes No No No Yes (two channel - upto 96 KHz 24 bit) No DisplayPort
2.
Correct Table 8-8 DC Output Characteristics and NOTES 1.

The following changes applies to Table 8-8
Symbol VOL3 VOH3 NOTES: 1. The SERR#, PIRQ[H:A], SMBDATA, SMBCLK, SML[1:0]CLK, SML[1:0]DATA, SML[1:0] ALERT# and PWM[3:0] signal has an open-drain driver and SATALED# has an open-collector driver, and the VOH / IOH specification does not apply. This signal must have external pull up resistor. Parameter Output Low Voltage Output High Voltage Min 0 3.3 V - 0.5 Max 0.4 Unit V V IOL / IOH 4 mA -2 mA Note 1, 7 Notes
3.
Correct 21.1.2 HSFS-Hardware Sequencing Flash Status Register (SPI Memory Mapped Configuration Registers)
Bit Description Flash Descriptor Override Pin Strap Status (FDOPSS) RO. This bit reflects the value the Flash Descriptor Override Pin-Strap. 13 0 = The Flash Descriptor Override strap is set 1 = No override
36
4.
Correct 21.4.2 HSFSHardware Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers)
Bit Description Flash Descriptor Override Pin Strap Status (FDOPSS) RO. This bit reflects the value the Flash Descriptor Override Pin-Strap. 13 0 = The Flash Descriptor Override strap is set 1 = No override
5.
Correct 13.1.23 GEN1_DECLPC I/F Generic Decode Range 1 Register (LPC I/FD31:F0)
Bit 15:2 Description Generic I/O Decode Range 1 Base Address (GEN1_BASE)R/W. NOTE: The PCH Does not provide decode down to the word or byte level
6.
Correct Table 2-28 Functional Strap Definitions

Signal Usage When Sampled Rising edge of MEPWROK Comment This signal has a weak internal pull-down resistor. This signal must be sampled low.
SPI_MOSI
Reserved
7.
Correct Table 9-4 Memory Decode Ranges from Processor Perspective

Memory Range FED4 0000hFED4 BFFFh Target TPM on LPC Dependency/Comments
8.
Correct 10.1.43 OICOther Interrupt Control Register

Bit 11 Description Reserved
9.
Miscellaneous Typographical and Omission Error Corrections

a. Section 10.1.67 MISCCTLMiscellaneous Control Register RCBA+3590h is replaced as follows:
Bit 31:2 Reserved. EHCI 2 USBR Enable R/W. When set, this bit enables support for the USB-r redirect device on the EHCI controller in Device 26. SW must complete programming the following registers before this bit is set: 1. Enable RMH 2. HCSPARAMS (N_CC, N_Ports) Description
37
Bit
Description EHCI 1 USBR Enable R/W. When set, this bit enables support for the USB-r redirect device on the EHCI controller in Device 29. SW must complete programming the following registers before this bit is set: 1. Enable RMH 2. HCSPARAMS (N_CC, N_Ports)
b. The SATA RAID controller Device IDs when the AIE bit is set are corrected in 14.1.33 as shown below. The Device IDs with the AIE bit cleared are also added to the Device and Revision ID table in section 2.28.
Bit Description Alternate ID Enable (AIE) R/WO. 0 = When in RAID mode the SATA Controller located at Device 31: Function 2 will report the following Device ID 2822h for Desktop or 282Ah for Mobile and the Microsoft Windows Vista* in-box version of the Intel Rapid Storage Manager will load on the platform. 1 = When in RAID mode the SATA Controller located at Device 31: Function 2 will report the following Device ID 3B25h for Desktop or 3B2Ch for Mobile to prevent the Microsoft Windows Vista in-box version of the Intel Rapid Storage Manager from loading on the platform and will require the user to perform an F6 installation of the appropriate Intel Rapid Storage Manager. NOTE: This field is applicable when the AHCI is configured for RAID mode of operation. It has no impact for AHCI and IDE modes of operation. BIOS is recommended to program this bit prior to programming the MAP.SMS field to reflect RAID. This field is reset by PLTRST#. BIOS is required to reprogram the value of this bit after resuming from S3, S4 and S5.
7 (RAID Capable SKUs Only)
c. Section 10.1.69 (USBOCM2 - Overcurrent MAP Register 2) is updated as follows:

Bit 31:30 Reserved OC7 Mapping Each bit position maps OC7# to a set of ports as follows: The OC7# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given ports bit map is set only for one OC pin. Bit Port 23:22 Reserved OC6 Mapping Each bit position maps OC6# to a set of ports as follows: The OC6# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given ports bit map is set only for one OC pin. Bit Port 15:14 Reserved 21 13 20 12 19 11 18 10 17 9 16 8 29 13 28 12 27 11 26 10 25 9 24 8 Description
29:24
21:16
38
Bit
Description OC5 Mapping Each bit position maps OC5# to a set of ports as follows: The OC5# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given ports bit map is set only for one OC pin. Bit Port 13 13 12 12 11 11 10 10 9 9 8 8
13:8
7:6
Reserved OC4 Mapping Each bit position maps OC4# to a set of ports as follows: The OC4# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given ports bit map is set only for one OC pin. Bit Port 5 13 4 12 3 11 2 10 1 9 0 8
5:0
d. D31:F1 references are changed to D31:F2 or D31:F5, where appropriate, throughout the document.
10.
Update Table 2-8 USB Interface Signals

Name OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 I Type Description Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred. These signals can instead be used as GPIOs. NOTES: 1. OC# pins are not 5 V tolerant. 2. Depending on platform configuration, sharing of OC# pins may be required. 3. OC#[3:0] can only be used for EHCI controller #1 4. OC#[4:7] can only be used for EHCI controller #2
11.
Update Note 2 of Table 9-1 PCI Devices and Functions

It is updated to SATA controller 2 (D31:F5) is only visible when D31:F2 CC.SCC=01h.
39
12.
Correct 14.2.1 BMIC[P,S]Bus Master IDE Command Register (D31:F2)

Bit Description Start/Stop Bus Master (START) R/W.
0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped and then resumed. If this bit is reset while bus master operation is still active (i.e., the Bus Master IDE Active bit (D31:F2:BAR + 02h, bit 0) of the Bus Master IDE Status register for that IDE channel is set) and the drive has not yet finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for that IDE channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = Enables bus master operation of the controller. Bus master operation does not actually start unless the Bus Master Enable bit (D31:F2:04h, bit 2) in PCI configuration space is also set. Bus master operation begins when this bit is detected changing from 0 to 1. The controller will transfer data between the IDE device and memory only when this bit is set. Master operation can be halted by writing a 0 to this bit. Note: This bit is intended to be cleared by software after the data transfer is completed, as indicated by either the Bus Master IDE Active bit being cleared or the Interrupt bit of the Bus Master IDE Status register for that IDE channel being set, or both. Hardware does not clear this bit automatically. If this bit is cleared to 0 prior to the DMA data transfer being initiated by the drive in a device to memory data transfer, then the PCH will not send DMAT to terminate the data transfer. SW intervention (such as, sending SRST) is required to reset the interface in this condition.
13.
Correct 15.2.1 BMIC[P,S]Bus Master IDE Command Register (D31:F5)

Bit Description Start/Stop Bus Master (START) R/W.
0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped and then resumed. If this bit is reset while bus master operation is still active (i.e., the Bus Master IDE Active bit (D31:F5:BAR + 02h, bit 0) of the Bus Master IDE Status register for that IDE channel is set) and the drive has not yet finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for that IDE channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = Enables bus master operation of the controller. Bus master operation does not actually start unless the Bus Master Enable bit (D31:F5:04h, bit 2) in PCI configuration space is also set. Bus master operation begins when this bit is detected changing from 0 to 1. The controller will transfer data between the IDE device and memory only when this bit is set. Master operation can be halted by writing a 0 to this bit. Note: This bit is intended to be cleared by software after the data transfer is completed, as indicated by either the Bus Master IDE Active bit being cleared or the Interrupt bit of the Bus Master IDE Status register for that IDE channel being set, or both. Hardware does not clear this bit automatically. If this bit is cleared to 0 prior to the DMA data transfer being initiated by the drive in a device to memory data transfer, then the PCH will not send DMAT to terminate the data transfer. SW intervention (such as, sending SRST) is required to reset the interface in this condition.
14.
Update Table 4-1 PCH System Clock Inputs

Clock Domain CLKIN_BCLK_P, CLKIN_BCLK_N Frequency 133 MHz Usage 133 MHz differential reference clock from a clock chip in Buffer-Through Mode.
40
15.
Update Table 2-20 Clock Interface Signals

Name CLKIN_BCLK_P, CLKIN_BCLK_N Type I Description 133 MHz differential reference clock from a clock chip in Buffer-Through Mode.
16.
Display Interface Updates

a. In section 1.2, Embedded DisplayPort is added to the list supported Analog and Digital Display ports. b. The following two paragraphs are added to section 1.2.1:
PCH Display Interface

PCH integrates latest display technologies such as HDMI*, DisplayPort*, Embedded DisplayPort (eDP*), SDVO, and DVI along with legacy display technologies: Analog Port (VGA) and LVDS (mobile only). The Analog Port and LVDS Port are dedicated ports on the PCH and the Digital Ports B, C and D can be configured to drive HDMI, DVI, or DisplayPort. Digital Port B can also be configured as SDVO while Digital Port D can be configured as eDP. The HDMI interface supports the HDMI* 1.3C specification while the DisplayPort interface supports the DisplayPort* 1.1a specification. PCH supports High-bandwidth Digital Content Protection for high definition content playback over digital interfaces. PCH also integrates audio codecs for audio support over HDMI and DisplayPort interfaces. PCH receives the display data over the Intel FDI and transcodes the data as per the display technology protocol and sends the data through the display interface.
Intel Flexible Display Interconnect (FDI)

Intel FDI connects the display engine in the processor with the display interfaces on the PCH. The display data from the frame buffer is processed by the display engine and sent to the PCH where it is transcoded and driven out on the panel. Intel FDI involves two channels A and B for display data transfer. Intel FDI supports maximum data rate of 2.7Gb/s per lane. c. The following replaces section 5.27:
5.27 PCH Display Interfaces

The PCH integrates one Analog, LVDS (mobile only) and three Digital Ports B, C, and D. Each Digital Port can transmit data according to one or more protocols. Digital Port B, C and D can be configured to drive natively HDMI, DisplayPort or DVI. Digital Port B also supports Serial Digital Video Out (SDVO) that converts one protocol to another. Digital Port D can be configured to drive natively Embedded DisplayPort (eDP). Each display port has control signals that may be used to control, configure and/or determine the capabilities of an external device. The PCHs Analog Port uses an integrated 340.4 MHz RAMDAC that can directly drive a standard progressive scan analog monitor up to a resolution of 2048x1536 pixels with 32-bit color at 75 Hz. The PCH SDVO port (configured through Digital Port B) is capable of driving a 200 MP/s (Megapixels/second) rate. Each Digital Port is capable of driving a digital display up to 2560x1600 at 60 Hz using DisplayPort and 1920x1200 at 60 Hz using HDMI, DVI (with reduced blanking).
41
5.27.1 Analog Display Interface Characteristics

The Analog Port provides a RGB signal output along with a HSYNC and VSYNC signal. There is an associated Display Data Channel (DDC) signal pair that is implemented using GPIO pins dedicated to the Analog Port. The intended target device is for a monitor with a VGA connector. Display devices such as LCD panels with analog inputs may work satisfactory but no functionality added to the signals to enhance that capability. Figure 5-14. Analog Port Characteristics
5.27.1.1 Integrated RAMDAC

The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that transforms the digital data from the graphics and video subsystems to analog data for the VGA monitor. The PCHs integrated 340.4 MHz RAMDAC supports resolutions up to 2048x1536 at 75 Hz. Three 8-bit DACs provide the R, G, and B signals to the monitor. 5.27.1.1.1 Sync Signals HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector. Since these levels cannot be generated internal to the device, external level shifting buffers are required. These signals can be polarity adjusted and individually disabled in one of the two possible states. The sync signals should power up disabled in the high state. No composite sync or special flat panel sync support are included. 5.27.1.1.2 VESA/VGA Mode VESA/VGA mode provides compatibility for pre-existing software that set the display mode using the VGA CRTC registers. Timings are generated based on the VGA register values and the timing generator registers are not used.
5.27.1.2 DDC (Display Data Channel)

DDC is a standard defined by VESA. Its purpose is to allow communication between the host system and display. Both configuration and control information can be exchanged allowing plug- and-play systems to be realized. Support for DDC 1 and 2 is implemented. The PCH uses the DDC_CLK and DDC_DATA signals to communicate with the analog monitor. The PCH will generate these signals at 2.5 V. External pull-up resistors and level shifting circuitry should be implemented on the board.
42
5.27.2 Digital Display Interfaces

The PCH can drive a number of digital interfaces natively. The Digital Ports B, C, and/or D can be configured to drive HDMI, DVI, DisplayPort, and Embedded DisplayPort (port D only). The PCH provides a dedicated port for Digital Port LVDS (mobile only).
5.27.2.1 LVDS (Mobile only)

LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an electrical standard only defining driver output characteristics and receiver input characteristics. Each channel supports transmit clock frequency ranges from 25 MHz to 112 MHz, which provides a throughput of up to 784 Mbps on each data output and up to 112 MP/s on the input. When using both channels, each carry a portion of the data; thus, doubling the throughput to a maximum theoretical pixel rate of 224 MP/s. There are two LVDS transmitter channels (Channel A and Channel B) in the LVDS interface. Channel A and Channel B consist of 4-data pairs and a clock pair each. The LVDS data pair is used to transfer pixel data as well as the LCD timing control signals. Figure 5-15 shows a pair of LVDS signals and swing voltage. Figure 5-15. LVDS Signals and Swing Voltage
Logic values of 1s and 0s are represented by the differential voltage between the pair of signals. As shown in the Figure 5-16 a serial pattern of 1100011 represents one cycle of the clock. Figure 5-16. LVDS Clock and Data Relationship
5.27.2.2 LVDS Pair States The LVDS pairs can be put into one of five states:
43
Active Powered down Hi-Z Powered down 0 V Common mode Send zeros When in the active state, several data formats are supported. When in powered down state, the circuit enters a low power state and drives out 0 V or the buffer is the Hi-Z state on both the output pins for the entire channel. The common mode Hi-Z state is both pins of the pair set to the common mode voltage. When in the send zeros state, the circuit is powered up but sends only zero for the pixel color data regardless what the actual data is with the clock lines and timing signals sending the normal clock and timing data. The LVDS Port can be enabled/disabled using software. A disabled port enters a low power state. Once the port is enabled, individual driver pairs may be disabled based on the operating mode. Disabled drivers can be powered down for reduced power consumption or optionally fixed to forced 0s output. Individual pairs or sets of LVDS pairs can be selectively powered down when not being used. The panel power sequencing can be set to override the selected power state of the drivers during power sequencing. 5.27.2.3 Single Channel versus Dual Channel Mode In the single channel mode, only Channel-A is used. Channel-B cannot be used for single channel mode. In the dual channel mode, both Channel-A and Channel-B pins are used concurrently to drive one LVDS display. In Single Channel mode, Channel A can take 18 bits of RGB pixel data, plus 3 bits of timing control (HSYNC/VSYNC/DE) and output them on three differential data pair outputs; or 24 bits of RGB (plus 4 bits of timing control) output on four differential data pair outputs. A dual channel interface converts 36 or 48 bits of color information plus the 3 or 4 bits of timing control respectively and outputs it on six or eight sets of differential data outputs respectively. Dual Channel mode uses twice the number of LVDS pairs and transfers the pixel data at twice the rate of the single channel. In general, one channel will be used for even pixels and the other for odd pixel data. The first pixel of the line is determined by the display enable going active and that pixel will be sent out Channel-A. All horizontal timings for active, sync, and blank will be limited to be on two pixel boundaries in the two channel modes. Note: Platforms using the PCH for integrated graphics support 24-bpp display panels of Type 1 only (compatible with VESA LVDS color mapping). 5.27.2.4 Panel Power Sequencing This section provides details for the power sequence timing relationship of the panel power, the backlight enable and the LVDS data timing delivery. To meet the panel power timing specification requirements two signals, LFP_VDD_EN and LFP_BKLT_EN, are provided to control the timing sequencing function of the panel and the backlight power supplies. A defined power sequence is recommended when enabling the panel or disabling the panel. The set of timing parameters can vary from panel to panel vendor, provided that they stay within a predefined range of values. The panel VDD power, the backlight on/off state and the LVDS clock and data lines are all managed by an internal power sequencer.
44
Figure 5-17. Panel Power Sequencing
T4
T1+T2
T5 Panel On
TX
T3
T4
Panel VDD Enable Panel BackLight Enable

Off Off
Clock/Data Lines
Valid
Power On Sequence from off state and Power Off Sequence after full On
NOTE: Support for programming parameters TX and T1 through T5 using software is provided.
5.27.2.5 LVDS DDC The display pipe selected by the LVDS display port is programmed with the panel timing parameters that are determined by installed panel specifications or read from an onboard EDID ROM. The programmed timing values are then locked into the registers to prevent unwanted corruption of the values. From that point on, the display modes are changed by selecting a different source size for that pipe, programming the VGA registers, or selecting a source size and enabling the VGA. The LVDS DDC helps to reads the panel timing parameters or panel EDID.
5.27.2.6 High-Definition Multimedia Interface

The High-Definition Multimedia Interface (HDMI) is provided for transmitting uncompressed digital audio and video signals from DVD players, set-top boxes and other audiovisual sources to television sets, projectors and other video displays. It can carry high quality multi-channel audio data and all standard and high-definition consumer electronics video formats. HDMI display interface connecting the PCH and display devices utilizes transition minimized differential signaling (TMDS) to carry audiovisual information through the same HDMI cable. HDMI includes three separate communications channels: TMDS, DDC, and the optional CEC (consumer electronics control) (not supported by the PCH). As shown in Figure 5-18, the HDMI cable carries four differential pairs that make up the TMDS data and clock channels. These channels are used to carry video, audio, and auxiliary data. In addition, HDMI carries a VESA DDC. The DDC is used by an HDMI Source to determine the capabilities and characteristics of the Sink. Audio, video and auxiliary (control/status) data is transmitted across the three TMDS data channels. The video pixel clock is transmitted on the TMDS clock channel and is used by the receiver for data recovery on the three data channels. The digital display data signals driven natively through the PCH are AC coupled and needs level shifting to convert the AC coupled signals to the HDMI compliant digital signals. PCH HDMI interface is designed as per High-Definition Multimedia Interface Specifica-
45
tion 1.4a. The PCH supports High-Definition Multimedia Interface Compliance Test Specification 1.4a. Figure 5-18. HDMI Overview
5.27.2.7 Digital Video Interface (DVI)

The PCH Digital Ports can be configured to drive DVI-D. DVI uses TMDS for transmitting data from the transmitter to the receiver which is similar to the HDMI protocol but the audio and CEC. Refer to the HDMI section for more information on the signals and data transmission. To drive DVI-I through the back panel the VGA DDC signals is connected along with the digital data and clock signals from one of the Digital Ports. When a system has support for a DVI-I port, then either VGA or the DVI-D through a single DVI-I connector can be driven but not both simultaneously. The digital display data signals driven natively through the PCH are AC coupled and needs level shifting to convert the AC coupled signals to the HDMI compliant digital signals.
46
5.27.2.8 DisplayPort*
DisplayPort is a digital communication interface that utilizes differential signaling to achieve a high bandwidth bus interface designed to support connections between PCs and monitors, projectors, and TV displays. DisplayPort is also suitable for display connections between consumer electronics devices such as high definition optical disc players, set top boxes, and TV displays. A DisplayPort consists of a Main Link, Auxiliary channel, and a Hot Plug Detect signal. The Main Link is a uni-directional, high-bandwidth, and low latency channel used for transport of isochronous data streams such as uncompressed video and audio. The Auxiliary Channel (AUX CH) is a half-duplex bidirectional channel used for link management and device control. The Hot Plug Detect (HPD) signal serves as an interrupt request for the sink device. PCH is designed as per VESA DisplayPort Standard Version 1.1a. The PCH supports VESA DisplayPort* PHY Compliance Test Specification 1.1 and VESA DisplayPort* Link Layer Compliance Test Specification 1.1. Figure 5-19. DisplayPort Overview
5.27.2.9 Embedded DisplayPort

Embedded DisplayPort (eDP*) is an embedded version of the DisplayPort standard oriented towards applications such as notebook and All-In-One PCs. eDP is supported only on Digital Port D. Like DisplayPort, Embedded DisplayPort also consists of a Main Link, Auxiliary channel, and a optional Hot Plug Detect signal. The eDP support on desktop PCH is possible because of the addition of the panel power sequencing pins: L_VDD, L_BKLT_EN and L_BLKT_CTRL. The eDP on the PCH can be configured for 2 or 4 lanes. PCH supports Embedded DisplayPort* (eDP*) Standard Version 1.1.
5.27.2.10 DisplayPort Aux Channel

A bi-directional AC coupled AUX channel interface replaces the I2C for EDID read, link management and device control. I2C-to-Aux bridges are required to connect legacy display devices.
47
5.27.2.11 DisplayPort Hot-Plug Detect (HPD)

The PCH supports HPD for Hot-Plug sink events on the HDMI and DisplayPort interface.
5.27.2.12 Integrated Audio over HDMI and DisplayPort

DisplayPort and HDMI interfaces on PCH support audio. The below table shows the supported audio technologies on the PCH. Table 5-58. PCH supported Audio formats over HDMI and DisplayPort*
Audio Formats AC-3 - Dolby* Digital Dolby Digital Plus DTS-HD* LPCM, 192 kHz/24 bit, 8 Channel Dolby TrueHD, DTS-HD Master Audio* (Losses Blu-ray Disc* Audio Format) HDMI Yes Yes Yes Yes Yes No No No Yes (two channel - up to 96 kHz 24 bit) No DisplayPort
PCH adds support for Silent stream. Silent stream is a integrated audio feature that enables short audio streams such as system events to be heard over the HDMI and DisplayPort monitors. PCH supports silent streams over the HDMI and DisplayPort interfaces at 48 kHz, 96 kHz, and 192 kHz sampling rates.
5.27.2.13 Serial Digital Video Out (SDVO)

Serial Digital Video Out (SDVO) supports SDVO-LVDS only on the PCH. Though the SDVO electrical interface is based on the PCI Express interface, the protocol and timings are completely unique. The PCH utilizes an external SDVO device to translate from SDVO protocol and timings to the desired display format and timings. SDVO is supported only on Digital Port B of the PCH.
48
Figure 5-20. SDVO Conceptual Block Diagram
TV Clock in Stall Interrupt Control Clock 3rd Party SDVO External Device
SDVO B
PCH
Control Data RED B GREEN B BLUE B
LVDS Panel
5.27.2.14 Control Bus Communication to SDVO registers and if utilized, ADD2 PROMs and monitor DDCs, are accomplished by using the SDVOCTRLDATA and SDVOCTRLCLK signals through the SDVO device. These signals run up to 400 kHz and connect directly to the SDVO device. The SDVO device is then responsible for routing the DDC and PROM data streams to the appropriate location. Consult SDVO device data sheets for level shifting requirements of these signals.
49
5.27.3 Mapping of Digital Display Interface Signals

Table 5-59. PCH Digital Port Pin Mapping
Port Description DisplayPort* Signals DPB_LANE3 DPB_LANE3# DPB_LANE2 DPB_LANE2# DPB_LANE1 Port B DPB_LANE1# DPB_LANE0 DPB_LANE0# DPB_HPD DPB_AUX DPB_AUXB DPC_LANE3 DPC_LANE3# DPC_LANE2 DPC_LANE2# DPC_LANE1 Port C DPC_LANE1# DPC_LANE0 DPC_LANE0# DPC_HPD DPC_AUX DPC_AUXC DPD_LANE3 DPD_LANE3# DPD_LANE2 DPD_LANE2# DPD_LANE1 Port D DPD_LANE1# DPD_LANE0 DPD_LANE0# DPD_HPD DPD_AUX DPD_AUXD TMDSD_CLK TMDSD_CLKB TMDSD_DATA0 TMDSD_DATA0B TMDSD_DATA1 TMDSD_DATA1B TMDSD_DATA2 TMDSD_DATA2B TMDSD_HPD TMDSC_CLK TMDSC_CLKB TMDSC_DATA0 TMDSC_DATA0B TMDSC_DATA1 TMDSC_DATA1B TMDSC_DATA2 TMDSC_DATA2B TMDSC_HPD HDMI* Signals TMDSB_CLK TMDSB_CLKB TMDSB_DATA0 TMDSB_DATA0B TMDSB_DATA1 TMDSB_DATA1B TMDSB_DATA2 TMDSB_DATA2B TMDSB_HPD SDVO Signals SDVOB_CLK SDVOB_CLK# SDVOB_BLUE SDVOB_BLUE# SDVOB_GREEN SDVOB_GREEN# SDVOB_RED SDVOB_RED* PCH Display Port Pin details DDPB_[3]P DDPB_[3]N DDPB_[2]P DDPB_[2]N DDPB_[1]P DDPB_[1]N DDPB_[0]P DDPB_[0]N DDPB_HPD DDPB_AUXP DDPB_AUXN DDPC_[3]P DDPC_[3]N DDPC_[2]P DDPC_[2]N DDPC_[1]P DDPC_[1]N DDPC_[0]P DDPC_[0]N DDPC_HPD DDPC_AUXP DDPC_AUXN DDPD_[3]P DDPD_[3]N DDPD_[2]P DDPD_[2]N DDPD_[1]P DDPD_[1]N DDPD_[0]P DDPD_[0]N DDPD_HPD DDPD_AUXP DDPD_AUXN
50
5.27.4 Multiple Display Configurations

Microsoft Windows* XP, Windows Vista* and Windows* 7 operating systems supports multiple displays. PCH has two pipes which send the display data out through the ports. Two display pipes enables the PCH to support two different images on different display devices. Single Display is a mode with one display port activated to display the output to one display device. Intel Dual Display Clone is a mode with two display ports activated to display the same output to two different display devices with the same color depth setting, but potentially different refresh rates and resolution settings. Extended Desktop is a mode with two display ports activated used to display two different outputs to two different display devices with potentially different color depth, refresh rate, and resolution settings. Table 5-61 describes the valid interoperability between display technologies. Table 5-60. Display Co-Existence Table
Display Not Attached DAC VGA Not Attached X S S S S S S DAC VGA S X S1, C, E A A S1, C, E S1, C, E Intel Integrated LVDS S S1, C, E X S1, C, E S1, C, E X X Integrated DisplayPort * S A S1, C, E A A S1, C, E S1, C, E HDMI*/D VI S A S1, C, E A X S1, C, E S1, C, E eDP*
S S1, C, E X S1, C, E S1, C, E X X
Integrated LVDS Integrated DisplayPort HDMI/DVI SDVO LVDS eDP
A = Single Pipe Single Display, Desktop Mode C = Clone Mode E = Extended Desktop Mode S = Single Pipe Single Display
Dual Display Clone (Only 24-bpp), or Extended
S1 = Single Pipe Single Display With One Display Device Disabled X = Unsupported/Not Applicable
5.27.5 High-bandwidth Digital Content Protection (HDCP)

HDCP is the technology for protecting high definition content against unauthorized copy or unreceptive between a source (computer, digital set top boxes, etc.) and the sink (panels, monitor and TVs). The PCH supports HDCP 1.4 for content protection over wired displays (HDMI, DVI and DisplayPort). The HDCP 1.4 keys are integrated into the PCH and customers are not required to physically configure or handle the keys.
51
5.27.6 Intel Flexible Display Interconnect

Intel FDI connects the display engine in the processor with the display interfaces on the PCH. The display data from the frame buffer is processed in the display engine of the processor and sent to the PCH over the Intel FDI where it is transcoded as per the display protocol and driven to the display monitor. Intel FDI has two channels A and B. Each channel has 4 lanes and total combined is 8 lanes to transfer the data from the processor to the PCH. Depending on the data bandwidth the interface is dynamically configured as x1, x2 or x4 lanes. Intel FDI supports lane reversal and lane polarity reversal.
17.
Correct Table 1-4. Intel 5 Series Chipset Mobile SKUs

Feature Set HDMI/DVI/VGA/SDVO/DisplayPort/eDP SKU Name(s) QM57 Yes HM57 Yes PM55 No HM55 Yes QS57 Yes
18.
Correct Table 1-3. Intel 5 Series Chipset Desktop SKUs

Feature Set HDMI/DVI/VGA/SDVO/DisplayPort/eDP SKU Name(s) Q57 Yes H57 Yes H55 Yes P55 No B55 Yes
19.
Controller Link Updates

a. Controller Link is supported on all platforms. References to Mobile Only are removed throughout the document. b. Controller Link signal names are updated as follows throughout the document: CL_RST# corrected to CL_RST1# CL_CLK corrected to CL_CLK1 CL_DATA corrected to CL_DATA1 c. AC timings are added in Section 8.6: Table 8-35 Controller Link Receive Timings
Sym t190 t191 t192 t193 t194 VIL_AC VIH_AC Parameter Single bit time Single clock period Rise time/Fall time Setup time before CL_CLK1 Hold time after CL_CLK1 Input low voltage (AC) Input high voltage (AC) CL_Vref +0.08 Min 13 15 0.11 0.9 0.9 Max 3.5 CL_Vref 0.08 Units ns ns V/ns ns ns V V 2 2 1 Notes Fig 8-30 8-30 8-31 8-30 8-30
52
NOTES: 1. Measured from (CL_Vref - 50mV to CL_Vref + 50mV) at the receiving device side. No test load is required for this measurement as the receiving device fulfills this purpose. 2. CL_Vref = 0.12*(VccSus3_3).
d. The following figures are added to section 8.9: Figure 8-30 Controller Link Receive Timings
t191 CL_CLK1 t190
t193 CL_DATA1
t194
Figure 8-31 Controller Link Receive Slew Rate
t192 CL_Vref + 50mV CL_Vref CL_CLK1 / CL_DATA1 CL_Vref 50mV
t192
e. CL_RST0# references are changed to CL_RST1# f. Controller Link signals are added to table 3-3:
Signal Name Power Plane During Reset1 Immediately after Reset1 S0/S1 S3 S4/S5
Controller Link CL_CLK16 CL_DATA16 CL_RST1#

6
Suspend Suspend Suspend
High/Low15 High/Low15 Low
High/Low15 High/Low15 High
Defined Defined High
g. Note 15 is added to table 3-3 as follows: 15. Controller Link Clock and Data buffers use internal pull-up and pull-down resistors to drive a logical 1 or a 0. h. Link Controller references are changed to Controller Link.
53
20.
Miscellaneous Typographical Error Corrections II

a. Default values for section 23.5.14 SIDSubsystem ID Register (D22:F2) and section 23.9.11 SIDSubsystem ID Register (D22:F3) are corrected from 0000h to 8086h. b. ACPI 3.0b references are changed to ACPI 4.0a throughout the document. c. Mobile Only / Desktop Only tags are removed from bits 27:26 of section 10.1.64 CGClock Gating (RCBA+341Ch) as shown:
Bit Description SATA Port 3 Dynamic Clock Gate Enable R/W. 27 0 = SATA Port 3 Dynamic Clock Gating is Disabled 1 = SATA Port 3 Dynamic Clock Gating is Enabled
Note: This bit may be Reserved depending on if port is available in the given SKU. See Section 1.3 for details if port is available.
SATA Port 2 Dynamic Clock Gate Enable R/W. 26 0 = SATA Port 2 Dynamic Clock Gating is Disabled 1 = SATA Port 2 Dynamic Clock Gating is Enabled
Note: This bit may be Reserved depending on if port is available in the given SKU. See Section 1.3 for details if port is available.
21.
Remove note 11 on Table 3-3

11. PMSYNCH is low in C6/C7 states only
22.
Remove VccpNAND on Table 8-3 and Table 8-4

Table 8-3 Measured ICC (Desktop Only)
S0 Iccmax Current Integrated Graphics (A) S0 Iccmax Current External Graphics (A) S0 Idle Current Integrated Graphics (A) S0 Idle Current External Graphics (A) Sx Iccmax Current (A) Sx Idle Current (A)
Voltage Rail
Voltage (V)
G3
VccpNAND
1.8
.0055
.0055
.0022
.0022
Table 8-4 Measured ICC (Mobile Only)

S0 Iccmax Current Integrated Graphics (A) S0 Iccmax Current External Graphics (A) S0 Idle Current Integrated Graphics (A) S0 Idle Current External Graphics (A) Sx Iccmax Current (A) Sx Idle Current (A)
Voltage Rail
Voltage (V)
G3
VccpNAND
1.8
.0055
.0055
.0022
.0022
54
23.
Section 8.2 Updates

The title of section 8.2 is changed as below.
8.2 Absolute Maximum and Minimum Ratings

The following paragraphs are added to section 8.2: Table 8-2 specifies absolute maximum and minimum ratings. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits (but within the absolute maximum and minimum ratings) the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time, it will either not function or its reliability will be severely degraded when returned to conditions within the functional operating condition limits. Although the PCH/ICHx contains protective circuitry to resist damage from Electro Static Discharge (ESD), precautions should always be taken to avoid high static voltages or electric fields.
24.
TEMP_ALERT# Muxing
TEMP_ALERT# functionality is muxed on SATA5GP/GPIO49. Figure 2-1, table 2-5, table 3-4, table 3-5, table 6-61 and table 6-62, SATA5GP/GPIO49 are updated to show SATA5GP/GPIO49/TEMP_ALERT#.
25.
Causes of Host and Global Resets Update

PROCPWRGD-to CPURST# Violation is removed from table 5-35.
26.
GPIO18 Toggling Note

Note 7 of table 2-25 is modified as shown: 7. GPIO18 will toggle at a frequency of approximately 1 Hz when the signal is programmed as a GPIO (when configured as an output) by BIOS.
27.
Pre-fetch Based Pause Bit Definition

The Pre-fetch Based Pause control bit is redefined as Pre-fetch Based Pause Enable with the following description:
Bit 4 Description Pre-fetch Based Pause Enable R/W. 0 = Pre-fetch Based Pause is disabled. 1 = Pre-fetch Based Pause is enabled.
28.
Register Corrections
a. Bit 2 of section 22.1.3 CMDCommand (D31:F6) is changed as shown:
55
Bit BME (Bus Master Enable) R/W. 2 0 = Function disabled as bus master. 1 = Function enabled as bus master.
Description
b. Section 22.2.12 PTAPCH Temperature Adjust (TBARB+14h) is changed as shown:

Bit 15:8 Description PCH Slope R/W. This field contains the PCH slope for calculating PCH temperature. The bits are locked by AE.bit7 (offset 3Fh). NOTE: When thermal reporting is enabled, BIOS must write 80h into this field. Offset R/W. This field contains the PCH offset for calculating PCH temperature. The bits are locked by AE.bit7 (offset 3Fh). NOTE: When thermal reporting is enabled, BIOS must write 8Ch into this field.
7:0
29.
Display BDF Register Additions

Bit 0 of section 10.1.66 FD2Function Disable 2 (RCBA+3428h) is changed as shown (Reserved bits are also corrected to show bits 31:5 instead of 31:0):
Bit 31:5 Reserved Description
30.
Miscellaneous Typographical Error Corrections III

a. TRST# is removed from tables 3-4 and 3-5. b. SATAGP[5:0] is corrected to SATA[5:0]GP in table 8-5. c. Port numbers are corrected in section 10.1.15 RPFNRoot Port Function Number and Hide for PCI Express* Root Ports (RCBA+0404h) as shown:
Bit 30:28 Description Root Port 8 Function Number (RP8FN) R/WO. These bits set the function number for PCI Express Root Port 8. This root port function number must be a unique value from the other root port function numbers Root Port 7 Function Number (RP7FN) R/WO. These bits set the function number for PCI Express Root Port 7. This root port function number must be a unique value from the other root port function numbers
26:24
d. Occurrences of SMBASE are changed to SMB_BASE throughout the document. e. In section 5.14.1.2, TCO_STS is changed to TCO2_STS. f. In section 13.9.3, TCO_STS is changed to TCO1_STS. g. Occurrences of PCH_PWROK are corrected to PWROK. h. Occurrences of e-SATA are corrected to eSATA.
56
31.
Chapter 8 Table Renumbering

Due to a formatting error, there are two table 8-1 and table 8-2 in chapter 8 of the Datasheet. The second table 8-1 (in section 8.2) is renumbered to table 8-3 and the second table 8-2 (in section 8.3) is renumbered to table 8-4. Note that all table numbers in this Specification Update refer to the numbers as published in Datasheet revision 1.5 and clarifications have been added where necessary to identify which of the duplicated table numbers is being referred to.
32.
AC Characteristics Notes Additions and Corrections

a. The following notes are added below to table 8-14 PCI Express* Interface Timing
1. 2. Specified at the measurement point into a timing and voltage compliance test load and measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye diagram) A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. Specified at the measurement point and measured over any 250 consecutive UIs. The test load documented in the PCI Express* specification 2.0 should be used as the RX device when taking measurements (also refer to the Receiver compliance eye diagram). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to--MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total 0.6 UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. Nominal Unit Interval is 400 ps for 2.5 GT/s and 200 ps for 5 GT/s.
3.
4.
5.
b. The following notes are added below to table 8-15 HDMI Interface Timings (DDP[D:B][3:0])Timings
1. 2.
Specified at the measurement point into a timing and voltage compliance test load and measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye diagram) A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value.
c. Table 8-15 HDMI Interface Timings (DDP[D:B][3:0])Timings, 5 is removed from the Notes column in the UI row. d. The following notes are added below to table 8-16 SDVO Interface Timings
1. 2. Specified at the measurement point into a timing and voltage compliance test load and measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye diagram) A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. Specified at the measurement point and measured over any 250 consecutive UIs. The test load documented in the PCI Express* specification 2.0 should be used as the RX device when taking measurements (also refer to the Receiver compliance eye diagram). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to--MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total 0.6 UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in
3.
4.
57
time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. Nominal Unit Interval for highest SDVO speed is 370 ps. However, depending on the resolution on the interface, the UI may be more than 370 ps.
33.
Table 8-22 Clock Timings

The SPI_CLK Slew_Rise and Slew_Fall figures reference numbers are changed from 8-27 to 8-29.
34.
Miscellaneous Typographical Error Corrections IV

a. Table 8-15 title is changed from HDMI Interface Timings (DDP[D:B][3:0])Timings to HDMI Interface Timings (DDP[D:B][3:0]). Table 8-15. HDMI Interface timings (DDP[D:B][3:0])Timings b. Section 10.1.13 RPCRoot Port Configuration Register bit 11 (GbE Over PCIe Root Port Enable (GBEPCIERPEN)) and bits 10:8 (GbE Over PCIe Root Port Select (GBEPCIERPSEL)) are R/W. 10.1.13 RPC-Root Port Configuration Register
GBE Over PCIe Root Port Select (GBEPCIERPSEL):R/W. If the GBEPCIERPEN is a 1, then this register determines which port is used for GbE MAC/PHY communication over PCI Express. This register is set by soft strap and is writable to support separate PHY on motherboard and docking station. 111 = Port 8 (Lane 7) 110 = Port 7 (Lane 6) 10:8 101 = Port 6 (Lane 5) 100 = Port 5 (Lane 4) 101 = Port 4 (Lane 3) 010 = Port 3 (Lane 2) 001 = Port 2 (Lane 1) 000 = Port 1 (Lane 0) The default value for this register is set by the GBE_PCIEPORTSEL[2:0] soft strap. NOTE: GbE and PCIE will use the output of this register and not the soft strap.
c. Section 12.1.15 ERBAExpansion ROM Base Address Register (Gigabit LAND25:F0) bit numbering is changed from 32:0 to 31:0. 12.1.15 ERBAExpansion ROM Base Address Register (Gigabit LAND25:F0)
Bit 31:0 Description Expansion ROM Base Address (ERBA)RO. This register is used to define the address and size information for boot-time access to the optional FLASH memory. If no Flash memory exists, this register reports 00000000h.
d. In table 14-1 SATA Controller PCI Register Address Map (SATAD31:F2), the mnemonic for SATA Capability Register 0 is changed from SCAP0 to SATACR0 and the mnemonic for SATA Capability Register 1 is changed from SCAP1 to SATACR1.
58
Table 14-1. SATA Controller PCI Register Address Map (SATA-D31:F2)

Offset A8hABh AChAFh Mnemonic SATACR0 SATACR1 Register Name SATA Capability Register 0 SATA Capability Register 1 Default 0010B012h 00000048h Type RO, R/WO RO
e. In table 15-1 SATA Controller PCI Register Address Map (SATAD31:F5), the mnemonic for SATA Capability Register 0 is changed from SCAP0 to SATACR0 and the mnemonic for SATA Capability Register 1 is changed from SCAP1 to SATACR1. Table 15-1. SATA Controller PCI Register Address Map (SATA-D31:F5)
Offset A8hABh AChAFh Mnemonic SATACR0 SATACR1 Register Name SATA Capability Register 0 SATA Capability Register 1 Default 0010B012h 00000048h Type RO RO
f.The sub-bullet 2 SPI Flash components or and 1 SPI Flash and 1 user authentication device are removed from section 5.24.1.2. 5.24.1.2 Descriptor Mode Supports up to two SPI components using two separate chip select pins 2 SPI Flash components or 1 SPI Flash and 1 user authentication device.
35.
Absolute Maximum Ratings

Table 8-1 PCH Absolute Maximum Ratings
Parameter Voltage on any 5 V Tolerant Pin with respect to Ground (V5REF = 5 V) Voltage on any 3.3 V Pin with respect to Ground Voltage on any 1.8 V Tolerant Pin with respect to Ground Voltage on any 1.5V Pin with respect to Gound Voltage on any 1.05 V Tolerant Pin with respect to Ground 1.05 V Supply Voltage with respect to VSS 1.8 V Supply Voltage with respect to VSS 3.3 V Supply Voltage with respect to VSS 5.0 V Supply Voltage with respect to VSS V_CPU_IO Supply Voltage with respect to VSS 1.8 V Supply Voltage for the analog PLL with respect to VSS Maximum Limits -0.5 to V5REF + 0.5 V -0.5 to Vcc3_3 + 0.4 V -0.5 to VccVRM + 0.5 V -0.5 to VccVRM + 0.5V -0.5 to VccIO + 0.5 V -0.5 to 1.3 V -0.5 to 3.7 V -0.5 to 3.7 V -0.5 to 5.5 V -0.5 to 1.3 V -0.5 to 1.98 V
59
36.
USB Register Corrections
Note: These frist several items are not new to the delta sheet, but were not in the Draft of the EDS sent out for review so are marked with a change bar.
a. 10.1.82 MISCCTLMiscellaneous Control Register offset address is changed from 3590-3594h to 3590-3593h. b. The following register is added after section 10.1.70: USBIREUSB Initialization Register D Offset Address: 35983599h Default Value: 0000h
Bit 15:1 0 Reserved. USB Initialization Register D Field 1 R/W. BIOS must set this bit to 0.
Attribute: Size:
Description
R/W 16-bit
c. The register size of 10.1.87 PDOUSB Port Disable Override is corrected from 22-bit to 32-bit. d. Section 16.1.31 EHCIIR1EHCI Initialization Register 1 is modified as shown: 16.1.31 EHCIIR1EHCI Initialization Register 1 (USB EHCID29:F0, D26:F0) Offset Address: 84h87h Attribute: R/W Default Value: 83088E01h Size: 32-bit
Bit 31:29 28 27:19 18 17:11 10:8 7:5 4 3:0 Reserved EHCI Prefetch Entry Clear R/W. 0 = EHC will clear prefetched entries in DMA. 1 = EHC will not clear prefetched entries in DMA Reserved EHCI Initialization Register 1 Field 2 R/W. BIOS must set this bit to 1. Reserved EHCI Initialization Register 1 Field 1 R/W. BIOS must set this field to 11. Reserved Intel Pre-fetch Based Pause Enable R/W. 0 = Intel Pre-fetch Based Pause is disabled. 1 = Intel Pre-fetch Based Pause is enabled. Reserved Description
e. The following register is added after section 16.1.31: EHCIIR2EHCI Initialization Register 2 (USB EHCID29:F0, D26:F0) Offset Address: 88h8Bh Attribute: R/W Default Value: 04000010h Size: 32-bit
60
Bit 31:30 29 28:20 19 18:12 11 10 9 8 7:6 5 4:0 Reserved
Description
EHCI Initialization Register 2 Field 6 R/W. BIOS must set this bit to 0. Reserved EHCI Initialization Register 2 Field 5 R/W. BIOS must set this bit to 1. Reserved EHCI Initialization Register 2 Field 4 R/W. BIOS must set this bit to 1. EHCI Initialization Register 2 Field 3 R/W. BIOS must set this bit to 1. Reserved EHCI Initialization Register 2 Field 2 R/W. BIOS must set this bit to 1. Reserved EHCI Initialization Register 2 Field 1 R/W. BIOS must set this bit to 1. Reserved
f. The following register is added after section 16.1.36: EHCIIR3EHCI Initialization Register 3 (USB EHCID29:F0, D26:F0) Offset Address: F4hF7h Attribute: R/W Default Value: 00408588h Size: 32-bit
Bit EHCIIR3 Write Enable R/W. 31 30:24 23:22 21:0 0 = Writes to the EHCIIR3 register are disabled 1 = If set, the values of the EHCIIR3 register may be modified Reserved EHCI Initialization Register 3 Field 1 R/W. BIOS must program this field to 10b. Reserved Description
g. The following register is added after section 16.1.36: HCIIR4EHCI Initialization Register 4 (USB EHCID29:F0, D26:F0) Offset Address: FChFFh Attribute: R/W Default Value: 20591708h Size: 32-bit
61
Bit 31:18 17 16 15 14:0 Reserved
Description
EHCI Initialization Register 4 Field 2 R/W. BIOS must set this bit to 1. Reserved EHCI Initialization Register 4 Field 1 R/W. BIOS must set this bit to 1. Reserved
h. 10.1.68 USBIRCUSB Initialization Register C bits 2:0 are defined as shown:

2 USB Initialization Register A Field 4 R/W BIOS must program this field to 0b. USB Clock Gating on Disconnected Ports R/W 1 This bit field controls the port gating setting for USB 0 = Clock gating is not enabled on USB ports that are disconnected 1 = Clock gating is enabled on USB ports that are disconnected USB Clock Gating on Suspended Ports R/W 0 This bit field controls the port gating setting for USB 0 = Clock gating is not enabled on USB ports that are suspended 1 = Clock gating is enabled on USB ports that are suspended
37.
Revised Industry Specifications

Table 1-1 is updated as shown below
Specification Location http://www.pcisig.com/specifications ftp://ftp.seagate.com/sff/SFF-8485.PDF http://www.intel.com/technology/serialata/ahci .htm http://www.intel.com/standards/hdaudio/
PCI Power Management Specification, Revision 1.2 SFF-8485 Specification for Serial GPIO (SGPIO) Bus, Revision 0.7 Advanced Host Controller Interface specification for Serial ATA, Revision 1.2 Intel High Definition Audio Specification, Revision 1.0
38.
Note Renumbering and Corrections on Table 3-1

a. The note for GPIO15 table 3-1 Integrated Pull-Up and Pull-Down Resistors is changed from 2 to 3.
39.
Power Management Initialization Register Updates

The following note is added after section 13.8.1.8 a. bit 20 will be read only when bit31 set to 1.
40.
(1/1/1) Chapter 9 Corrections

a. The following rows of table 9-2 Fixed I/O Ranges Decoded by PCH are changed as shown:
62
I/O Address 70h F0h 200h-207h 208h-20Fh
Read Target RESERVED1 FERR# / Interrupt Controller Gameport Low Gameport High
Write Target NMI and RTC Controller FERR# / Interrupt Controller Gameport Low Gameport High
Internal Unit RTC Processor I/F Forwarded to LPC Forwarded to LPC
b. Note 1 of table 9-2 Fixed I/O Ranges Decoded by PCH is changed to: 1. See Section 13.7.2 c. The following rows of table 9-3 Variable I/O Decode Ranges are changed as shown:
Range Name Mappable Size (Bytes) 1. 16 or 32 2. 16 Target 1. SATA Host Controller #1, #2 2. IDE-R 1. SATA Host Controller #1, #2 2. IDE-R 1. SATA Host Controller #1, #2 2. IDE-R SATA Host Controller #1, #2 GPIO Unit LPC Peripheral LAN Unit PCI Bridge PCI Express Root Ports 1-8 KT
IDE Bus Master
Anywhere in 64 KB I/O Space
Native IDE Command
Anywhere in 64 KB I/O Space1
Native IDE Control
Anywhere in 64 KB I/O Space1
SATA Index/Data Pair GPIO Parallel Port LAN PCI Bridge PCI Express Root Ports KT
Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space 3 Ranges in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space
16 128 83 322 I/O Base/Limit I/O Base/Limit 8
d. The note of table 9-4 Variable I/O Decode Ranges is replaced with the following notes:
Notes: 1. All ranges are decoded directly from DMI. The I/O cycles will not be seen on PCI, except the range associated with PCI bridge. 2. The LAN range is typically not used, as the registers can also be accessed via a memory space. There is also an alias 400h above the parallel port range that is used for ECP parallel ports.
e. The following rows of table 9-4 Memory Decode Ranges from Processor Perspective are changed as shown:
63
Memory Range 000E 0000h000E FFFFh 000F 0000h000F FFFFh FFC0 0000hFFC7 FFFFh FF80 0000hFF87 FFFFh FFC8 0000hFFCF FFFFh FF88 0000hFF8F FFFFh FFD0 0000hFFD7 FFFFh FF90 0000hFF97 FFFFh FFD8 0000hFFDF FFFFh FF98 0000hFF9F FFFFh FFE0 000hFFE7 FFFFh FFA0 0000hFFA7 FFFFh FFE8 0000hFFEF FFFFh FFA8 0000hFFAF FFFFh FFF0 0000hFFF7 FFFFh FFB0 0000hFFB7 FFFFh FFF8 0000hFFFF FFFFh FFB8 0000hFFBF FFFFh FF70 0000hFF7F FFFFh FF30 0000hFF3F FFFFh FF60 0000hFF6F FFFFh FF20 0000hFF2F FFFFh FF50 0000hFF5F FFFFh FF10 0000hFF1F FFFFh FF40 0000hFF4F FFFFh FF00 0000hFF0F FFFFh 128 KB anywhere in 4 GB range 4 KB anywhere in 4 GB range 1 KB anywhere in 4 GB range 1 KB anywhere in 4 GB range FED4 0000hFED4 FFFFh Memory Base/Limit anywhere in 4 GB range Prefetchable Memory Base/Limit anywhere in 64-bit address range 64 KB anywhere in 4 GB range
Target LPC or SPI LPC or SPI LPC or SPI (or PCI)2 LPC or SPI (or PCI)2 LPC or SPI (or PCI)2 LPC or SPI (or PCI)2 LPC or SPI (or PCI)2 LPC or SPI (or PCI)3 LPC or SPI (or PCI)2 LPC or SPI (or PCI)2 LPC or SPI (or PCI)2 LPC or SPI (or PCI)2 LPC or SPI (or PCI)2 LPC or SPI (or PCI)2 Integrated LAN Controller Integrated LAN Controller USB EHCI Controller #11 USB EHCI Controller #21 TPM on LPC PCI Bridge
Dependency/Comments Bit 6 in BIOS Decode Enable register is set Bit 7 in BIOS Decode Enable register is set Bit 8 in BIOS Decode Enable register is set Bit 9 in BIOS Decode Enable register is set Bit 10 in BIOS Decode Enable register is set Bit 11 in BIOS Decode Enable register is set Bit 12 in BIOS Decode Enable register is set Bit 13 in BIOS Decode Enable register is set Bit 14 in BIOS Decode Enable register is set Always enabled. The top two 64 KB blocks of this range can be swapped, as described in Section 9.4.1. Bit 3 in BIOS Decode Enable register is set Bit 2 in BIOS Decode Enable register is set Bit 1 in BIOS Decode Enable register is set Bit 0 in BIOS Decode Enable register is set Enable using BAR in Device 25:Function 0 (Integrated LAN Controller MBARA) Enable using BAR in Device 25:Function 0 (Integrated LAN Controller MBARB) Enable using standard PCI mechanism (Device 29, Function 0) Enable using standard PCI mechanism (Device 26, Function 0) None Enable via standard PCI mechanism (Device 30: Function 0) Enable via standard PCI mechanism (Device 30: Function 0) LPC Generic Memory Range. Enable via setting bit[0] of the LPC Generic Memory Range register (D31:F0:offset 98h).
PCI Bridge
LPC
64
Memory Range 32 Bytes anywhere in 64-bit address range 2 KB anywhere above 64 KB to 4 GB range Memory Base/Limit anywhere in 4 GB range Prefetchable Memory Base/Limit anywhere in 64-bit address range 4 KB anywhere in 64-bit address range 4 KB anywhere in 64-bit address range 16 Bytes anywhere in 64-bit address range 4 KB anywhere in 4 GB range 16 KB anywhere in 4 GB range
Target SMBus SATA Host Controller #1 PCI Express Root Ports 1-8 PCI Express Root Ports 1-8 Thermal Reporting Thermal Reporting Intel MEI #1, #2 KT Root Complex Register Block (RCRB)
Dependency/Comments Enable via standard PCI mechanism (Device 31: Function 3) AHCI memory-mapped registers. Enable via standard PCI mechanism (Device 31: Function 2) Enable via standard PCI mechanism (Device 28: Function 0-7) Enable via standard PCI mechanism (Device 28: Function 0-7) Enable via standard PCI mechanism (Device 31: Function 6 TBAR/TBARH) Enable via standard PCI mechanism (Device 31: Function 6 TBARB/TBARBH) Enable via standard PCI mechanism (Device 22: Function 1:0) Enable via standard PCI mechanism (Device 22: Function 3) Enable via setting bit[0] of the Root Complex Base Address register (D31:F0:offset F0h).
f. Section 9.4.1 Boot-Block Update Scheme is replaced with the following: The PCH supports a top-block swap mode that has the PCH swap the top block in the FWH or SPI flash (the boot block) with another location. This allows for safe update of the Boot Block (even if a power failure occurs). When the TOP_SWAP Enable bit is set, the PCH will invert A16 for cycles going to the upper two 64 KB blocks in the FWH or appropriate address lines as selected in Boot Block Size (BOOT_BLOCK_SIZE) soft strap for SPI. Specifically for FHW, in this mode accesses to FFFF_0000h-FFFF_FFFFh are directed to FFFE_0000h-FFFE_FFFFh and vice versa. When the Top Swap Enable bit is 0, the PCH will not invert A16. Specifically for SPI, in this mode the Top-Block Swap behavior is as described below. When the Top Swap Enable bit is 0, the PCH will not invert any address bit. Table 9-5 SPI Mode Address Swapping
BOOT_BLOCK_SIZE Value 000 (64KB) 001 (128KB) 010 (256KB) Accesses to FFFF_0000h - FFFF_FFFFh FFFE_0000h - FFFF_FFFFh FFFC_0000h - FFFF_FFFFh Being Directed to FFFE_0000h - FFFE_FFFFh and vice versa FFFC_0000h - FFFD_FFFFh and vice versa FFF8_0000h - FFFB_FFFFh and vice versa
65
Table 9-5 SPI Mode Address Swapping

BOOT_BLOCK_SIZE Value 011 (512KB) 100 (1MB) 101 - 111 Accesses to FFF8_0000h - FFFF_FFFFh FFF0_0000h - FFFF_FFFFh Reserved Being Directed to FFF0_0000h - FFF7_FFFFh and vice versa FFE0_0000h - FFEF_FFFFh and vice versa Reserved
This bit is automatically set to 0 by RTCRST#, but not by PLTRST#. The scheme is based on the concept that the top block is reserved as the boot block, and the block immediately below the top block is reserved for doing boot-block updates. The algorithm is: 1. Software copies the top block to the block immediately below the top 2. Software checks that the copied block is correct. This could be done by performing a checksum calculation. 3. Software sets the TOP_SWAP bit. This will invert the appropriate address bits for the cycles going to the FWH or SPI. 4. Software erases the top block 5. Software writes the new top block 6. Software checks the new top block 7. Software clears the TOP_SWAP bit Software sets the Top_Swap Lock-Down bit If a power failure occurs at any point after step 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. This is because the TOP_SWAP bit is backed in the RTC well. Note: The top-block swap mode may be forced by an external strapping option (See Section 2-28). When top-block swap mode is forced in this manner, the TOP_SWAP bit cannot be cleared by software. A re-boot with the strap removed will be required to exit a forced top-block swap mode. Top-block swap mode only affects accesses to the Firmware Hub space, not feature space for FWH. The top-block swap mode has no effect on accesses below FFFE_0000h for FWH.
Note:
41.
HD Audio Corrections
a. The register name for the MMUA register in table 17-1 Intel High Definition Audio PCI Register Address Map is corrected to MSI Message Upper Address b. The Parity Error Response bit description in section 17.1.1.3 PCICMDPCI Command Register (Intel High Definition Audio ControllerD27:F0) is updated to:
Bit 6 Description Parity Error Response (PER) R/W. PER functionality not implemented.
66
c. The INTLNInterrupt Line Register (Intel High Definition Audio ControllerD27:F0) of section 17.1.1.7 is not reset by a Function Level Reset; this information is added to the register attributes. d. The following note is added to section 17.2 Intel High Definition Audio Memory Mapped Configuration Registers: Address locations that are not shown should be treated as Reserved. e. The mnemonic and abbreviation for Immediate Command Status is changed to ICS in table 17-2 Intel High Definition Audio Memory Mapped Configuration Registers Address Map and section 17.2.32. f. The description for Stream Synchronization (SSYNC) in section 17.1.2.15 SSYNCStream Synchronization Register (Intel High Definition Audio ControllerD27:F0) is updated as follows. Due to formatting issues, bits 5, 6, and 7 were not visible:
Bit Description Stream Synchronization (SSYNC) R/W. When set to 1, these bits block data from being sent on or received from the link. Each bit controls the associated stream descriptor (that is, bit 0 corresponds to the first stream descriptor, etc.) To synchronously start a set of DMA engines, these bits are first set to 1. The RUN bits for the associated stream descriptors are then set to 1 to start the DMA engines. When all streams are ready (FIFORDY =1), the associated SSYNC bits can all be set to 0 at the same time, and transmission or reception of bits to or from the link will begin together at the start of the next full link frame. To synchronously stop the streams, fist these bits are set, and then the individual RUN bits in the stream descriptor are cleared by software. If synchronization is not desired, these bits may be left as 0, and the stream will simply 7:0 begin running normally when the streams RUN bit is set. The streams are numbered and the SIE bits assigned sequentially, based on their order in the register set. Bit 0 = input stream 1 Bit 1 = input stream 2 Bit 2 = input stream 3 Bit 3 = input stream 4 Bit 4 = output stream 1 Bit 5 = output stream 2 Bit 6 = output stream 3 Bit 7 = output stream 4
g. The name of bits 31:7 in section 17.1.2.23 RIRBLBASERIRB Lower Base Address Register (Intel High Definition Audio ControllerD27:F0) is corrected to RIRB Lower Base Address. h. The following register is added after section 17.1.1.19: HDINIT1Intel High Definition Audio Initialization Register 1 (Intel High Definition Audio ControllerD27:F0) Address Offset: 43h Attribute: RO Default Value: 07h Size: 8 bits
67
Bit 7 6 5:3 2:0 Reserved.
Description
HDINIT1 Field 2 R/W. BIOS must set this bit to 1. Reserved. HDINIT1 Field 1 R/W. BIOS must program this field to 111b.
68
Preface ...................................................................................................................... 7 Affected Documents/Related Documents ................................................................ 7 Nomenclature ..................................................................................................... 7 Summary Tables of Changes...................................................................................... 8 Codes Used in Summary Tables............................................................................. 8 Stepping ................................................................................................. 8 Page....................................................................................................... 8 Status .................................................................................................... 8 Row ....................................................................................................... 8 Errata ................................................................................................................ 9 Specification Changes ........................................................................................ 10 Specification Clarification.................................................................................... 10 Documentation Changes..................................................................................... 11 Identification Information ....................................................................................... 13 Markings .......................................................................................................... 13 PCH Device and Revision Identification ................................................................... 14 Errata ...................................................................................................................... 16 Specification Changes.............................................................................................. 27 Specification Clarification ........................................................................................ 30 Documentation Changes .......................................................................................... 36

322170

Încărcat de

Informații document

Descriere originală:

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

322170

Încărcat de

Drepturi de autor:

Formate disponibile

Intel 5 Series Chipset and Intel 3400 Series Chipset

Document Number: 322170-019

Isochronous Packet Truncation Added

January 13, 2010

February 13, 2010

March 10, 2010

IntelQS57 Chipset High Definition Audio Device ID Updated

May 12, 2010

May 17, 2010

July 14, 2010

August 11, 2010

Errata: 23 - Pixel Corruption Over Integrated LVDS Interface of Intel 5 Series

October 13, 2010

November 10, 2010

January 12, 2011

February 16, 2011

Revision -018 -019

March 16, 2011

April 13, 2011

Jun 13, 2011

Affected Documents/Related Documents

Summary Tables of Changes

Summary Tables of Changes

Codes Used in Summary Tables

Summary Tables of Changes

Summary Tables of Changes

Summary Tables of Changes

Documentation Changes (Sheet 1 of 2)

Summary Tables of Changes

Documentation Changes (Sheet 2 of 2)

PCH Device and Revision Identification

PCH Device and Revision Identification

PCH Device and Revision Identification

B2 Rev ID 05h 05h 05h 05h A5h A5h

B3 Rev ID 06h 06h 06h 06h A6h A6h

Intel MEI #1 Intel MEI #2 IDE-R KT NOTES:

No Fix. For steppings affected, see the Summary Table of Changes.

Workaround: BIOS workaround available. Status:

Workaround: None. Status:

Workaround: None. Status:

Workaround: None Status:

Workaround: None. Status:

Workaround: None Status:

Workaround: None Status:

Pixel Corruption Over Integrated LVDS Interface of Intel 5 Series Chipset

Workaround: None. Status:

USB Isoch In Transfer Error Issue

Workaround: None. Status: No Plan to Fix.

USB Full-Speed / Low-Speed Device Removal Issue

Workaround: None. Status:

USB Babble Detected with SW Overscheduling

Workaround: None. Status:

USB Low-Speed/Full-Speed EOP Issue

Workaround: None. Status:

USB PLL Control FSM not Getting Reset on Global Reset

Workaround: None. Status:

Asynchronous Retries Prioritized Over Periodic Transfers

Workaround: None. Status:

Incorrect Data for LS or FS USB Periodic IN Transaction

Implication: Note: Status:

Workaround: None. Status: No Plan to Fix.

Table 8-26 SMBus and SMLink Timing

Min 4.7 1.3