Electronics II

[1] (a) In the following circuit , and given that respectivily

and rd for the FET are 30 and 5 K

50 K G VS 40 K
D

10 K

5K Rload

Determine Zout (seen by load ) , Zin ( seen by source ) and Av ( Vload / Vs ) ( 10 marks)

/ Avm

vgs 3 vgs

Z out Z in Avm Vout Thus

= Zx // 5 K where Zx = 5K // 50 K // 10 K = (50 K / Avm ) + 40 K = vout / vgs = 30 vgs ( Zx / [ Zx + 5 K ] ) potential divider principle Vout = 30 ( Zx / [ Zx + 5 K ] )

(b ) In the following circuit ;

VDD RL Q2

2 Q1 D1

V2

S1 V1

Given that the two FET transistors are Identical with parameters , r d and gm find an expression for the signal voltage across R Load , in terms of V1, V2 and circuit componets ( 10 marks )
(rd+Rl) / ( 1+ ) / ( 1+ )

Using Small signal equivalent circuit and considering the componets in FET2 as a load for FET 1 . ie. Reflect all components in FET 2 into the source of FET 2 ( and subsequently the drain of FET1) as follows : Applying KVL around the circuit shown : v2 / ( 1+ ) + v1 = I [ rd + ( rd + Rl) / (1+ ) ] Solving for I we obtain : I= v2 / D + ( 1+ ) v1 / D where D = [( 2+ )rd + Rl ] But Vl = - I Rl i.e Vl = [ v2 / D + ( 1+ ) v1 / D ] Rl

[2] In the following circuit Both transistors are identical with hfe = 50 , the source voltage v is an AC one

rd D1

12V +V R2 10k

Q1 NPN

R1 1k

R4 15k + Q2 NPN R3 1k

Vo

- 6 V

10V U1

Find hie (4 marks) Considering the input loop for transistor Q2 , then we may write the following equation ( KVL) : 6 =15K * IBQ + 0.7 + 1k * IEQ 5.3 =15K * IBQ + 1K *IBQ ( 1+ ) from thie above equation we deduce IBQ and subsequently ; hie = VT/IBQ =26mV / IBQ Find the value of Rl such that Vo ( dc ) = 0 (4 marks ) Consider the input loop for transistor Q1 : 10K * IBQ +0.7 V + Rl * IEQ = Vo = 0 Subsituting for the value of IEQ from the above requirement will yeild RL Draw the samll signal equivalent circuit : ( 4Marks )

Calculate the value ( use approximation as needed ) of Vo/V

( 6 marks)

Write down an expression for Ri ( the resistance seen , looking in the circuit from the voltage source terminals ) : ( 4 marks ) Ri = (( 1+ ) 1K + hie + 15 K)

Write down an expression for Ro ( the resistance seen , looking in the circuit from the output terminal ) : ( 4 Marks )

[3] In the following circuit :

VCC

Io

Prove that : Io =[ / ( +2 ) ] [ ( VCC VBE ) / R ] ( 6 Marks ) Current pasing through resistor r , I x = IC1 + 2 IB = IB + 2 IB = IB ( +2 ) KVL yeild Vcc 0.7 = Ix ( r ) Substitute for IX in the first equation ; (Vcc 0.7 ) / R = IB ( +2 ) Thus IB = (Vcc 0.7 ) ( +2 ) / R The current passing through the collector of Q2 , Io = IB i.e. Io =[ / ( +2 ) ] [ ( VCC VBE ) / R ] [4] In the following circuit :

Ground

Q1= Q

RE

6V +V

R2 1k Q1 NPN R1 1k + R3 100 V1 10V U2 U1

Vc

VE

Is1 100mA

Determi e t e val e of VBB for maximum possi le voltage collector swi g ( hfe =50 ) ( 8 Marks ) Appl i g the followi g design equations ; IC = VCC / ( Rac + Rdc ) Then after calculating IC we deduce IB from IC = IB Appl ing KV around the input loop VBB may be obtained VBB =1K * IBA + 0.7 + 100 * IB ( 1+ ) Draw a wave diagram showning the maximum possible swings in the output voltages at the collector ( Vc ) and the Emitter ( VE ) -Solve this part on a separate paper and then enter the required answer : (10Marks)

[5] In the following Op - Amp Circuit :

Rf

Ra

R V1

Vo

Write down an expression for Vo interms of V1 , V2 , V3 and cct components (10 Marks ) Using the superposition method , i.e. The total output voltage equals the sum of output voltages due to each input source acting alone Taking v2, v3 to be aero ( short circuited ) Then vout1 , due to v3 = - V3 ( Rf / Ra ) Taking V3 , V2 to be zero Then Vout2 , due to v1 = v1 [ 10 R / ( 10 R + R ) ] * [ 1 + Rf/Ra ] Taking V1 , V3 to be zero Then Vout2 , due to v2 = v2 [ R / ( 10 R + R ) ] * [ 1 + Rf/Ra ] Vout total = Vout1 + Vout2 + Vout3 = - v3 ( Rf/ Ra ) +[ v1 ( 10/11) + v2 ( 1/11)] [1 + Rf/Ra ]

[7] In the following Power Amplifier Circuit :

11V
.7

(a) Draw the AC / DC Load Lines

10 R Ground

:1
60 Ohms

hfe

00 0 Micro F

0. 6 ( 5 Marks )

19. 4

10.4

C load lin

11 V

15. V

For the DC load line

The voltage intersection is 11 V and the current intersection = 11/0.56K = 19.64 mA (b) Calculate the power efficiency of the amplifier ( 10 Marks ) RB = 4.7 // 2.2 = 1.5 K , VBB = 3.5 V KVl input circuit yeild : 3.5 0.7 1.5 K IBQ 0.56 K . IBQ = 0 IBQ = 2.8 / 113.5 K = 0.025 mA and ICQ = 0.025 ( 200 ) = 5 Ignoring the primary resistance of the transformer VCEQ =VCC ICQ ( RE ) = 8.2V Apparent Load resistance = 60 ( 5/1 ) = 1.5 K For the AC load line , The voltage intersection is given by VCEQ + ICQ . Rac =15.7 V where Rac = approx 0.56 K The current intersection is given by ; ICQ + VCEQ / Rac = 10.47 mA Power in ( ignoring that dissipated in the bias circuit = ICQ . VCC = 55 mW Power out = (I load ) . Rl / 2 = ( 5 . 5 . 10 ) 60 /2 = 18.75 mW Efficiency = Pout / P in = 55 / 18.75 . 100 % =29.33 %

 

Vcc / Rdc

 
DC load lin

(c) Explain the advantage of using the transformer in the design of A class amplifier ( 5 marks ) The advantage of using the transformer : (1) It is a mean for the isolation of the load from the rest of the drive circuit (2) Provide a means for matching the load with the drive circuit (3) Increase the maximum power of efficiency which could be attained from class A amplifier by increasing the apparent maximum allowable voltage swing at the colloector of the amplifier , as a result of the increase apparent load ( when reflected by the transformer )