FABRICATION OF ICS

FABRICATION OF ICS
INTRODUCTION:
The Manufacturing of ICs (integrated circuit) is the process which need very accuracy and also need very precision instruments. It is the process which consists of many simple and sophisticated steps. Mainly it needs the very expensive labs and computer technology. Semiconductor device fabrication is the process used to create the integrated circuits (silicon chips) that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is the most commonly used semiconductor material today, along with various compound semiconductors. The entire manufacturing process, from start to packaged chips ready for shipment, takes six to eight weeks and is performed in highly specialized facilities referred to as fabs.

SOME HISTORY:
When feature widths were far greater than about 10 micrometres, purity was not the issue that it is today in device manufacturing. As devices became more integrated, cleanrooms became even cleaner. Today, the fabs are pressurized with filtered air to remove even the smallest particles, which could come to rest on the wafers and contribute to defects. The workers in a
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semiconductor fabrication facility are required to wear cleanroom suits to protect the devices from human contamination.

In an effort to increase profits, semiconductor device manufacturing has spread from Texas and California in the 1960s to the rest of the world, such as Europe, Israel, and Asia. It is a global business today.

SOME SEMICONDUCTORS MANUFACTURERS:

The leading semiconductor manufacturers typically have facilities all over the world. Intel, the world's largest manufacturer, has facilities in Europe and Asia as well as the U.S. Other top manufacturers include STMicroelectronics (Europe), Analog Devices (US), Integrated Device Technology (US), Atmel (US/Europe), Freescale Semiconductor (US), Samsung (Korea), Texas Instruments (US), GlobalFoundries (Germany, Singapore, future New York fab in construction), Toshiba (Japan), NEC Electronics (Japan), Infineon (Europe), Renesas (Japan), Taiwan Semiconductor Manufacturing Company (Taiwan), Fujitsu (Japan/US), NXP Semiconductors (Europe), Micron Technology (US), Hynix (Korea) and SMIC (China).

The Detail Description of Semiconductor ICs Fabrication consists of the following steps:

1-WAFER PREPERATION:
A wafer is a thin slice of semiconductor material, such as a silicon crystal, used in the fabrication of integrated circuits and other microdevices. The wafer serves as the substrate for microelectronic devices built in and over the wafer and undergoes many microfabrication process steps such as doping or ion implantation, etching, deposition of various materials, and photolithographic patterning.
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Wafers are formed of highly pure (99.9999% purity),[1] nearly defect-free single crystalline material.[2] One process for forming crystalline wafers is known as Czochralski growth invented by the Polish chemist Jan Czochralski. In this process, a cylindrical ingot of high purity monocrystalline silicon is formed by pulling a seed crystal from a 'melt'.[3][4] Dopant impurity atoms such as boron or phosphorus can be added to the molten intrinsic silicon in precise amounts in order to dope the silicon, thus changing it into n-type or p-type extrinsic silicon. The ingot is then sliced with a wafer saw (wire saw) and polished to form wafers.[5] The size of wafers for photovoltaics is 100 200 mm square and the thickness is 200 - 300 m. In the future, 160 m will be the standard.[6] Electronics use wafer sizes from 100 - 300mm diameter. (The largest wafer made has a diameter of 450mm but isn't in production yet). SIX LAYERS OF INTERCONNECTION

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FIGURE:

Wafers are cleaned with weak acids to remove unwanted particles, or repair damage caused during the sawing process. When used for solar cells, the wafers are textured to create a rough surface to increase their efficiency. The generated PSG (phosphosilicate glass) is removed from the edge of the wafer in the etching.

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Wafers are prepared using Czochralski Process.

The Czochralski Process can be divided into following further steps:

1. 2. 3. 4. 5.

Czochralski growth Shaping Slicing Lapping and chemical etching Polishing

Crystal Growth: The two most important semiconductors for discrete devices and integrated circuits are silicon and gallium arsenide. Silicon Crystal Growth from the Melt. For Silicon Crystal growth the technique is called Czochralski technique. Process Flow

Starting Material: The staring material for silicon is a relative pure form of sand (SiO 2) called quartzite. This is placed in a furnace with various forms of carbons (Coal, coke and wood chips) at 1200C. The overall reaction is

SiC(solid) + SiO2 -> Si(Solid) + SiO(gas) + CO(gas) This process produces silicon with a purity of 98%. Now it react with HCl at 300C forming liquid cholride (SiHCl3) of Silicon. From this trichlorosilane (SiHCl3) is produced, it is liquid at room temperature. Fractional Distillation of this one removes the impurities.

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Then from a reduction reaction a electronic-grade silicon (EGS) is produce, EGS a polycrystalline material of high purity, is the raw material used to prepare device quality, single crystal silicon.Pure EGS generally has impurity concentrations in the parts-per-billion range. Now after the preparation of the EGS, the pure polycrystalline Silicon is placed and heated above the melting temperature of the Silicon, then the suitable seed crystal is suspended on the polycrystalline solid then this seed is inserted in to the melt silicon. It is then slowly pull upward and the melting silicon is then converting in to the solid crystal. Two important parameters are Rotational speed and pull rate. Diameter of the ingot is a function of pull rate.

2- Wafer Shaping:
In this step the ingot is grind to a uniform diameter using a lathe-type surface grinder.After the crystal grown, the first shaping operation is to remove the seed and the other end of the ingot, which is last to solidify. The next operation is to grind the surface so that the diameter of the material is defined. After that one or more flat regions are ground along the length of the ingot. These regions, or flats, mark the specific crystal orientation of the ingot and conductivity type of the material. Two types of flats are Primary Flats and Secondary Flats.

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3- Slicing:
Ingot is sliced into wafers. The ingots are then ready to be sliced by diamond saw into wafers.

4- Chemical Etching & lapping:

Is used to produce clean wafers of desired thickness..After slicing, both sides of the wafer are lapped to produce typical flatness uniformity within 2um. But it usually leaves the surface and edges of the wafer damaged and contaminated. This can be removed by chemical etching.

5- Polishing:
Is used to provide a smooth surface to the wafers. In the last polishing is done to provide a smooth, specular surface where device feature can be defined by photolithographic processes.

6-Crystal Defects:
A real crystal (such as silicon wafer) differs from the ideal crystal in important way, It is finite; thus surface atoms are incompletely bounded. Furthermore it has defects, which strongly influence the electrical, mechanical and optical properties of the semiconductor. There are four categories of defects * Point * Line * Area * Volume

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7- MASK Making:
A glass plate with a pattern of transparent and opaque areas used to photo lithographically creates patterns on wafers. A mask is commonly used to refer to a plate that has a pattern large enough to pattern a whole wafer at one time. Purpose is to control adding and removal of material only at specified places. This pattern is transferred through the process of lithography. Types of mask are Full Wafer Mask and single Die mask.

8- PHOTOLITHOGRAPHY: Photolithography is the process of transferring

patterns of geometric shapes on a mask to a thin layer of photosensitive material (called Photoresist) covering the surface of a semiconductor wafer. These patterns define the various regions in an IC, such as the implantation regions, the contact windows and the bonding pad areas. The resist patterns defined by the lithographic process are not permanent elements of the final device, but only replicas of circuit features. These patterns define the various regions in an IC, such as the implantation regions, the contact windows and the bonding pad areas. The resist patterns defined by the lithographic process are not permanent elements of the final device, but only replicas of circuit features. Optical Lithography: The vast majority of lithographic equipment for IC fabrication is optical equipment using ultraviolet light.

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THE HOUSE WHERE ICS ARE ABLE TO FABRICATE CLEAN ROOM:

Lithography area in clean room

The ultra-clean environment where microprocessors are made is called a clean room. Class one clean rooms are the cleanest of all, with no more than one speck
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of dust per cubic foot. Imagine a boulder large enough to cause traffic jams all over a big
city. If one fell on Times Square in New York, it could stop traffic on many streets around it, and eventually stop traffic on adjacent streets through a ripple effect. The same is true of a speck of dust landing in the middle of a microprocessor. Just one microscopic particle can obstruct the chip's pathways, ultimately rendering it unusable.

Clean rooms are 10,000 times cleaner than a hospital operating room. It takes an incredible amount of technology to achieve and maintain such cleanliness. Huge air filtration systems completely change the air in clean rooms about ten times per minute, reducing the chance that there are airborne particles that might harm the chips .Suiting up is a rather involved process, not to mention that every time you enter and leave a clean room you have to repeat at least 43 steps twice. If you have never done it before, putting on a bunny suit can take 30 to 40 minutes.

9- Types of Photo-resist:
Positive and Negative Photo-resist. When exposed to light positive resist becomes more soluble to the developing chemicals and negative resist becomes less soluble to these developers. Since positive has a higher resolution than negative type, because whole resist mass swells by absorbing developer solvent. Positive photo-resist is more commonly used.

FIGURES OF PHOTOLITHOGRAPHY:

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9- No Mask Lithography:
Electronic Beam Lithography: For lithography below 0.5u geometrics, a technique called e-beam lithography is used.In this technique there is no use of mask, rather the e-beam is used to directly write the pattern onto the resist coated wafer.This technique is considered quite slow now a days. But in future it would give more throughput with faster performance.

10- Epitaxial Layer:

"The term Epitaxial comes from the Greek word meaning 'arranged upon.' CMOS devices are usually formed in a thin crystalline layer of silicon which is grown on top of silicon substrate. This thin layer is called an epitaxial (epi) layer. Devices are formed in this layer because electrical properties of this layer can be controlled more carefully than that of substrate.

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The Silicon layer is obtained at the temperature of 1000 to 1200 0C in a LPCVD reaction chamber by the following reaction. SiCl4 + 2H2O Si+ 4HCL

11- Diffusion and Ion Implantation:

Ability to change the doping level or type essential in IC fabrication process since parts of the IC have to be doped differently in order that the IC functions correctly. For example, for a high gain BJT, emitter doping>base doping>collector doping.Epitaxy changes the doping over the whole of the wafer (globally) whereas more often it is required to change the doping over part of the slice (selectively). Photolithography used to form patterns on the wafer surface but cannot, in itself, be used as a mask to prevent dopants reaching the silicon wafer underneath it. This is because both diffusion and ion implantation are high temperature/high energy processes and the chemical elements involved would simply pass through the photo-resist. Silicon dioxide which can be easily formed on the surface of the wafer and is very dense and strong, is capable of forming an excellent dopant barrier. Diffusion (or solid state diffusion) is the process whereby a solid will physically diffuse itself into another solid in close contact with it due to the random thermal movement of atoms. Ion Implantation is the most common method of supplying doping atoms for the diffusion process. It provides a low temperature means of supplying well controlled doses of doping atoms. To form a p-type region the element boron is diffused into silicon while the elements arsenic or phosphorus used to form n-type regions. For an n-type wafer placed in a furnace at high temperatures in the presence of a high concentration of boron, the boron will progressively diffuse into the wafer to a depth dependent on the furnace temperature and duration. (Typical depths used
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are 0.25-2.0m). A p-n junction is then formed in the wafer whose electrical properties are those of a diode and is electrically stable. Further diffusions can be used to form n-p-n, BJTs, MOSFETS, resistors, etc.

12- Ion Implantation

Alternative to diffusion which may be used in certain cases. Some diffusion processes are difficult to control accurately in terms of junction depths and doping concentration and in particular, due to the high temperatures involved, the profiles of the dopant fronts are not square but tapered in depth resulting in non-ideal device performance. Ion implantation works in two stages by firing high energy atoms of the relevant elements, say boron, onto the silicon wafer. The ions travel a small distance (typically <1m) into the wafer before losing their energy and being absorbed. Accurate control of the energy of the ions ensures that the absorption depth has a tight tolerance.

13-Material Removal ( Etching):

In variety of processes the deposition of materials is done on the entire wafer by means of CVD, but we do not require this all. Therefore it must be removed. The removal of a particular material from undesired areas is known as etching. There are two types of etching, Wet Etching and Dry Etching.

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THE END
SOURCES: Lectures And Videos related with VLSI Manufacturing.

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