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SDLS029C DECEMBER 1983 REVISED JANUARY 2004

SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS

D Dependable Texas Instruments Quality and


Reliability

description/ordering information
These devices contain six independent inverters.

SN5404 . . . J PACKAGE SN54LS04, SN54S04 . . . J OR W PACKAGE SN7404, SN74S04 . . . D, N, OR NS PACKAGE SN74LS04 . . . D, DB, N, OR NS PACKAGE (TOP VIEW)

1A 1Y 2A 2Y 3A 3Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

VCC 6A 6Y 5A 5Y 4A 4Y

SN5404 . . . W PACKAGE (TOP VIEW)

1A 2Y 2A VCC 3A 3Y 4A

1 2 3 4 5 6 7

14 13 12 11 10 9 8

1Y 6A 6Y GND 5Y 5A 4Y

SN54LS04, SN54S04 . . . FK PACKAGE (TOP VIEW)

2A NC 2Y NC 3A

4 5 6 7 8

3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

1Y 1A NC VCC 6A 6Y NC 5A NC 5Y
NC No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

Copyright 2004, Texas Instruments Incorporated

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3Y GND NC 4Y 4A

SDLS029C DECEMBER 1983 REVISED JANUARY 2004

SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS

ORDERING INFORMATION
TA PACKAGE Tube PDIP N Tube Tube Tube Tape and reel Tube 0 C 70 C 0C to 70C SOIC D Tape and reel Tube Tape and reel Tape and reel SOP NS SSOP DB Tape and reel Tape and reel Tape and reel Tube Tube Tube CDIP J Tube Tube 55 C 125C 55C to 125 C CFP W Tube Tube Tube Tube Tube LCCC FK Tube ORDERABLE PART NUMBER SN7404N SN74LS04N SN74S04N SN7404D SN7404DR SN74LS04D SN74LS04DR SN74S04D SN74S04DR SN7404NSR SN74LS04NSR SN74S04NSR SN74LS04DBR SN5404J SNJ5404J SN54LS04J SN54S04J SNJ54LS04J SNJ54S04J SNJ5404W SNJ54LS04W SNJ54S04W SNJ54LS04FK SNJ54S04FK S04 SN7404 74LS04 74S04 LS04 SN5404J SNJ5404J SN54LS04J SN54S04J SNJ54LS04J SNJ54S04J SNJ5404W SNJ54LS04W SNJ54S04W SNJ54LS04FK SNJ54S04FK LS04 7404 TOP-SIDE MARKING SN7404N SN74LS04N SN74S04N

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each inverter) INPUT A H L OUTPUT Y L H

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SDLS029C DECEMBER 1983 REVISED JANUARY 2004

SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS

logic diagram (positive logic)


1A 1Y

2A

2Y

3A

3Y

4A

4Y

5A

5Y

6A Y=A

6Y

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SDLS029C DECEMBER 1983 REVISED JANUARY 2004

SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS


schematics (each gate)

04 VCC 130

4 k

1.6 k

Input A Output Y

1 k GND

LS04 VCC 20 k 8 k 120 2.8 k

S04 VCC 900 50

Input A 12 k

4 k

Output Y

Input A

3.5 k

Output Y

500 3 k 1.5 k

250

GND GND

Resistor values shown are nominal.

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SDLS029C DECEMBER 1983 REVISED JANUARY 2004

SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI: 04, S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)


SN5404 MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature 55 4.5 2 0.8 0.4 16 125 0 NOM 5 MAX 5.5 MIN 4.75 2 0.8 0.4 16 70 SN7404 NOM 5 MAX 5.25 UNIT V V V mA mA C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IIH IIL IOS ICCH ICCL VCC = MIN, VCC = MIN, VCC = MIN, VCC = MAX, VCC = MAX, VCC = MAX, VCC = MAX VCC = MAX, VCC = MAX, VI = 0 V VI = 4.5 V TEST CONDITIONS II = 12 mA VIL = 0.8 V, VIH = 2 V, VI = 5.5 V VI = 2.4 V VI = 0.4 V 20 6 18 MIN 2.4 SN5404 TYP 3.4 0.2 0.4 1 40 1.6 55 12 33 18 6 18 MAX 1.5 IOH = 0.4 mA IOL = 16 mA 2.4 3.4 0.2 0.4 1 40 1.6 55 12 33 MIN SN7404 TYP MAX 1.5 UNIT V V V mA A mA mA mA mA

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time.

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SDLS029C DECEMBER 1983 REVISED JANUARY 2004

SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS

switching characteristics, VCC = 5 V, TA = 25C (see Figure 1)


PARAMETER tPLH tPHL FROM (INPUT) A TO (OUTPUT) Y TEST CONDITIONS MIN RL = 400 , CL = 15 pF SN5404 SN7404 TYP 12 8 MAX 22 15 ns UNIT

recommended operating conditions (see Note 3)


SN54LS04 MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature 55 4.5 2 0.7 0.4 4 125 0 NOM 5 MAX 5.5 SN74LS04 MIN 4.75 2 0.8 0.4 8 70 NOM 5 MAX 5.25 UNIT V V V mA mA C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IIH IIL IOS ICCH ICCL VCC = MIN, VCC = MIN, VCC = MIN, VCC = MAX, VCC = MAX, VCC = MAX, VCC = MAX VCC = MAX, VCC = MAX, TEST CONDITIONS II = 18 mA VIL = MAX, VIH = 2 V VI = 7 V VI = 2.7 V VI = 0.4 V 20 VI = 0 V VI = 4.5 V 1.2 3.6 SN54LS04 MIN TYP MAX 1.5 IOH = 0.4 mA IOL = 4 mA IOL = 8 mA 0.1 20 0.4 100 2.4 6.6 20 1.2 3.6 2.5 3.4 0.25 0.4 0.25 2.7 3.4 0.4 0.5 0.1 20 0.4 100 2.4 6.6 SN74LS04 MIN TYP MAX 1.5 UNIT V V V mA A mA mA mA mA

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25C (see Figure 2)


PARAMETER tPLH tPHL FROM (INPUT) A TO (OUTPUT) Y TEST CONDITIONS SN54LS04 SN74LS04 MIN RL = 2 k, CL = 15 pF TYP 9 10 MAX 15 15 ns UNIT

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SDLS029C DECEMBER 1983 REVISED JANUARY 2004

SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS

recommended operating conditions (see Note 3)


SN54S04 MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature 55 4.5 2 0.8 1 20 125 0 NOM 5 MAX 5.5 MIN 4.75 2 0.8 1 20 70 SN74S04 NOM 5 MAX 5.25 UNIT V V V mA mA C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IIH IIL IOS ICCH ICCL VCC = MIN, VCC = MIN, VCC = MIN, VCC = MAX, VCC = MAX, VCC = MAX, VCC = MAX VCC = MAX, VCC = MAX, VI = 0 V VI = 4.5 V TEST CONDITIONS II = 18 mA VIL = 0.8 V, VIH = 2 V, VI = 5.5 V VI = 2.7 V VI = 0.5 V 40 15 30 MIN 2.5 SN54S04 TYP MAX 1.2 IOH = 1 mA IOL = 20 mA 3.4 0.5 1 50 2 100 24 54 40 15 30 2.7 3.4 0.5 1 50 2 100 24 54 MIN SN74S04 TYP MAX 1.2 UNIT V V V mA A mA mA mA mA

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25C (see Figure 1)


PARAMETER tPLH tPHL tPLH tPHL FROM (INPUT) A A TO (OUTPUT) Y Y TEST CONDITIONS MIN RL = 280 , RL = 280 , CL = 15 pF CL = 50 pF SN54S04 SN74S04 TYP 3 3 4.5 5 MAX 4.5 5 ns ns UNIT

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SDLS029C DECEMBER 1983 REVISED JANUARY 2004

SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS

PARAMETER MEASUREMENT INFORMATION SERIES 54/74 AND 54S/74S DEVICES


VCC Test Point VCC VCC RL From Output Under Test CL (see Note A) RL (see Note B) From Output Under Test CL (see Note A) Test Point S2 Test Point RL S1 (see Note B) 1 k

From Output Under Test CL (see Note A)

LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS High-Level Pulse

LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS Timing Input tsu 1.5 V Data Input 1.5 V

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V 1.5 V 0V th 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

1.5 V tw

1.5 V

Low-Level Pulse

1.5 V

VOLTAGE WAVEFORMS PULSE DURATIONS Output Control (low-level enabling) tPZL Waveform 1 (see Notes C and D) tPZH VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Waveform 2 (see Notes C and D)

3V 1.5 V 1.5 V 0V tPLZ 1.5 V VOL tPHZ VOH 1.5 V VOH 0.5 V 1.5 V VOL + 0.5 V

3V Input 1.5 V 1.5 V 0V tPLH In-Phase Output (see Note D) tPHL Out-of-Phase Output (see Note D) 1.5 V tPHL VOH 1.5 V VOL tPLH

1.5 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 ; tr and tf 7 ns for Series 54/74 devices and tr and tf 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time, with one input transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

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SDLS029C DECEMBER 1983 REVISED JANUARY 2004

SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS

PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES


VCC Test Point VCC VCC RL From Output Under Test CL (see Note A) RL (see Note B) From Output Under Test CL (see Note A) Test Point S2 Test Point RL S1 (see Note B) 5 k

From Output Under Test CL (see Note A)

LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS High-Level Pulse

LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS Timing Input tsu 1.3 V Data Input 1.3 V

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V 1.3 V 0V th 3V 1.3 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

1.3 V tw

1.3 V

Low-Level Pulse

1.3 V

VOLTAGE WAVEFORMS PULSE DURATIONS Output Control (low-level enabling) tPZL Waveform 1 (see Notes C and D) tPZH VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Waveform 2 (see Notes C and D)

3V 1.3 V 1.3 V 0V tPLZ 1.5 V VOL tPHZ VOH 1.3 V VOH 0.5 V 1.5 V VOL + 0.5 V

3V Input 1.3 V 1.3 V 0V tPLH In-Phase Output (see Note D) tPHL Out-of-Phase Output (see Note D) 1.3 V tPHL VOH 1.3 V VOL tPLH

1.3 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 , tr 1.5 ns, tf 2.6 ns. G. The outputs are measured one at a time, with one input transition per measurement.

Figure 2. Load Circuits and Voltage Waveforms

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MECHANICAL DATA
MCFP002A JANUARY 1995 REVISED FEBRUARY 2002

W (R-GDFP-F14)

CERAMIC DUAL FLATPACK


Base and Seating Plane

0.045 (1,14) 0.026 (0,66)

0.260 (6,60) 0.235 (5,97)

0.080 (2,03) 0.045 (1,14)

0.008 (0,20) 0.004 (0,10)

0.280 (7,11) MAX 1 14 0.019 (0,48) 0.015 (0,38)

0.050 (1,27)

0.390 (9,91) 0.335 (8,51) 0.005 (0,13) MIN 4 Places

7 0.360 (9,14) 0.250 (6,35)

8 0.360 (9,14) 0.250 (6,35)

4040180-2 / C 02/02 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB

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MECHANICAL DATA
MLCC006B OCTOBER 1996

FK (S-CQCC-N**)
28 TERMINAL SHOWN

LEADLESS CERAMIC CHIP CARRIER

18

17

16

15

14

13

12

NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20

A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)

B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)

19 20 21 B SQ 22 A SQ 23 24 25

26

27

28

4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)

0.020 (0,51) 0.010 (0,25)

0.055 (1,40) 0.045 (1,14)

0.045 (1,14) 0.035 (0,89)

0.028 (0,71) 0.022 (0,54) 0.050 (1,27)

0.045 (1,14) 0.035 (0,89)

4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004

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