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Dr. David S. Touretzky

Hexapod Robots

Issue 5 August 2, 2011

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TA B L E O F C O N T E N T S
Dr. David S. Touretzky
RESEARCH PROFESSOR, CARNEGIE MELLON UNIVERSITY
Interview with Dr. David S. Touretzky, research professor in the Computer Science Department and the Center for the Neural Basis of Cognition at Carnegie Mellon University.

4 8 11 14

TABLE OF CONTENTS

Creating Combinatorial Logic (Part 1)

BY RAY SALEMI
Salemi discusses concurrent (VHDL) and continuous (Verilog) assignments and how these can be used to implement simple combinatorial logic and buffers.

A Plan for Debug

BY PHIL SIMPSON WITH ALTERA
Help reduce the in-system debug cycle and improve the quality of your FPGA design.

RTZ - Return to Zero Comic

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INTERVIEW

Dr. David S. Touretzky

Hexapod Robots, Center for the Neural Basis of Cognition
How did you get into electronics and when did you start? I got into ham radio and electronics at age 10, and discovered computers at age 12. I taught myself BASIC programming from a textbook. Then I taught myself assembly language programming. In high school I worked part time for a computer company. The pay was minimum wage but they offered all the free computer time I wanted, which was worth a lot more! When did you start to get into robotics? It has been at least 10 years, maybe 15. I came to Carnegie Mellon in 1978 as a graduate student. The robotics institute started in 1979. I was here from the beginning, but I did not do robotics then. I was a Computer Science PhD student. I took some robotics course work, but did not seriously get into robotics until after I became a faculty member. The CMU Robotics Institute is the largest academic robotics group in the world. We have our own PhD program, three masters programs and a large faculty with a very big facility. What are your favorite hardware tools that you use? I build robots, so I use a laser cutter, a milling machine, and lots of servos. What are your favorite software tools that you use? Solidworks for CAD work. C++ and MATLAB for software development. What is on your bookshelf? I am slowly trying to learn quantum mechanics. Right now Im reading Noson Yanofsky and Mirco Mannuccis Quantum Computing for Computer Scientists, and Manjit Kumars Quantum: Einstein, Bohr, and the Great Debate about the Nature of Reality. Both are excellent books. Do you have any tricks up your sleeve? I take a constructivist approach to understanding. When I study something, I ask How could I build this, or how can I build things with this? This is opposed to, for example, Where might I observe this in nature? I also tend to ask right away, What are the limits of this? Where does it break?

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INTERVIEW
Do you have any note-worthy engineering experiences? Im actually a computer scientist who dabbles in engineering. One interesting experience I had as a computer scientist occurred when the Motion Picture Association filed a lawsuit to suppress publication of computer code for decrypting DVD movies. The judge granted a preliminary injunction barring the defendants from distributing the code, but not from discussing the algorithm, which he thought was protected speech. I created a now famous web site, the Gallery of CSS Descramblers, demonstrating that this distinction made no sense; computer code is speech. This led to my testifying as an expert defense witness in federal court. The judge appreciated my testimony and concluded that code really is speech. But the defendants still lost. What has been your favorite project? I designed a hexapod robot called the Chiara, which some students of mine have used to do really cool things. One programmed two Chiaras to play chess on a real chessboard. Another got a Chiara to walk up to an electronic keyboard and play Ode to Joy. Can you tell us more about Chiara? It bears some resemblance to a spider or crab, but the head makes it closer to a praying mantis. The robot in the photo is still an early design; it needs more refinement before we can actually sell it. We are working now on the next generation, which will be closer to a mantis. The body of the Chiara is laser cut acrylic. That is actually one of the problems with it, acrylic is pretty fragile. We cannot ship the Chiara; we have to deliver them by hand. For the new robot, we are hoping to go with a new structure and software framework called Tekkotsu (Japanese for framework) for teaching robotics to students using the AIBO. When Sony left the robotics business in 2006, no one stepped in to fill that market niche. I was forced to start developing my own platforms so we would have something to use, because you could not buy anything at a reasonable price. This is how I ended up in the robot business. I am having a lot of fun, but am eagerly looking forward to the day when I am run out of the business by big companies with serious financial resources. My aspiration is that manufacturers see my robots and decide they can design something better; I will happily pay retail if they offer attractive products. Then I can go back to being a software guy. What types of sensors are mounted on the robot? There is an webcam mounted on the head. There is also a 3-direction IR range finder mounted just below the webcam. There are some pushbuttons on the back as well. There are about 27 servos used in the Chiara, depending on the configuration. Most of the Chiaras that we built do not have a closable gripper, they just have a C bracket so they can push things, but cannot grasp them. We also built some that could play chess last year. We built a specialized gripper to pick up chess pieces. All of the control is done on board. The computer onboard is comparable to a laptop. The robot is basically a laptop with legs: it runs Linux and has its own IP address. In collaboration

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The pay was minimum wage but they offered all the free computer time I wanted, which was worth a lot more.
enclosure out of a different material. We are looking at laser cut ABS plastic or some kind of vacuum forming process. Injection molding would be great but we dont have that kind of budget. What are the communications methods with Chiara? It has both Wi-Fi and Ethernet. There is an antenna for Wi-Fi and an Ethernet jack if you need to run it wired. The Chiara is designed for robotics education. We have a serious problem in terms of robotics education for undergraduates. Many schools are still using LEGO MindStorms because they cannot buy anything better. LEGO MindStorms is great if youre a ten year old tinkering with robotics, but when youre twenty and have spent the last 2 or 3 years studying serious computer science, its completely inadequate. The Sony AIBO robot dog was a great robotics education platform. In 2003 I started developing a

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INTERVIEW
with a local company called RoPro Design, we have delivered a total of 21 robots besides the ones in my lab. Carnegie Mellon owns six. Cornell has the only green one. What are you currently working on? The robot I am working on now, a short term successor to the Chiara, is called Calliope. Its built on top of the iRobot Create. Calliope has a camera on a pan/tilt like Chiara had, and it has a larger, more complex arm. It uses an ASUS netbook for onboard control. Long term, we are promoting the hexapod. Legs are better than wheels. But servo prices have to come down first. A big problem with robotics today is that the components are produced in small quantities; theres no economy of scale. We are in our early days. You can learn more about Chiara and other projects we are working on at Chiara-Robot.org Im developing a software framework called Tekkotsu that makes it easy for students to program sophisticated robots such as the Chiara. Im also looking into building a praying mantis robot. In what direction do you see your business heading in the next few years? Were still in the early days of the robotics business, with products that are primitive and yet expensive. But the pace of development has quickened and I think were going to see a lot of exciting new platforms in the next few years. The Microsoft Kinect is a good example of how important bits of technology can suddenly become an order of magnitude cheaper and more sophisticated. Expect more of these surprises. What challenges do you foresee in the industry? People are rightly concerned about keeping the STEM (Science, Technology, Engineering, and Mathematics) education pipeline filled so that we can take full advantage of our native talent pool. NSF has a bunch of programs that are trying to address this need. I am one of the founders of the ARTSI Alliance, an NSF-funded consortium of 17 Historically Black Colleges and Universities and 8 major research universities that is working to recruit more African Americans to pursue advanced training in computer science and robotics. Im also working with a similar organization in Puerto Rico. Robotics is increasingly dependent on good software engineering, so its vital that we attract more students to computer science so that the engineers have colleagues who can program the robots they build.

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Creating Combinatorial Logic

Ray Salemi
Verification Consultant Verification Consultant

PART 1
see how these can be used to implement simple combinatorial logic and buffers. For the purposes of this article, Im going to stop saying concurrent and continuous assignments and am going to refer to both by the Verilog name continuous assignments because that gives a closer feel for whats going on. A continuous assignment monitors the signals on the right hand of its equation and executes whenever one of them changes. Here is an example of a simple continuous assignment from a cache design. It tells us whether we have a cache miss. (See Figure 1)
cache_miss <= (invalid or tag_miss) and rd;

n the first issue, we put the R into RTL by discussing registers and how to create them in Verilog and VHDL. We learned how to create resets, both synchronous and asynchronous, clock enables, and even...clock enables with resets. But, creating registers is only part of the story when it comes to digital design. The next part of the story is creating combinatorial logic. Combinatorial logic is the kind of logic we learn about in our first digital course. Combinatorial circuits are sets of AND, OR, NAND, NOR, and even XOR gates that we assemble to create functionality in our digital design. Verilog and VHDL have three ways for you to create combinatorial logic: 1. You can use concurrent assignments, or continuous assignments to describe logic. 2. You can create processes that implement continuous assignments. 3. You can place equations on the input side of your registers. Today we are going to talk about Number 1. Concurrent (VHDL) and continuous (Verilog) assignments. Well

invalid tag_miss rd cache_miss

assign cache_miss = (invalid | tag_miss) & rd;

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F E AT U R E D A R T I C L E
The beauty of continuous assignments is that we no longer need to use those Karnaugh maps they taught us about in our first digital circuits class. We can let the synthesis tool do all the work for us. For example, here is an equation from the Wikipedia entry on Karnaugh maps: f = ac + ab + bcd + ad We can minimize this function by simply entering it directly into a continuous assignment and letting the synthesis tool do the work:
f <= (a and not c) or (a and not b) or (b and c and not d) or (a and not d);

Here are examples of both mechanism. In this code we either output the value of the data bus or high impedance:
output_bus <= data_bus when enable = 1 else (others => Z) ;

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data_bus(7:0) enable

output_bus(7:0)

assign output_bus = (enable) ? data_bus : z;

Figure 3

b a c f c

Here we see that the synthesis tool has understood us perfectly and created a tristate buffer. Using concurrent and continuous assignments is a simple way to create simple combinatorial circuits. But what if we want to create something more complicated? For example, what if we want a combinatorial circuit that will detect an edge in an array of data from a sensor? We would need code like this to create a project like a linefollowing robot. Well discuss that in my next article when we see how to create combinatorial logic with process blocks and always blocks. Well also discuss the evil of latches. About the Author Ray Salemi is a veteran of the EDA industry and has been working with Hardware Description Languages since he joined Gateway Design Automationthe company that invented Verilog. Over the course of his career he has worked at Cadence, Sun Microsystems, and Mentor Graphics. Ray is currently an Applications Engineer Consultant with Mentor Graphics.

assign f = a & ~c | a & ~b | b & c & ~d | a & ~d;

Figure 2

Of course, the joke is really on us because any 4-variable equation like this gets sucked up into a single LUT on most FPGA technologies. It doesnt matter how we optimize it. Continuous assignments allow you to easily implement tristate logic on the output of a block. If you have several blocks that talk together on a bus, you can implement their buffers with a continuous assignment. Both Verilog and VHDL have two features that make this possible: Z as a value: Verilog and VHDL (using std_logic) allow you to assign the value Z to a signal. Synthesis tools interpret the value Z to mean that you want to create a tristate device. Conditional Assignments: Both Verilog and VHDL allow you to put conditionals into concurrent assignments. Synthesis devices interpret the conditional assignment signal to be the control on the tristate buffer. VHDL uses the WHEN construct to implement the conditional assignment, while Verilog uses the C-like conditional assignment.

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A PLAN
FOR DE
Phil Simpson Ray Salemi
Sr. Manager, SW Product Planning Verification Consultant

ith the increase in complexity of FPGA device capabilities and the associated designs targeting these FPGA devices, in-system debug can quickly become a bottleneck in the FPGA design cycle. This article describes a methodology that can help reduce the in-system debug cycle and improve the quality of your design. The debug of any type of semiconductor device that is operating in-system can be a challenging and nerve racking experience. You cross your fingers, power up your board, the FPGA loads with your design and nothing happensor at least not the behavior that you expected to see. Deep down inside, you knew this would happen, but you hoped that everything would function perfectly the first time. You were too busy designing to the latest changes in specification to consider how to debug the different features in the design while it is running in-system. You now start the stressful and tedious task of trying to isolate the problem within the device that is running, possibly by stripping out parts of the design and trying to

shoehorn in debug logic or an FPGA vendor Embedded Logic Analyzer (ELA). This can be a slow and laborious task involving long delays waiting for FPGA compilations to finish in order to obtain new design images to debug. Seasoned veterans have been through the pressure of debugging designs many times and want to minimize the time spent in this high-pressure environment. They avoid spending evenings and weekends in the lab trying to determine the cause of the problem. But how is this accomplished? Its simple: plan for debug up front. Combine some of the techniques that are commonly used in ASIC design with the advantages provided by hardware programmability and the in-system debug tools that are provided by the FPGA vendor. This delivers the best of both worlds. In-system debug requirements should be built into the specification for an FPGA design. This should cover how each of the major blocks in the design should be verified in-system. Also included should be information on the type

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F E AT U R E D A R T I C L E
of data that can be viewed to determine that the block is operating as intended. This could include system-level statistics such as the efficiency of memory interfaces, performance bottleneck analysis on buses and bit error ratio information on high-speed transceiver interfaces. The specification will detail the techniques and tools that will be used as part of the in-system debug process to capture the information. This includes information on how many pins, how much logic, how much memory is reserved for in-system debug, and where FPGA debug tools should be used versus user-created debug logic. The definition of the debug strategy should also include the channel to be used for accessing debug data. The ELAs that are provided by the major FPGA vendors typically use JTAG as the channel for debug. The design engineer needs to determine how to extract data from their debug logic that they have used in the design. They can use device pins, hook it up to the ELA, or design their own debug channel. One technique is to use a soft processor to control the debug process and access the debug data. The user debug logic provides a good starting point in identifying the area of the design where the problem manifests. It helps to avoid numerous recompiles of the design in trying to isolate the problem. Altera provides a utility, called SystemConsole, for accessing user-created debug logic via an API. It is effectively an interactive console for low-level system debug of designs over various communication channels, including JTAG and TCP/IP It also provides read and write access . to the debug IP in the design via a set of TCL-based commands as shown in Figure 1. Once the problem area has been identified, the user can then use the FPGA vendor-provided ELAs to further refine the analysis of the problem. This will require incremental compiles of the design, however the number of design recompiles should be substantially fewer than trying to identify the problem without initial debug data. Following is an In-System Debug Checklist to ensure successful verification of your design. In-System Debug Checklist 1. Plan for debug a. Reserve logic and memory resources for Embedded Logic Analyzer (ELA) use. b. Ensure that you use the JTAG interface to the FPGA. c. Place a Header on the Board as an interface to an external logic analyzer or scope. d. Reserve pins for debug. e. Add debug logic to your design or consider using the FPGA vendor utilities for forcing data to memories and multiplexing data at the pins. f. Consider adding a soft processor to your design for debug. 2. Perform debug a. Lock down the design implementation using incremental compilation. b. For free running data, or for a small handful of control signals, incrementally route the signals to pins for analysis on a logic analyzer or scope. c. In order to capture data based on events, add an ELA to your design. Where possible, use post-fit signal names to avoid a full recompile of the design. d. If there are multiple devices within the JTAG chain, select the device that you want to target. 3. Recreate the problem in RTL simulation
DSP Filter DSP Filter DSP Filter

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FPGA
JTAG Stream JTAG SNK SRC

System Console

a. Once you have identified the bug, fix the RTL and validate that the fix works with functional simulation. In summary, FPGA design debug does not need to be

Figure 1: Sample application of an in-system debug via

the SystemConsole utility

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a last minute panic. You can reduce your FPGA design debug cycle time by using a combination of planning for debug and utilizing FPGA vendor supplied debug tools. Further details on FPGA debug techniques are available in the book FPGA Design: Best Practices for TeamBased Design, by Phil Simpson. Springer Publishing, 2010. About the Author Phil Simpson is Alteras senior manager for software technical marketing, product planning, and EDA relationships. In this role, he is responsible for Alteras Quartus II software and third-party EDA interfaces product planning and the creation of the Altera design flow software roadmap. Prior to joining Altera in 1997, Phil held several engineering roles at various EDA and semiconductor companies, including EDA Solutions, Data I/O, and Graseby Microsystems. He holds a B.S. (with honors) in Electrical & Electronic Engineering from City University, London and an M.S.C. (with distinction) in system design from the University of Central England, Birmingham, England. Phil is a published book author on team-based FPGA design. In addition he has written and had published numerous technical articles on topics related to his experience.s on topics related to his experience.

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