Electric Power Systems Research 77 (2007) 989999

Control of cascaded transformer multilevel inverter based DSTATCOM

Rajesh Gupta a , Arindam Ghosh b, , Avinash Joshi a
b

Department of Electrical Engineering, Indian Institute of Technology, Kanpur 208016, India School of Engineering Systems, Queensland University of Technology, Brisbane, Qld 4001, Australia Received 6 January 2006; received in revised form 9 June 2006; accepted 25 August 2006 Available online 12 October 2006

Abstract In this paper, the design of a distribution static compensator (DSTATCOM) based on cascaded transformer multilevel inverter is proposed. The topology requires controlling only a common dc storage capacitor. Two-level ramp-comparison current control method is extended for the multilevel inverter using phase-shifted multi-carrier PWM. The method provides equal switching stress and power handling for all the cascaded units. The net switching frequency increases while the ripple magnitude reduces using multilevel topology. These cause the feedforward gain to increase leading to a higher bandwidth of the control loop. An expression of the feedforward gain is derived for xed switching frequency modulation of the inverter. It is shown that the use of proportional plus resonant controller with proposed multilevel modulation improves the tracking characteristics at fundamental frequency. A seven-level inverter based DSTATCOM is proposed for the application to the three-phase medium voltage distribution system and the results are shown through the PSCAD/EMTDC simulation. The proposed modulation and control scheme is validated through the experimental results that are obtained using the laboratory model of a single-phase, ve-level inverter based DSTATCOM. 2006 Elsevier B.V. All rights reserved.
Keywords: Cascaded transformer; DSTATCOM; Multilevel; Resonant controller

1. Introduction Several variations of cascaded topology have been attempted for STATCOM applications [1,2]. There are few applications of cascaded multilevel inverters for shunt compensation of distribution systems [3,4]. Cascaded multilevel conguration of inverter has the advantage of its simplicity over a diode-clamped multilevel inverter (DCMLI) or a ying-capacitor multilevel inverter (FCMLI). The DCMLI or FCMLI congurations require additional diodes or capacitors whereas the cascaded topology requires a separate dc-link capacitor for each cell, requiring a complex control strategy to regulate the voltage across each capacitor. Moreover, for unequal dc-link voltages, the switching strategies employed will be unable to provide equal switching stress and power handling for all cascaded units. Recently cascaded transformer multilevel topology is proposed [5,6]. This has the advantage of having single storage capacitor for all its cells. Therefore, the dc voltage across each cell is equal. This topology has much signicance for higher rated converters used

Corresponding author. Tel.: +61 7 3864 2459; fax: +61 7 3864 1516. E-mail address: a.ghosh@qut.edu.au (A. Ghosh).

for high or medium voltage distribution system, as they require transformers to increase the inverter output voltage at the distribution level [79]. There are various current control methods for two-level converters [10]. The hysteresis control of power converters, based on instantaneous current errors, is widely used as it has good dynamic characteristics and robustness against parameter variations and load non-linearties [9]. However, the switching pattern is not xed and depends upon the system parameters and operating conditions. This disadvantage is overcome by using the ramp-comparison modulation scheme. The scheme, while retaining the dynamic and robustness properties of hysteresis control, provides a constant switching frequency that is decided by a triangular carrier frequency [11]. However, the method suffers from the disadvantage of having tracking error in the steady state for low frequencies that is inversely proportional to the feedforward gain. This gain is limited by the ripple magnitude of the error function. The use of proportional plus resonant controller tuned near the fundamental frequency minimizes the tracking error at this frequency [12,13]. A distribution static compensator (DSTATCOM) is a voltage source converter (VSC) based device. When operated in a current control mode, it can improve the quality of power by mitigating

0378-7796/$ see front matter 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.epsr.2006.08.015

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poor load power factor, eliminating harmonic content of load and balancing source currents for unbalanced loads [8,9]. In this paper a cascaded transformer, multilevel level inverter based DSTATCOM control is proposed. The topology requires common dc-link capacitor for each cascaded units of all the three phases. Hence only a single dc storage capacitor needs to be controlled. The two-level ramp-comparison method of control is extended for the multilevel inverter following the principle of phase-shifted multi-carrier unipolar PWM. The method provides equal switching stress for all the H-bridge units. Also each switch of the H-bridge is stressed equally. The basic motivations for the use of multilevel inverters are the reduction of voltage stress on the power electronic devices and reduction in the harmonic content of voltage and current delivered. The multilevel cascaded topology with phase-shifted carrier reduces the effective switching delay due to PWM and ripple magnitude in the current error. The reduction in the ripple magnitude allows the use of higher feedforward gain. The reduction in switching delay and higher feedforward gain improves the bandwidth of the current control loop. An expression has been derived for the maximum feedforward gain required for smooth modulation at xed switching frequency. The use of above method allows replacing the multilevel modulator by a constant gain and a xed delay. This allows analysis of the current control loop of the DSTATCOM using linear theory. The application is shown through the simulation studies of the three-phase, seven-level inverter controlled DSTATCOM and the proposed

modulation and control scheme is validated through the experimental results for single-phase, ve-level inverter controlled DSTATCOM. 2. Modeling and control of multilevel inverter Fig. 1 shows the single line diagram of a shunt compensated distribution system with load supplied through a feeder. For higher rated DSTATCOMs, the switching frequency and device ratings are limited. Therefore, it is desirable to distribute the stress among number of devices. For an n-level inverter (n = 3, 5, 7, . . .), the voltage stress of semiconductor switches and dclink capacitor is 2/(n 1) times the net dc-link voltage required. The total number of power semiconductor devices required perphase is 2 (n 1). Since the dc-link voltage across each H-bridge is common therefore use of phase shifted unipolar PWM lead harmonic spectrum of the inverter output voltage to lie at (n 1) times the frequency of the carrier wave and the side bands shifted from this center in the multiples of the fundamental frequency [14]. Also the magnitude of the switching harmonics in the PWM output is reduced by a factor 1/(n 1). These two conditions considerably reduce the ripples in the switching function and allow smooth modulation of the multilevel inverter at xed switching frequency. The output voltage levels are added through the secondary of the (n 1)/2 = N number of cascaded transformers. Therefore,

Fig. 1. Single-phase line diagram of cascaded multilevel DSTATCOM controlled distribution system.

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the principle of unipolar PWM [15], i.e., +Vdc 2 Vdc Condition 1.2 : se < vtri , then Sw4 is on and vAO = 2 where O is the assumed to be the mid point of the dc input voltage (see Fig. 3). Similarly for other phase leg of H-bridge, Condition 1.1 : se > vtri , then Sw1 is on and vAO = +Vdc 2 Vdc Condition 2.2 : se < vtri , then Sw2 is on and vBO = 2 Therefore, the net voltage levels obtained for one H-bridge between points A1 and B1 are +Vdc , 0 and Vdc . The same process is repeated with remaining H-bridges with the carriers phase-shifted by the corresponding angles. The output voltages VA1 B1 , VA2 B2 , VA3 B3 as shown in Fig. 1 are added through the secondary terminals of the transformers. Condition 2.1 : se > vtri , then Sw3 is on and vBO =
Fig. 2. Carrier phase shifted unipolar PWM of switching function.

2.2. Multilevel PWM as gain and delay for obtaining ve switched dc levels two H-bridges are used. Similarly for seven switched dc levels, three H-bridges are used as shown in Fig. 1. For phase shifted cascaded PWM, the phase shift of each carrier is (i 1)/N, where i is the ith converter. For ve-level inverter the phase shifts of carriers required are 0 and /2 and for seven-level inverter these phase shifts required are 0, /3 and 2/3 radians. Fig. 2 shows the carrier phaseshifted PWM for ramp-comparison control of VSC with sevenlevels of normalized output. The carrier frequency is 1.0 kHz and therefore the harmonic cancellation up to 6.0 kHz is achieved. Note however that all semiconductor switches of VSC operate at 1.0 kHz uniformly [14]. 2.1. Modulation principle The basic ramp-comparison current controller with two-level topology given in [11] is extended for the multilevel inverter in this section. Fig. 3 shows the control strategy for one arm of the H-bridge of VSC. The shunt current ish is compared with the reference shunt current ishref . The error is passed through the controller. The switching function se so obtained is compared with the triangular carrier vtri of frequency fs and amplitude U. Switching function se is modulated with the carrier following For the purpose of analysis of multilevel inverter, carrier based PWM of switching function may be represented by a constant gain and xed delay. Consider the unipolar modulation of the switching function for one arm of the H-bridge as shown in Fig. 4. The ripple in the switching function is ignored. Let us assume that there is a nite error in the current tracking. This assumption is valid for the ramp-comparison control method. The carrier frequency is considered to be signicantly high so that the switching function se (t) is considered constant and equal to S for one switching time period. From Fig. 4 it can be shown [15] that the instantaneous average output over one switching period (uav ) is proportional to the ratio of the control voltage S and amplitude U of the triangular carrier vtri as uav = kM S = kc S U (1)

where, kM is a constant that depends upon the logic levels of the inverter and is equal to 1/2 in the present case. Therefore, input to output relation for one arm of the H-bridge in (1) is a simple gain kc = 1/(2U) for the components of se (t) whose frequency is much smaller than the carrier frequency. The output voltage levels of all the 2N arms of N, H-bridges are additive, although the switching pulses are phase-shifted and have the

Fig. 3. Ramp-comparison control for one arm of the H-bridge of VSC.

Fig. 4. Unipolar modulation of one arm of H-bridge of VSC.

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switching harmonic cancellation property [14]. Therefore, the net gain achieved between input switching function se (t) and the total output of multilevel modulator is 2N kc = N/U. For Note that the seven-level inverter, N = 3 and 2N kc = 3/U. dc voltage Vdc is considered as the multiplier of output of the modulator, considering uc to represent the normalized output of multilevel modulator. Now K = (1/U) is considered as the gain of the modulator. The factor N is multiplied with Vdc and kept with the model of the system, shown in the next section. From the above analysis it is clear that if the amplitude of the carrier signal increases, the modulator gain K decreases. The average switching delay due to the PWM may be approximated by a rst order lag with the time constant equal to half the effective switchig period, i.e., Ts /2(n 1) where Ts is the carrier time period. Multilevel modulation using phase-shifted multicarrier unipolar PWM reduces the time constant by factor (n 1) that results in improved dynamic performance. Combining the gain and delay of the multilevel modulator the following relation between input (se ) and output (uc ) of the modulator may be written in s-domain as GM (s) = K uc (s) = se (s) 1 + (s(Ts /2(n 1))) (2)

Fig. 5. Block diagram of the shunt compensated distribution system in current control mode using multilevel modulator.

where, L2 = Lf L + Ll Lf + Ll L and eq A= (Rf L + Rf Ll + RLl ) (Lf R LRf ) Ll , Lf (RLl Rl L) (RLf + Rl Lf + LRl ) (L + Ll )mVdc N LmVdc N

b1 =

b2 =

2.3. DSTATCOM model Consider the per-phase equivalent of a distribution system as shown in Fig. 1. The load is supplied from voltage source vs through the feeder with impedance (R, L). Let the nominal linear load be represented by (Rl , Ll ). The DSTATCOM consists of H-bridge VSCs. Each of the switches Sw1 to Sw4 consists of a power semiconductor device (e.g., IGBT) and an anti-parallel diode. The dc-link voltage Vdc across the dc capacitor Cdc is common to all the H-bridges. The output voltages of H-bridges are cascaded through the secondary of the transformers T1 , T2 and T3 . Resistor Rf represents the load dependent loss equivalent of the transformer. Lf is the combined leakage inductance of the cascaded transformers. The PCC voltage is denoted by vt . The currents owing through the different branches at PCC are denoted as: the source current is , the load current il , and the current injected in shunt branch is ish . The net output voltage cascaded through the secondary sides of the transformer is uc mVdc N, where uc = 1, 2/3, 1/3, 0, +1/3, +2/3, +1 is the switching action for seven-level inverter, m is the transformer voltage ratio and N = 3. Similarly the switching action for velevel inverter can be dened as uc = 1, 1/2, 0, +1/2, +1 with N = 2. The DSTATCOM contains two control loopsone for the current and the other for the dc-link voltage (Vdc ). The two loops are controlled separately. The current control loop is separated from the dc voltage control loop as the latter is much slower. Therefore, the dc voltage is assumed to be constant for the purpose of model derivation. Choosing a state vector as T x = [ ish il ] , the following state space equation is obtained L2 x = Ax + b1 vs + b2 uc eq (3)

Fig. 5 shows the block diagram of a multilevel rampcomparison control of a DSTATCOM compensated system. The non-linear component of the load is represented by a disturbance d and added to the nominal load current. Reference shunt current ishref is derived from the net load current ild after subtracting the reference source current isref . Calculation of isref and ishref is dicussed in Section 3. The resultant closed loop system is in the conguration of the output feedback switched linear system. 2.4. Switching ripple Fixed frequency switching condition for two-level inverter has been recently obtained for the carrier based modulation of a sliding mode controlled system [16]. In this section the concept of switching transition used in [16] is extended to determine the amplitude of switching ripples for multilevel inverter modulation used for current control application. Proper modulation of multilevel inverter requires a smooth switching function se (t) as shown in Fig. 4. However, the control signal uc contains high frequency pulses and this leads to the switching ripple in both shunt current ish and load current il . However, the reference isref (see Fig. 5), being a computed quantity, is free from switching ripples [8,9]. Therefore, the net ripple in the switching function se (t) is mainly due to the shunt current ish and a small component due to the load current il . The contribution due to the non-linear load is neglected. The magnitude of peakpeak switching pulses is 2/(n 1), i.e., equal to 1/3 for seven-level inverter (see Fig. 2). It is known from the spectrum of phase-shifted unipolar SPWM [14] that the output uc for n-level cascaded inverter carries component at the fundamental frequency and switching components at the frequency (n 1)fs and its multiples with side bands centered around these frequencies. Therefore, the PWM output uc consists of two components, i.e., the fundamental component ucf and the switching component uco . The fundamental component ucf is the desired signal used for the tracking of the reference

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input whereas the switching component uco is ltered and propagated through the system and controller, and combined with the switching function se . Here the approximate analysis is done to determine the ripple present in the switching function se . Assuming the square shape pulses for the switching component uco with the amplitude 1/(n 1), i.e., equal to 1/6 for seven-level inverter. The following Fourier series may be written for uco as uco (t) = 4 (n 1)
p=1(2)

1 sin(ps (n 1)t) p

Fig. 6. Intersection of switching function with the carrier for seven-level inverter.

(4) show only for one carrier. Let 2U be the peakpeak magnitude and Ts be the time period of the carrier. Then the time period of ripple will be Ts /(n 1). In order that the slope of the carrier to be greater than the slope of the ripple in the switching function the following condition must be satised 2Sr U 2U < Sr < Ts /2(n 1) Ts /2 n1 (8)

The following expression for the ripples in the switching function can be obtained using linear system theory as sr (t) = 4 (n 1)
p=1(2)

1 k |Gt (jps (n 1))| p (5)

sin(ps (n 1)t + )

where, Gt (s) = [Gf2 (s) Gf1 (s)]Gc (s) and = tan1 {Im[Gt (jps (n 1))]/(Re[Gt (jps (n 1))])}. The transfer functions are dened as follows, Gf1 (s) = ish (s)/uc (s) and Gf2 (s) = il (s)/uc (s) are obtained from (3) with vs (s) = 0, and Gc (s) is the transfer function of the controller. k is the feedforward gain and s is the carrier frequency in rad/s. Peak of the switchig ripple occurs at the positive to negative transition of the square switching pulses, i.e., at t = /(s (n 1)). Therefore, the peak value of sr may be obtained from (5) as Sr = 4 (n 1)
p=1(2)

Keeping the inequality factor of 75% in (8) to have clean intersection in Fig. 6 and substituting (7) into (8), following expression of feedforward gain is derived. k= 16
p=1(2) (1/p)Im[Gt (jps (n 1))]

3U

(9)

1 k |Gt (jps (n 1))| sin() p

(6)

It is noted from the expression of Gt (s) that the maximum ripple amplitude from (7) is obtained for lightly loaded condition. Therefore, the calculation of k should be done for no-load condition in case the load follows the wide variations. This ensures smooth modulation at xed switching frequency for all possible loadings. 2.6. P + resonant controllers As shown in Section 2.2 the multilevel modulation algorithm using phase-shifted PWM offers a nite gain at the fundamental frequency. This leads to error in tracking fundamental component of current reference. It is proposed to pass the error through a proportional plus resonant controller as shown in Fig. 5. The resonant controller is tuned close to the fundamental frequency to minimize the error at this frequency [12,13]. The controller structure in the frequency domain is written as kGc (s) = 2Ki c s se (s) =k 1+ 2 2 e(s) s + 2c s + o (10)

Using trigonometric property, sin() = Im[Gt (jps (n 1))]/|(Gt (jps (n 1)))|, (6) is reduced to 4 Sr = (n 1)
p=1(2)

k Im[Gt (jps (n 1))] p

(7)

Since the system Gt (s) has low pass characteristics the shifting of switching component by (n 1) times switching frequency and reduction of pulse amplitude by 1/(n 1) times in (7) signicantly reduces the switching ripple in se (t). The feedforward gain k is selected on the basis of maximum ripple condition discussed below. 2.5. Calculation of feedforward gain The feedforward gain k should be high for improvement in both the steady state and dynamic behavior. But increase in gain also increases the ripple magnitude in the switching function se (t). Therefore, for proper modulation at xed switching frequency the amplitude and slope of the ripple should be less than the amplitude and slope of the carrier [11,17]. If this condition is not satised inverter modulation will follow higher switching frequency than the carrier frequency due to the multiple intersections. Fig. 6 shows the intersection of the switching function se (t) with the carrier vtri (t). The gure is the enlarge view of Fig. 2,

where k and Ki are the feedforward gain and integral gain, respectively. o is the resonant frequency and c represents the damping factor for the ideal resonant controller. The positive value of c introduces high gain for the band of frequencies around the resonant frequency o . Fig. 7 shows the frequency response characteristics of the controller Gc (s) for Ki = 20.0, c = 2.513 rad/s and o = 314 rad/s (for fundamental frequency of 50 Hz). The resonant frequency o may be continuously updated using the current estimate of the fundamental frequency. The controller provides high gain around the resonant frequency o to compensate the error component at the fundamental frequency. The phase characteristics at the fundamental frequency suffer 180

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Fig. 8. Open loop Bode plot of the current control loop. Fig. 7. Frequency response of the proportional plus resonant controller.

shift. This deteriorates the transient performance and makes the convergence sluggish at this frequency. The analysis of the closed loop system may now be investigated using linear theory. Example 1. Consider the system parameters as given in Table 1. Let the amplitude of the triangular carrier (U) be equal to 0.005 kV. Therefore, the modulator gain K = 1/U = 1 . Consider a seven-level modulation with a carrier 200.0 kV frequency of 1 kHz. The switching delay for the seven-level inverter is Ts /12 = 0.0000833 s. The gain calculation from (9) yields k = 0.58 kV/kA. The transfer function of each block of the system shown in Fig. 5 is obtained as, GM (s) from (2), Gf1 (s) from (3) and kGc (s) from (9) and (10). Combining all the blocks, Bode plot of the current control loop of DSTATCOM is shown in Fig. 8, assuming constant gain K for the multilevel modulator. In actual the gain of the modulator decreases with the increase in frequency of the reference shunt current. As seen from Fig. 8 control loop has the bandwidth of arroud 2.5 kHz. Gain and phase margins are innity and 42 , respectively, showing closed loop stability. System has higher gain near fundamental frequency of 50.0 Hz reducing any tracking error at this frequency. It may be noted that for seven-level inverter, the ripple magnitude decreases signicantly. This leads higher value of gain k from (9), as compared to the inverters with ve- or threelevels. Also the net delay is very small, i.e., 0.000083 s. The two factors lead to the higher bandwidth and better trackTable 1 System parameters used for simulation studies Parameters Source voltage vs , frequency fo Feeder resistance and inductance R, L Nominal load Rl , Ll Cascaded transformers Ti1 , Ti2 , Ti3 ; i = a, b, c Net shunt resistance and inductance Rf , Lf Common dc-link capacitor Cdc and reference voltage Vdc Numerical value 11.0 kV (LL) rms, 50 Hz 2.05 , 35.5 mH 102 , 392.6 mH 1 kV/3.67 kV, 180.0 kVA 2.24 , 39.0 mH 5000 F, 1.1 kV

ing characteristics as compared to the inverters with lower levels. 3. Multilevel DSTATCOM for three-phase distribution system The cascaded transformer H-bridge structure, shown in Fig. 1, is now used for the three-phase four-wire distribution system shown in Fig. 9. The DSTATCOM is realized by three seven-level cascaded transformer multilevel inverters. All the units of three-phases are supplied from the common dc capacitor Cdc . The single-phase model obtained in (3) is also valid for each phase of the three-phase four-wire distribution system [8,9]. Therefore, the results derived in Section 2 are applicable for three-phase DSTATCOM on per-phase basis. 3.1. Reference current generation Refer to Fig. 5; the current control requires the reference for shunt current ishref for each phase. The reference current

Fig. 9. Shunt compensation using three cascaded transformer multilevel inverter supplied from common dc storage capacitor.

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generation in this paper follows the method described in [8,9]. For an independent control of shunt currents in all the threephases in Fig. 9, the references for shunt currents are determined on-line using the following equations vta v0 ishrefa = ilda isrefa = ilda (plav + pdc ) vtb v0 (11) ishrefb = ildb isrefb = ildb (plav + pdc ) vtc v0 ishrefc = ildc isrefc = ildc (plav + pdc ) where ishrefk , isrefk , ildk and vtk , k = a, b, c, respectively, are the reference shunt current, reference source current, load current and PCC terminal voltages for the three phases and 1 v0 = vt and = v2 v 2 t 0 3
=a,b,c =a,b,c

given as e = Vdcref Vdcav 3.2. Three-phase simulation Consider the shunt compensated distribution system shown in Fig. 9. The following example illustrates the performance of a proposed compensator with multicarrier phase shifted unipolar PWM discussed in Section 2.1, forward gain calculated from (9) and using P + resonant controller (10). The reference shunt currents are derived from (11). Example 2. The parameters of the system are given in the Table 1. The unbalanced linear load is given by Rla = 102.0 , Lla = 392.6 mH, Rlc = 80.0 , Rlb = 300.0 , (13)

Llb = 520.0 mH,

Llc = 200.0 mH

In (11) plav is the average load power (linear plus non-linear) that is obtained by a moving average lter using the continuous measurement of instantaneous power. Note that the PCC terminal voltages vtk used in (11) are the fundamental frequency components of the switching frequency contaminated terminal voltages that are extracted on-line from the measurement of the actual voltages [8,9]. Therefore, isrefk , in (11) are free from any switching ripples. The variable pdc in (11) is the power drawn from the ac system to replenish the loss caused by the DSTATCOM circuit. The main objective of pdc is to hold the average dc bus voltage Vdcav constant equal to Vdcref and hence the dc control loop is given by pdc = Kpdc e + Kidc e dt (12)

where Kpdc and Kidc are the proportional and integral gain for the dc control loop. The error e between the reference dc voltage and average dc voltage across the common dc-link capacitor is

In addition the load contains a three-phase diode rectier bridge supplying a load of 100 and 200 mH. The carrier frequency is chosen as 1.0 kHz. P + resonant controller has same parameter as considered in Section 2.6. Feedforward gain k = 0.58 kV/kA is used as calculated in Example 1. The reference voltage for the dc capacitor is kept at 1.1 kV and PI parameters of dc voltage control loop (12) are chosen as Kpdc = 0.05 and Kidc = 0.2 s1 . The simulation is performed in the PSCAD/EMTDC simulation package (version 3.0.7). The THD in the source current for uncompensated system is 13.3%. Fig. 10(a) shows the harmonic spectrum of the source current showing the presence of dominant 5th and 7th order harmonics. It is desired to bring down the THD in source current to acceptable limit with good tracking of fundamental component for reactive power compensation and balancing the three-phase source currents. The performance of the seven-level inverter based DSTATCOM is described below. Compensator is connected after 5cycles, i.e., at 0.1 s. Fig. 11 shows the three-phase source currents which is unbalanced with high THD before 0.1 s. The source currents get balanced after the compensator is connected and

Fig. 10. Harmonic spectrum of source current, base frequency (50 Hz) (a) uncompensated system and (b) compensated system.

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Fig. 14. Tracking of dc-link voltage. Fig. 11. Three-phase source currents, DSTATCOM connected at 0.1 s.

resonant action of controller at the fundamental frequency. The maximum steady state error for tracking of fundamental component is 1.0 A (rms) for the variation of fundamental frequency of 2% from 50 Hz. Better tracking is due to the band resonant nature of the controller (10). Fig. 14 shows the PI controller performance for the dc capacitor voltage control. The dc-link voltage settles near to the reference of 1.1 kV with initial peak overshoot of 45%. The switching device rating of IGBT required for inverter is given in Table 2. Example 3. In this example, the power loss is estimated for the cascaded transformer based DSATACOM discussed in Example 2. The compensator rating is assumed to be 540 kVA for each phase. Transformer losses are charecterized by xed core loss and load dependent copper loss. Core loss is assigned 0.5% and the copper loss is represented by a resistance of 2.24 (equivalent to 1% per transformer given in Table 1). In order to estimate inverter losses, the data of the switching devices, i.e., IGBT and anti-parallel diode given in Table 2 are considered. Inverter losses are also divided into two categories, i.e., conduction loss and switching loss in both the devices [18]. Conduction loss is calculated using the actual currents owing through the IGBT and anti-parallel diodes during the conduction period of the devices. Switching loss is estimated from the inverter full load conditions and for xed switching frequency of 1.0 kHz [15,18]. Switching loss comprises of IGBT turn-on plus turnoff losses and diode reverse recovery loss. Loss estimation is done for single cell only and the total estimation is obtained by multiplication with the number of cascaded units. This is the advantage of the proposed switching scheme for the cascaded transformer topology as the power is distributed equally and all the units are stressed uniformly. Fig. 15 shows the transformer loss, inverter loss and total power loss in the three-phase DSTATCOM circuit. After an initial transient the steady state power loss settles to about 35.0 kW. About 75% of total loss occurs in the
Table 2 Semiconductor device ratings considered for power loss estimation Parameters IGBT collectoremitter voltage and collector current Turn-on and turn-off time Collectoremitter saturation voltage Diode forward voltage, reverse recovery current, reverse recovery time Numerical value 1.7 kV, 250 A 0.55 s, 1.3 s 3.0 V 2.5 V, 230 A, 0.15 s

Fig. 12. In-phase source current with terminal voltage for phase-a.

the THD is improved to 3.2% whereas the load current THD is 20.5%. The harmonic spectrum of the compensated source current is shown in Fig. 10(b) showing the attenuation of the dominant harmonics. Figure also shows the harmonic cancellation of switching components up to 6 kHz due to the multi-carrier unipolar PWM. The small group of switching harmonics is visible with the center frequency of 120th harmonic. All the switches operate at switching frequency of 1.0 kHz uniformly. It may be noted that if the feedforward gain k is chosen higher than calculated from (9) the switches enters into the chaotic operation due to multiple crossings and leads to higher switching frequency than 1.0 kHz. Fig. 12 shows the source current in-phase with PCC voltage for phase-a under the steady state condition. This shows that the DSTATCOM not only compensates the harmonic components and unbalancing of load but also provides near unity power factor. Shunt current tracking performance for phase-a is shown in Fig. 13. The controller tracks the reference shunt current after the initial transient of about 2-cycles. The reason for transient is the

Fig. 13. Tracking of reference shunt current for phase-a.

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Fig. 15. Power loss in the DSTATCOM circuit.

Fig. 16. (a) Load current and (b) source current.

transformer and that is dissipated by the cooling arrangement in the transformer itself. Separate cooling may be done for the rest 25% losses in the inverter circuit. The maximum supplied load is 3.0 MVA. 4. Experimental results In this section the experimental verication of multilevel modulation and control proposed in Section 2 is obtained through the laboratory model of a single phase, ve-level inverter based DSTATCOM. A LabVIEW FPGA based digital processor that runs on recongurable I/O NI 7831R is used for the modulation of a multilevel inverter. This digital processor also incorporates dead time in the gating signal for the complimentary switches of the same arm of the H-bridges. The analog input signals are sampled at the rate of 100 kHz. A proportional plus resonant controller is implemented using NI LabVIEW RT programming that carries out oating point operation required for the controller implementation. Two H-bridges of the ve-level inverter are implemented using two arms of the Mitsubishi make Intelligent Power Modules (IPMs) PM50CSD120. The detail of IPM is available in [18]. Table 3 shows the data considered for the implementation of the experimental model. Equivalent circuit of the model is same as shown in Fig. 1, except that the DSTATCOM consists of two cascaded transformers and inverters units. Load connected to the distribution system model consists of linear load and non-linear load. Linear load parameters are Rl = 50 , Ll = 10 mH and non-linear load contains a single-phase diode rectier bridge supplying a resistive load of 25 in parallel with 220 F capacitor. This diode rectier bridge is interfaced to the PCC through an inductance of 10 mH. The THD of uncompensated source current is found to be 9.2%. DSTATCOM is connected with common dc-link voltage controlled through a separate rectier unit supplied from an external
Table 3 System parameters used for experimental studies Parameters Source voltage vs , frequency fo Feeder resistance and inductance R, L Cascaded transformers T1 , T2 Net shunt resistance and inductance Rf , Lf Common dc-link capacitor Cdc and reference voltage Vdc Numerical value 50.0 V rms, 50 Hz 6.0 , 30.0 mH 110/220 V, 500 VA 10.0 , 10.0 mH 2200 F, 50.0 V

source. Fig. 5 represents the equivalent block diagram of this system. State-space model (3) can be determined using data given in Table 3 and load represented as above. Gain calculation using (9) yields k = 21.0 V/A for carrier amplitide U = 5.0 V and controller dened in Section 2.6. The controller (10) is implemented with the gain k calculated as above in the digital processor. Refer to Fig. 5, sinusoidal reference source current isref is generated in the digital processor that is phase locked with the PCC voltage vt . Fig. 16 shows the load current and the compensated source current when the ve-level DSTATCOM is operated using the above modulation and control. The THD of this compensated source current is 3.8% and the THD of load current shown in Fig. 16 is 25%. The currents are shown at the scale of (1 V:2.5 A). In-phase source current with the terminal voltage is shown in Fig. 17. Voltages are shown at the scale of (1 V:50 V). Smooth modulation is obtained at the calculated value of the gain k = 21.0 V/A. The gating signals for the switches Sw1 and Sw3 of rst H-bridge, at xed switching frequency of 1 kHz is shown in Fig. 18. Above this value of gain multiple crossings are observed as shown in Fig. 19 at the gain of k = 30.0 V/A. The three-level output voltages of the two H-bridges are shown in Fig. 20. These voltages, when added, provide ve-level output as shown in Fig. 20. These individual outputs are added at the secondary of the two cascaded transformers leading to ve-level output. Fig. 21 shows the injected shunt current and tracking error. The use of proportional plus resonant controller almost eliminates the tracking error at the fundamental frequency. Fig. 22 shows the shunt current and tracking error when DSTATCOM is operated without resonant controller. It is clear from Fig. 22 that the shunt cur-

Fig. 17. Source current and terminal voltage.

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Fig. 18. Gating signal for switches Sw1 and Sw3 .

Fig. 22. (a) Shunt current and (b) tracking error, without resonant controller.

rent tracking has signicant error in the absence of the resonant controller. 5. Conclusions Cascaded transformer multilevel topology is well suited to the current control of DSTATCOM, as this requires controlling only a common dc storage capacitor. Use of multilevel inverter signicantly reduces the voltage stress in capacitors and semiconductor devices. The cascaded topology with phase shifted multicarrier unipolar PWM increases the net switching frequency and reduces the ripple magnitude leading to higher feedforward gain and hence the bandwidth. The choice of feedforward gain using derived expression leads to the smooth modulation at the xed switching frequency. It is shown through the simulation results that the proposed control improves THD, balances the source currents with good tracking of fundamental component. Power losses are easier to estimate due the xed switching frequency operation and equal power distribution among the cascaded units of DSTATCOM. Experimental results validate the multilevel modulation and control proposed in this paper. References
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Fig. 19. Multiple crossings of gating signals at higher gain.

Fig. 20. Individual three-level outputs of each H-bridge leading to ve-level output when added.

Fig. 21. (a) Shunt current and (b) tracking error, with resonant controller.

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