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Digital Design:

An Embedded Systems Approach Using VHDL

Digital Design: An Embedded Systems Approach Usin g VHDL Chapter 7 Processor Basics Portions of this
Digital Design: An Embedded Systems Approach Usin g VHDL Chapter 7 Processor Basics Portions of this
Digital Design: An Embedded Systems Approach Usin g VHDL Chapter 7 Processor Basics Portions of this
Digital Design: An Embedded Systems Approach Usin g VHDL Chapter 7 Processor Basics Portions of this

Chapter 7 Processor Basics

Systems Approach Usin g VHDL Chapter 7 Processor Basics Portions of this work are from the

Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using VHDL, by Peter J. Ashenden, published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.

VHDL

VHDL Embedded Com p uters A computer as part of a digital system Performs processing to
VHDL Embedded Com p uters A computer as part of a digital system Performs processing to

Embedded Computers

VHDL Embedded Com p uters A computer as part of a digital system Performs processing to

A computer as part of a digital system

Performs processing to implement or control the system’s function

Components

Processor core Instruction and data memory Input, output, and input/output controllers

For interacting with the physical world

Accelerators

High-performance circuit for specialized functions

Interconnecting buses

circuit for specialized functions Interc o nnectin g bu ses Digital Design — Chapter 7 —

Digital Design — Chapter 7 — Processor Basics

2

VHDL

VHDL Memor y Org anization Von Neumann architecture Single memory for instructions and data H arvar
VHDL Memor y Org anization Von Neumann architecture Single memory for instructions and data H arvar

Memory Organization

VHDL Memor y Org anization Von Neumann architecture Single memory for instructions and data H arvar

Von Neumann architecture

Single memory for instructions and data

Harvard architecture

Separate instruction and data memories Most common in embedded systems

CPU

Instruction

Data

Accelerator

 

memory

memory

 
Data A cce ler ato r   memor y memor y   Input Output I/O …
Data A cce ler ato r   memor y memor y   Input Output I/O …
Data A cce ler ato r   memor y memor y   Input Output I/O …
Data A cce ler ato r   memor y memor y   Input Output I/O …
Data A cce ler ato r   memor y memor y   Input Output I/O …
Data A cce ler ato r   memor y memor y   Input Output I/O …
Data A cce ler ato r   memor y memor y   Input Output I/O …
Data A cce ler ato r   memor y memor y   Input Output I/O …

Input

Output

I/O

controller

controller

controller

   
   
   
r   memor y memor y   Input Output I/O … controller controller controller    
… controller controller controller     Digital Design — Chapter 7 — Processor Basics 3

Digital Design — Chapter 7 — Processor Basics

3

VHDL

VHDL Bus Org anization Sing le bus for low-cost low- p erformance systems Multi p le
VHDL Bus Org anization Sing le bus for low-cost low- p erformance systems Multi p le

Bus Organization

VHDL Bus Org anization Sing le bus for low-cost low- p erformance systems Multi p le

Single bus for low-cost low-performance systems Multiple buses for higher performance

Data Accelerator memory Instruction CPU memory Input Output I/O controller controller controller
Data
Accelerator
memory
Instruction
CPU
memory
Input
Output
I/O
controller
controller
controller
CPU memory Input Output I/O controller controller controller Digital Design — Chapter 7 — Processor Basics

Digital Design — Chapter 7 — Processor Basics

4

VHDL

VHDL Bus Org anization Traditional Bus Topology Digital Design — Chapter 7 — Processor Basics 5
VHDL Bus Org anization Traditional Bus Topology Digital Design — Chapter 7 — Processor Basics 5

Bus Organization

VHDL Bus Org anization Traditional Bus Topology Digital Design — Chapter 7 — Processor Basics 5

Traditional Bus Topology

VHDL Bus Org anization Traditional Bus Topology Digital Design — Chapter 7 — Processor Basics 5
VHDL Bus Org anization Traditional Bus Topology Digital Design — Chapter 7 — Processor Basics 5

Digital Design — Chapter 7 — Processor Basics

5

VHDL

VHDL Bus Org anization Typical Switch Fabric Topology Digital Design — Chapter 7 — Processor Basics
VHDL Bus Org anization Typical Switch Fabric Topology Digital Design — Chapter 7 — Processor Basics

Bus Organization

VHDL Bus Org anization Typical Switch Fabric Topology Digital Design — Chapter 7 — Processor Basics

Typical Switch Fabric Topology

VHDL Bus Org anization Typical Switch Fabric Topology Digital Design — Chapter 7 — Processor Basics
VHDL Bus Org anization Typical Switch Fabric Topology Digital Design — Chapter 7 — Processor Basics

Digital Design — Chapter 7 — Processor Basics

6

VHDL

VHDL Bus Org anization Altera’s System Interconnect Fabric Example Digital Design — Chapter 7 — Processor
VHDL Bus Org anization Altera’s System Interconnect Fabric Example Digital Design — Chapter 7 — Processor

Bus Organization

VHDL Bus Org anization Altera’s System Interconnect Fabric Example Digital Design — Chapter 7 — Processor

Altera’s System Interconnect Fabric Example

VHDL Bus Org anization Altera’s System Interconnect Fabric Example Digital Design — Chapter 7 — Processor

Digital Design — Chapter 7 — Processor Basics

VHDL Bus Org anization Altera’s System Interconnect Fabric Example Digital Design — Chapter 7 — Processor

7

VHDL

VHDL Bus Org anization Altera’s Memory-Mapped and Streaming System Interconnect Fabrics Digital Design — Chapter 7
VHDL Bus Org anization Altera’s Memory-Mapped and Streaming System Interconnect Fabrics Digital Design — Chapter 7

Bus Organization

VHDL Bus Org anization Altera’s Memory-Mapped and Streaming System Interconnect Fabrics Digital Design — Chapter 7

Altera’s Memory-Mapped and Streaming System Interconnect Fabrics

Digital Design — Chapter 7 — Processor Basics
Digital Design — Chapter 7 — Processor Basics

SRIO:

Serial RapidIO is a high- performance, point-to- point, packet-switched interconnect technology defined by the RapidIO Trade Association.

Full-duplex point-to-point links are established with single or multiple high- speed serial lanes (1x and 4x are currently defined), and industry-standard 8B/10B-encoded data transmission at signaling rates of 1.25, 2.50, or 3.125 Gbaud for peak bandwidth of up to 20 Gbps.

data transmission at signaling rates of 1.25, 2.50, or 3.125 Gbaud for peak bandwidth of up

8

VHDL

VHDL Micro p rocessors Single - chi p processor in a p acka g e External
VHDL Micro p rocessors Single - chi p processor in a p acka g e External

Microprocessors

VHDL Micro p rocessors Single - chi p processor in a p acka g e External

Single-chip processor in a package External connections to memory and I/O buses Most commonly seen in general purpose computers

E.g., Intel Pentium family, PowerPC, …

purpose computers E.g ., Intel Pentium family , PowerPC , … Digital Design — Chapter 7

Digital Design — Chapter 7 — Processor Basics

9

VHDL

VHDL Microcontrollers Sing le chi p combinin g Processor A small amount of instruction/data memor y
VHDL Microcontrollers Sing le chi p combinin g Processor A small amount of instruction/data memor y

Microcontrollers

VHDL Microcontrollers Sing le chi p combinin g Processor A small amount of instruction/data memor y

Single chip combining

Processor A small amount of instruction/data memory I/O controllers

Microcontroller families

Same processor, varying memory and I/O

8-bit microcontrollers

Operate on 8-bit data Low cost, low performance

16-bit and 32-bit microcontrollers

Higher performance

16-bit and 32-bit microcontrollers Higher performance Digital Design — Chapter 7 — Processor Basics N X

Digital Design — Chapter 7 — Processor Basics

NXPs 50-MHz ARM Cortex- M0-based LPC1100 microcontroller family represents the latest 32-bit challenge to 8- and 16-bit processors. The parts are available now with prices starting at 65 to 95 cents

(10,000).

CoreMark Benchmark measures 40 to 50% better

code density for the LPC1100 than that of 8- and 16-bit

microcontrollers.

10

VHDL

VHDL Processor Cores Processor as a component in an FPGA or ASIC I n FPGA ,
VHDL Processor Cores Processor as a component in an FPGA or ASIC I n FPGA ,

Processor Cores

VHDL Processor Cores Processor as a component in an FPGA or ASIC I n FPGA ,

Processor as a component in an FPGA or ASIC In FPGA, can be a fixed-function block

E.g., PowerPC cores in some Xilinx FPGAs

Or can be a soft core

Implemented using programmable resources E.g., Xilinx MicroBlaze, Altera Nios-II

In ASIC, provided as an IP block

E.g., ARM, PowerPC, MIPS, Tensilica cores Can be customized for an application

MIPS, Tensilica cores Can be customized for an application Digital Design — Chapter 7 — Processor

Digital Design — Chapter 7 — Processor Basics

11

VHDL

VHDL Di g ital Si g nal Processors DSPs are processors optimized for signal processing operations
VHDL Di g ital Si g nal Processors DSPs are processors optimized for signal processing operations

Digital Signal Processors

VHDL Di g ital Si g nal Processors DSPs are processors optimized for signal processing operations

DSPs are processors optimized for signal processing operations

E.g., audio, video, sensor data; wireless communication

Often combined with a conventional core for processing other data

Heterogeneous multiprocessor

core for processing other data Heterogeneous multiprocessor Digital Design — Chapter 7 — Processor Basics 12

Digital Design — Chapter 7 — Processor Basics

12

VHDL

VHDL Instruction Sets A processor executes a program A sequence of instructions, each performing a small
VHDL Instruction Sets A processor executes a program A sequence of instructions, each performing a small

Instruction Sets

VHDL Instruction Sets A processor executes a program A sequence of instructions, each performing a small

A processor executes a program

A sequence of instructions, each performing a small step of a computation

Instruction set: the repertoire of available instructions

Different processor types have different instruction sets

How are new instructions chosen to be

added to Instruction Set?

High-level languages: more abstract

E.g., C, C++, Ada, Java Translated to processor instructions by a compiler

Java Translated to processor instructions by a compiler CPU time _ IC =× ( CPI execution

CPU time

_

IC

(

CPI

execution

+

Memory s t a ll cycl es

_

_

Instruction

Digital Design — Chapter 7 — Processor Basics

Clock period

)_

×

13

VHDL

VHDL Instruction Execution Instructions are encoded in binary Stored in the instruction memory A processor executes
VHDL Instruction Execution Instructions are encoded in binary Stored in the instruction memory A processor executes

Instruction Execution

VHDL Instruction Execution Instructions are encoded in binary Stored in the instruction memory A processor executes

Instructions are encoded in binary

Stored in the instruction memory

A processor executes a program by repeatedly

Fetching the next instruction Decoding it to work out what to do Executing the operation

Program counter (PC)

Register in the processor holding the address of the next instruction

in the processor holding the add ress o f the next in st r uct ion

Digital Design — Chapter 7 — Processor Basics

14

VHDL

VHDL Data and Endian-ness Instructions o p erate on data from the data memor y Byte:
VHDL Data and Endian-ness Instructions o p erate on data from the data memor y Byte:

Data and Endian-ness

VHDL Data and Endian-ness Instructions o p erate on data from the data memor y Byte:

Instructions operate on data from the data memory Byte: 8-bit data

Data memory is usually byte addressed

16-bit, 32-bit, 64-bit words of data

Little endian

Big endian

 

0

 

8-bit data

   
   
 
   
   
 

m

least sig. byte

 

m + 1

most sig. byte

16-bit data

Little endian

   
 
     
     
 
     
     
 

LSB=lowest address

   

least sig. byte

 

Intel x86

 

n

   
 

n

+ 1

 

32-bit data

 
 

n

+ 2

 

n

+ 3

most si

g.

b

y

te

 

0

   
 
 
 
 
 

m

i

most s g.

b

yte

 

m + 1

least sig. byte

 
   
   
 
   
   

n

most sig. byte

 

n

+ 1

 

n

+ 2

 

n

+ 3

least sig. byte

  n + 2   n + 3 least sig. b yte Digital Design — Chapter

Digital Design — Chapter 7 — Processor Basics

8-bit data 16-bit data
8-bit data
16-bit data

Big endian

MSB=lowest address

PowerPC

32-bit data

15

VHDL

VHDL T he Gumnut Core A small 8- bit soft core Can be used in FPGA
VHDL T he Gumnut Core A small 8- bit soft core Can be used in FPGA

The Gumnut Core

VHDL T he Gumnut Core A small 8- bit soft core Can be used in FPGA

A small 8-bit soft core

Can be used in FPGA designs

Instruction set illustrates features typical of 8- bit cores and processors in general Programs written in assembly language

Each processor instruction written explicitly Translated to binary representation by an assembler

Resources available on companions web site

an assembler R esources ava il a bl e on compan i ons we b s

Digital Design — Chapter 7 — Processor Basics

16

VHDL

VHDL Gumnut Stora ge How many registers should you encode for in the instruction? Two? Three?
VHDL Gumnut Stora ge How many registers should you encode for in the instruction? Two? Three?

Gumnut Storage

VHDL Gumnut Stora ge How many registers should you encode for in the instruction? Two? Three?

How many registers should you encode for in the instruction? Two? Three?

How many registers should there be?

General-Purpose Registers

r0

0

 

r1

 

r2

 

r3

 

r4

 

r5

 

r6

 

r

7

 
 

Data Memory (256 × 8-bit, 8-bit addresses)

 

0

   

1

 

2

 

254

 

255

 

Condition Code Registers

C

Z

254   255   Condition Code Registers C Z Carry Zero Program C ounter PC Instruction

254   255   Condition Code Registers C Z Carry Zero Program C ounter PC Instruction

Carry

Zero

Program Counter

PC

Condition Code Registers C Z Carry Zero Program C ounter PC Instruction Memory (4K × 18-bit,

Instruction Memory (4K × 18-bit, 12-bit addresses)

0

1

2

4094

4095

Instruction Memory (4K × 18-bit, 12-bit addresses) 0 1 2 4094 4095 Digital Design — Chapter
Instruction Memory (4K × 18-bit, 12-bit addresses) 0 1 2 4094 4095 Digital Design — Chapter
Instruction Memory (4K × 18-bit, 12-bit addresses) 0 1 2 4094 4095 Digital Design — Chapter
Instruction Memory (4K × 18-bit, 12-bit addresses) 0 1 2 4094 4095 Digital Design — Chapter
Instruction Memory (4K × 18-bit, 12-bit addresses) 0 1 2 4094 4095 Digital Design — Chapter
Instruction Memory (4K × 18-bit, 12-bit addresses) 0 1 2 4094 4095 Digital Design — Chapter
Instruction Memory (4K × 18-bit, 12-bit addresses) 0 1 2 4094 4095 Digital Design — Chapter

Digital Design — Chapter 7 — Processor Basics

17

VHDL

VHDL Arithmetic Instructions Operate on register data and put result in a register add , addc
VHDL Arithmetic Instructions Operate on register data and put result in a register add , addc

Arithmetic Instructions

VHDL Arithmetic Instructions Operate on register data and put result in a register add , addc

Operate on register data and put result in a register

add, addc, sub, subc Can have immediate value operand

Condition codes

Z: 1 if result is zero, 0 if result is non-zero C: carry out of add/addc, borrow out of sub/subc

addc and subc include C bit in operation

borrow out of sub/subc addc and subc include C bit in op eration Digital Design —

Digital Design — Chapter 7 — Processor Basics

18

VHDL

VHDL Arithmetic Instructions Examples add r3, r4, r1 a dd r5, r1, 2 sub r4, r4,
VHDL Arithmetic Instructions Examples add r3, r4, r1 a dd r5, r1, 2 sub r4, r4,

Arithmetic Instructions

VHDL Arithmetic Instructions Examples add r3, r4, r1 a dd r5, r1, 2 sub r4, r4,

Examples

add

r3, r4, r1

add

r5, r1, 2

sub

r4, r4, 1

Evaluate 2x + 1; x in r3, result in r4

add

r4, r4, r3

; double x

add

r4, r4, 1

; then add 1

r4 , r4 , r3 ; double x add r4, r4, 1 ; then add 1

Digital Design — Chapter 7 — Processor Basics

19

VHDL

VHDL Lo g ical Instructions O p erate on re g ister data and p ut
VHDL Lo g ical Instructions O p erate on re g ister data and p ut

Logical Instructions

VHDL Lo g ical Instructions O p erate on re g ister data and p ut

Operate on register data and put result in a register

and, or, xor, mask (and not) Operate bitwise on 8-bit operands Can have immediate value operand

Condition codes

Z: 1 if result is zero, 0 if result is non-zero C: always 0

d es Z: 1 if result is zero, 0 if result is non-zero C: always 0

Digital Design — Chapter 7 — Processor Basics

20

VHDL

VHDL Lo g ical Instructions Exam p les and r3, r4, r5 or r1, r1, 0x80
VHDL Lo g ical Instructions Exam p les and r3, r4, r5 or r1, r1, 0x80

Logical Instructions

VHDL Lo g ical Instructions Exam p les and r3, r4, r5 or r1, r1, 0x80

Examples

and

r3, r4, r5

or

r1, r1, 0x80

; set r1(7)

xor

r5, r5, 0xFF

; invert r5

Set Z if least-significant 4 bits of r2 are 0101

and

r1, r2, 0x0F ; clear high bits

sub

r0, r1, 0x05 ; compare with 0101

0x0F ; clear high bits sub r0, r1, 0x05 ; compare with 0101 Digital Design —

Digital Design — Chapter 7 — Processor Basics

21

VHDL

VHDL Shift Instructions Lo g ical shift/rotate re g ister data and put result in a
VHDL Shift Instructions Lo g ical shift/rotate re g ister data and put result in a

Shift Instructions

VHDL Shift Instructions Lo g ical shift/rotate re g ister data and put result in a

Logical shift/rotate register data and put result in a register

shl, shr, rol, ror Count specified as a literal operand

Condition codes

Z: 1 if result is zero, 0 if result is non-zero C: the value of the last bit shifted/rotated past the end of the byte

of the last bit shifted/rotated pas t th e en d of th e byte Digital

Digital Design — Chapter 7 — Processor Basics

22

VHDL

VHDL Shift Instructions Exam p les shl r4, r1, 3 ror r2, r2, 4 Multiply r4
VHDL Shift Instructions Exam p les shl r4, r1, 3 ror r2, r2, 4 Multiply r4

Shift Instructions

VHDL Shift Instructions Exam p les shl r4, r1, 3 ror r2, r2, 4 Multiply r4

Examples

shl

r4, r1, 3

ror

r2, r2, 4

Multiply r4 by 8, ignoring overflow

shl

r4, r4, 3

Multiply r4 by 10, ignoring overflow

shl

r1, r4, 1

; multiply by 2

shl

r4, r4, 3

; multiply by 8

add

r4, r4, r1

by 2 shl r4, r4, 3 ; multiply by 8 add r4, r4, r1 Digital Design

Digital Design — Chapter 7 — Processor Basics

23

VHDL

VHDL Memor y Instructions T ransfer data between re g isters and data memory Compute address
VHDL Memor y Instructions T ransfer data between re g isters and data memory Compute address

Memory Instructions

VHDL Memor y Instructions T ransfer data between re g isters and data memory Compute address

Transfer data between registers and data memory

Compute address by adding an offset to a base register value

Load register from memory

ldm

r1, (r2)+5

Store from register to memory

stm

r1, (r4)-2

Use r0 if base address is 0

ldm

r3, 23 ldm

r3, (r0)+23

Condition codes not affected

is 0 ldm r3, 23 ≡ ldm r3, (r0)+23 Condition codes not affected Digital Design —

Digital Design — Chapter 7 — Processor Basics

24

VHDL

VHDL Memor y Instructions Increment a 16- bit integer in memory Little-endian: address of lsb in
VHDL Memor y Instructions Increment a 16- bit integer in memory Little-endian: address of lsb in

Memory Instructions

VHDL Memor y Instructions Increment a 16- bit integer in memory Little-endian: address of lsb in

Increment a 16-bit integer in memory

Little-endian: address of lsb in r2, msb in next location

ldm

r1, (r2)

; increment lsb

add

r1, r1, 1

stm

r1, (r2)

ldm

r1, (r2)+1

; increment msb

addc r1, r1, 0

; with carry

stm

; increment msb addc r1, r1, 0 ; with carry stm r1, (r2)+1 Digital Design —

r1, (r2)+1

Digital Design — Chapter 7 — Processor Basics

25

VHDL

VHDL In put/Outp ut Instructions I/O controllers have registers that govern their operation Each has an
VHDL In put/Outp ut Instructions I/O controllers have registers that govern their operation Each has an

Input/Output Instructions

VHDL In put/Outp ut Instructions I/O controllers have registers that govern their operation Each has an

I/O controllers have registers that govern their operation

Each has an address, like data memor Gumnut has separate data and I/O address spaces

Input from I/O register

inp

r3, 157 inp

r3, (r0)+157

Output to I/O register

out

r3, (r7) out

r3, (r7)+0

Condition codes not affected Further examples in Chapter 8

Condition codes not affected Further exam ples in Chap ter 8 Digital Design — Chapter 7

Digital Design — Chapter 7 — Processor Basics

26

VHDL

VHDL Branch Instructions Programs can evaluate conditions and take alternate courses of action Condition codes (Z
VHDL Branch Instructions Programs can evaluate conditions and take alternate courses of action Condition codes (Z

Branch Instructions

VHDL Branch Instructions Programs can evaluate conditions and take alternate courses of action Condition codes (Z

Programs can evaluate conditions and take alternate courses of action

Condition codes (Z, C) represent outcomes of arithmetic/logical/shift instructions

Branch instructions examine Z or C

bz, bnz, bc, bnc Add a displacement to PC if condition is true Specifies how many instructions forward or backward to skip

Counting from instruction after branch

forward or backward to skip Counting from instruction after branch Digital Design — Chapter 7 —

Digital Design — Chapter 7 — Processor Basics

27

VHDL

VHDL Branch Exam p le Elapsed seconds in location 100 Increment, wrapping to 0 after 59
VHDL Branch Exam p le Elapsed seconds in location 100 Increment, wrapping to 0 after 59

Branch Example

VHDL Branch Exam p le Elapsed seconds in location 100 Increment, wrapping to 0 after 59

Elapsed seconds in location 100

Increment, wrapping to 0 after 59

ldm

r1, 100

add

r1, r1, 1

sub

r0, r1, 60

; Z set if r1 = 60

bnz

+1

; Skip to store if

add

r1, r0, 0

;

Z is 0

stm

r1, 100

to store if add r1, r0, 0 ; Z is 0 stm r1, 100 Digital Design

Digital Design — Chapter 7 — Processor Basics

28

VHDL

VHDL Jum p Instruction Unconditionall y ski p s forward or backward to specified address Changes
VHDL Jum p Instruction Unconditionall y ski p s forward or backward to specified address Changes

Jump Instruction

VHDL Jum p Instruction Unconditionall y ski p s forward or backward to specified address Changes

Unconditionally skips forward or backward to specified address

Changes the PC to the address

Example: if r1 = 0, clear data location 100 to 0; otherwise clear location 200 to 0

Assume instructions start at address 10

10:

sub

r0, r1, 0

11:

bnz

+2

12:

stm

r0, 100

13:

jmp

15

14:

stm

r0, 200

15:

stm r0, 100 13: jmp 15 14: stm r0, 200 15: Digital Design — Chapter 7

Digital Design — Chapter 7 — Processor Basics

29

VHDL

VHDL Subroutines A sequence of instructions that perform some operation Can call them from different p
VHDL Subroutines A sequence of instructions that perform some operation Can call them from different p

Subroutines

VHDL Subroutines A sequence of instructions that perform some operation Can call them from different p

A sequence of instructions that perform some operation

Can call them from different parts of a program using a jsb instruction Subroutine returns with a ret instruction

jsb m …
jsb m
m subroutine instructions … jsb m … … ret
m
subroutine
instructions
jsb m
ret
jsb m … m subroutine instructions … jsb m … … ret Digital Design — Chapter

Digital Design — Chapter 7 — Processor Basics

30

VHDL

VHDL Subroutine Exam p le Subroutine to increment second count Address of count in r2 ldm
VHDL Subroutine Exam p le Subroutine to increment second count Address of count in r2 ldm

Subroutine Example

VHDL Subroutine Exam p le Subroutine to increment second count Address of count in r2 ldm

Subroutine to increment second count

Address of count in r2

ldm

r1, (r2)

add

r1, r1, 1

sub

r0, r1, 60

bnz

+1

add

r1, r0, 0

stm

r1, (r2)

ret

Call to increment locations 100 and 102

add

r2, r0, 100

jsb

20

add

r2, r0, 102

jsb

20

VHDL

VHDL Return Address Stack The jsb saves the return address for use by the ret But
VHDL Return Address Stack The jsb saves the return address for use by the ret But

Return Address Stack

VHDL Return Address Stack The jsb saves the return address for use by the ret But

The jsb saves the return address for use by the ret

But what if the subroutine includes a jsb?

Gumnut core includes an 8-entry push- down stack of return addresses

    return addr for third call return addr for second call return addr for
    return addr for third call return addr for second call return addr for
    return addr for third call return addr for second call return addr for
    return addr for third call return addr for second call return addr for
    return addr for third call return addr for second call return addr for
    return addr for third call return addr for second call return addr for
    return addr for third call return addr for second call return addr for
    return addr for third call return addr for second call return addr for
   

return addr for third call

return addr for second call

return addr for second call

return addr for first call

return addr for first call

call return addr for first call return addr for first call Digital Design — Chapter 7

Digital Design — Chapter 7 — Processor Basics

32

VHDL

VHDL Miscellaneous Instructions Instructions su pp ortin g interru p ts See Chapter 8 ret i
VHDL Miscellaneous Instructions Instructions su pp ortin g interru p ts See Chapter 8 ret i

Miscellaneous Instructions

VHDL Miscellaneous Instructions Instructions su pp ortin g interru p ts See Chapter 8 ret i

Instructions supporting interrupts

See Chapter 8 reti Return from interrupt enai Enable interrupts disi Disable interrupts wait Wait for an interrupt stby Stand by in low power mode until an interrupt occurs

p t stby Stand by in low power mode until an interrupt occurs Digital Design —

Digital Design — Chapter 7 — Processor Basics

33

VHDL

VHDL T he Gumnut Assembler Gasm: translates assembl y p ro g rams Generates memory images
VHDL T he Gumnut Assembler Gasm: translates assembl y p ro g rams Generates memory images

The Gumnut Assembler

VHDL T he Gumnut Assembler Gasm: translates assembl y p ro g rams Generates memory images

Gasm: translates assembly programs

Generates memory images for program text (binary-coded instructions) and data See documentation on web site

Write a program as a text file

Instructions Directives Comments Use symbolic labels

file Instructions Directives C ommen ts Use symbolic labels Digital Design — Chapter 7 — Processor

Digital Design — Chapter 7 — Processor Basics

34

VHDL

VHDL Exam p le Pro g ram ; Program to determine grea ter of value_1 and
VHDL Exam p le Pro g ram ; Program to determine grea ter of value_1 and

Example Program

VHDL Exam p le Pro g ram ; Program to determine grea ter of value_1 and

; Program to determine greater of value_1 and value_2 text

 

org

0x000

; start here on reset

jmp

main

; Data memory layout

 

data

value_1:

byte

10

value_2:

byte

20

result:

bss

1

;

Main program

 

text

org

0x010

main:

ldm

r1, value_1

; load values

ldm sub

r2, value_2 r0, r1, r2

; compare values

bc

value_2_greater

stm

r1, result

; value_1 is greater

jmp value_2_greater: stm

finish r2, result

; value_2 is greater

finish:

stm finish r2, result ; value_2 is greater finish: jm p finish idle loo ; p

jm

p

finish

idle loo

;

p

Digital Design — Chapter 7 — Processor Basics

35

VHDL

VHDL Gumnut Instruction Encodin g Instructions are a form of information Can be encoded in binary
VHDL Gumnut Instruction Encodin g Instructions are a form of information Can be encoded in binary

Gumnut Instruction Encoding

VHDL Gumnut Instruction Encodin g Instructions are a form of information Can be encoded in binary

Instructions are a form of information

Can be encoded in binary

Gumnut encoding

18 bits per instruction Divided into fields representing different aspects of the instruction

fields representing different as p ects of the instruction Opcodes and function codes Register num b

Opcodes and function codes

Register numbers Addresses

The VAX has a computer architecture with easily the most complex instruction set.

The instruction set has a highly variable format where the minimal instruction length is 1 byte and the longest instruction is 37 bytes (296 bits).

Digital Design — Chapter 7 — Processor Basics

36

VHDL

VHDL Gumnut Instruction Encodin g Arith/Log ical Register Arith/Logical Immediate Shift Memory, I/O Branch J ump
VHDL Gumnut Instruction Encodin g Arith/Log ical Register Arith/Logical Immediate Shift Memory, I/O Branch J ump

Gumnut Instruction Encoding

VHDL Gumnut Instruction Encodin g Arith/Log ical Register Arith/Logical Immediate Shift Memory, I/O Branch J ump

Arith/Logical

Register

Arith/Logical

Immediate

Shift

Memory, I/O

Branch

J ump

4

33

332

1

1

1

0

 

rd

 

rs

rs 2

 

fn

1

333

 

8

0

 

fn

 

rd

 

rs

 

immed

 

3

1

33

3

3

2

110

   

rd

 

rs

count

 

fn

22

 

3

3

8

1

0

fn

 

rd

 

rs

 

offset

 

6

 

22

 

8

11

111

0

fn

   

disp

 

5

1

12

1

1

1

1

0

   

dd

 

fn

 

a

r

Miscellaneous

73

8

111111

0

fn

111111 0 fn
  fn   a r Miscellaneous 73 8 111111 0 fn Digital Design — Chapter 7

Digital Design — Chapter 7 — Processor Basics

37

VHDL

VHDL Encodin g Exam p les Encoding for addc r3 , r5 , 24 Arithmetic immediate,
VHDL Encodin g Exam p les Encoding for addc r3 , r5 , 24 Arithmetic immediate,

Encoding Examples

VHDL Encodin g Exam p les Encoding for addc r3 , r5 , 24 Arithmetic immediate,

Encoding for addc r3, r5, 24

Arithmetic immediate, fn = 001

1

333

 

8

0

fn

rd

rs

 

immed

0

0110

0101

 

100

0101

0

0

05D18

Instruction encoded by 2ECFC

 

11

11

1

0

1100

111111

00

 
 

6

22

8

Branch

11

111

0

fn

 

disp

bnc -4

22 8 Branch 11 111 0 fn   disp bnc -4 Digital Design — Chapter 7

Digital Design — Chapter 7 — Processor Basics

38

VHDL

VHDL Other Instruction Sets 8- bit cores and microcontrollers Xilinx PicoBlaze: like Gumnut 8051 , and
VHDL Other Instruction Sets 8- bit cores and microcontrollers Xilinx PicoBlaze: like Gumnut 8051 , and

Other Instruction Sets

VHDL Other Instruction Sets 8- bit cores and microcontrollers Xilinx PicoBlaze: like Gumnut 8051 , and

8-bit cores and microcontrollers

Xilinx PicoBlaze: like Gumnut 8051, and numerous like it

Originated as 8-bit microprocessors Instructions encoded as one or more bytes Instruction set is more complex and irregular Complex instruction set computer (CISC) C.f. Reduced instruction set computer (RISC)

16-, 32- and 64-bit cores

Mostly RISC E.g., PowerPC, ARM, MIPS, Tensilica, …

64-bit cores Mostly RISC E.g., PowerPC, ARM, MIPS, Tensilica, … Digital Design — Chapter 7 —

Digital Design — Chapter 7 — Processor Basics

39

VHDL

VHDL Instruction and Data Memory In embedded s y stems Instruction memory is usually ROM, flash,
VHDL Instruction and Data Memory In embedded s y stems Instruction memory is usually ROM, flash,

Instruction and Data Memory

VHDL Instruction and Data Memory In embedded s y stems Instruction memory is usually ROM, flash,

In embedded systems

Instruction memory is usually ROM, flash, SRAM, or combination Data memory is usually SRAM

DRAM if large capacity needed

Processor/memory interfacing

Gluing the signals together

needed Processor / memor y interfacin g Gluing the signals together Digital Design — Chapter 7

Digital Design — Chapter 7 — Processor Basics

40

VHDL

VHDL Exam p le: Gumnut Memor y instruction gumnut data ROM SRAM clk_i clk_i rst_i clk_i
VHDL Exam p le: Gumnut Memor y instruction gumnut data ROM SRAM clk_i clk_i rst_i clk_i

Example: Gumnut Memory

VHDL Exam p le: Gumnut Memor y instruction gumnut data ROM SRAM clk_i clk_i rst_i clk_i
instruction gumnut data ROM SRAM clk_i clk_i rst_i clk_i inst_cyc_o data_cyc_o en en i nst_
instruction
gumnut
data
ROM
SRAM
clk_i
clk_i
rst_i
clk_i
inst_cyc_o
data_cyc_o
en
en
i
nst_ st _ o
b
d
ata_ st _ o
b
D
Q
inst_ack_i
data_ack_i
Q
D
clk
clk
data we o
_
_
we
adr
inst_adr_o
dat_o
inst_dat_i
data_adr_o
adr
data_dat_o
dat_i
data_dat_i
dat_o
inst_dat_i data_adr_o adr data_dat_o dat_i data_dat_i dat_o Digital Design — Chapter 7 — Processor Basics 41

Digital Design — Chapter 7 — Processor Basics

41

VHDL

VHDL Exam p le: Gumnut Memor y IMem : process (clk) is begin if rising_edge(clk) then
VHDL Exam p le: Gumnut Memor y IMem : process (clk) is begin if rising_edge(clk) then

Example: Gumnut Memory

VHDL Exam p le: Gumnut Memor y IMem : process (clk) is begin if rising_edge(clk) then

IMem : process (clk) is begin if rising_edge(clk) then if inst_cyc_o = '1' and inst_stb_o = '1' then inst_dat_i <= instr_ROM(to_integer(inst_adr_o(10 downto 0))); inst_ack_i <= '1'; else inst_ack_i <= '0'; end if; end if; end process IMem;

inst_ack_i <= '0'; end if; end if; end process IMem; Digital Design — Chapter 7 —

Digital Design — Chapter 7 — Processor Basics

42

VHDL

VHDL Exam p le: Gumnut Memor y DMem : process (clk) is begin if rising_edge(clk) then
VHDL Exam p le: Gumnut Memor y DMem : process (clk) is begin if rising_edge(clk) then

Example: Gumnut Memory

VHDL Exam p le: Gumnut Memor y DMem : process (clk) is begin if rising_edge(clk) then

DMem : process (clk) is begin if rising_edge(clk) then if data_cyc_o = '1' and data_stb_o = '1' then if data_we_o = '1' then data_RAM(to_integer(data_adr_o)) <= data_dat_o; data_dat_i <= data_dat_o; data_ack_i <= '1'; else data_dat_i <= data_RAM(to_integer(data_adr_o)); data_ack_i <= '1'; end if; else data_ack_i <= '0'; end if; end if; end process DMem;

data_ack_i <= '0'; end if; end if; end process DMem; Digital Design — Chapter 7 —

Digital Design — Chapter 7 — Processor Basics

43

VHDL

VHDL Exam p le: Microcontroller Memor y 8051 SRAM P2 A(15 8) D P0 D Q
VHDL Exam p le: Microcontroller Memor y 8051 SRAM P2 A(15 8) D P0 D Q

Example: Microcontroller Memory

VHDL Exam p le: Microcontroller Memor y 8051 SRAM P2 A(15 8) D P0 D Q
8051 SRAM P2 A(15 8) D P0 D Q A(7 0) ALE LE PSEN A(16)
8051
SRAM
P2
A(15 8)
D
P0
D Q
A(7 0)
ALE
LE
PSEN
A(16)
WR
WE
OE
RD
CE

PSEN (program store enable)

ALE LE PSEN A(16) WR WE OE RD CE PSEN (program store enable) Digital Design —

Digital Design — Chapter 7 — Processor Basics

44

VHDL

VHDL 32-bit Memor y Four bytes per memory word Little-endian: lsb at least address Big -endian:
VHDL 32-bit Memor y Four bytes per memory word Little-endian: lsb at least address Big -endian:

32-bit Memory

VHDL 32-bit Memor y Four bytes per memory word Little-endian: lsb at least address Big -endian:

Four bytes per memory word

Little-endian: lsb at least address Big-endian: msb at least address

   

0123

         

4

 

5

 

6

 

7

 

8

 

9

 

10

 

11

 
           
           
           
           
           
  6   7   8   9   10   11        
  6   7   8   9   10   11        
  6   7   8   9   10   11        
  6   7   8   9   10   11        
  6   7   8   9   10   11        
  6   7   8   9   10   11        

Partial-word read

Read all bytes, processor selects those needed

Partial-word write

pr ocesso r se lects th ose n eeded Partial-word write U se b t bl

U

se

b t

bl

y e-ena

i

l

e s gna s

Digital Design — Chapter 7 — Processor Basics

45

VHDL

VHDL Exam p le: MicroBlaze Memor y 2:16 SSRAM Add r A Data_Write 0:7 0:7 D_in
VHDL Exam p le: MicroBlaze Memor y 2:16 SSRAM Add r A Data_Write 0:7 0:7 D_in

Example: MicroBlaze Memory

VHDL Exam p le: MicroBlaze Memor y 2:16 SSRAM Add r A Data_Write 0:7 0:7 D_in
VHDL Exam p le: MicroBlaze Memor y 2:16 SSRAM Add r A Data_Write 0:7 0:7 D_in
2:16 SSRAM Add r A Data_Write 0:7 0:7 D_in D_out AS en Write_Strobe wr Byte_Enable(0)
2:16
SSRAM
Add r
A
Data_Write
0:7
0:7
D_in
D_out
AS
en
Write_Strobe
wr
Byte_Enable(0)
clk
Byte _ Enable(1)
Byte_Enable(2)
SSRAM
Byte_Enable(3)
A
8:15
8:15
Read_Strobe
D_in
D_out
en
Data_Read
wr
+V
clk
Ready
Clk
SSRAM
A
16:23
16:23
D_in
D_out
en
wr
clk
SSRAM
A
24:31
24:31
D_in
D_out
en
wr
clk
Digital Design — Chapter 7 — Processor Basics

46

VHDL

VHDL Cache Memor y For hi g h - performance processors Memory access time is several
VHDL Cache Memor y For hi g h - performance processors Memory access time is several

Cache Memory

VHDL Cache Memor y For hi g h - performance processors Memory access time is several

For high-performance processors

Memory access time is several clock cycles Performance bottleneck

Cache memory

Small fast memory attached to a processor Stores most frequently accessed items, plus adjacent items Locality: those items are most likely to be accessed again soon

y: th ose it ems are mos t lik ely t o b e accessed again

Digital Design — Chapter 7 — Processor Basics

47

VHDL

VHDL Cache Memor y Memory contents divided into fixed - sized blocks (lines) Cache co p
VHDL Cache Memor y Memory contents divided into fixed - sized blocks (lines) Cache co p

Cache Memory

VHDL Cache Memor y Memory contents divided into fixed - sized blocks (lines) Cache co p

Memory contents divided into fixed- sized blocks (lines)

Cache copies whole lines from memory

When processor accesses an item

If item is in cache: hit - fast access

Occurs most of the time

If item is not in cache: miss

Line containing item is copied from memory Slower, but less frequent May need to replace a line already in cache

but l ess f requen t May need to replace a line already in cache Digital

Digital Design — Chapter 7 — Processor Basics

48

VHDL

VHDL Fast Main Memor y Access Optimize memory for line access by cache Wide memory Read
VHDL Fast Main Memor y Access Optimize memory for line access by cache Wide memory Read

Fast Main Memory Access

VHDL Fast Main Memor y Access Optimize memory for line access by cache Wide memory Read

Optimize memory for line access by cache

Wide memory

Read a line in one access

Burst transfers

Send starting address, then read successive locations

Pipelining

Overlapping stages of memory access E.g., address transfer, memory operation, data transfer

Double data rate (DDR), Quad data rate (QDR)

Transfer on both rising and falling clock edges

Quad data rate (QDR) Transfer on both rising and falling clock edges Digital Design — Chapter

Digital Design — Chapter 7 — Processor Basics

49

VHDL

VHDL Summar y Embedded computer Processor, memory, I/O controllers, buses Microprocessors , microcontrollers , and
VHDL Summar y Embedded computer Processor, memory, I/O controllers, buses Microprocessors , microcontrollers , and

Summary

VHDL Summar y Embedded computer Processor, memory, I/O controllers, buses Microprocessors , microcontrollers , and

Embedded computer

Processor, memory, I/O controllers, buses

Microprocessors, microcontrollers, and processor cores Soft-core processors for ASIC/FPGA Processor instruction sets

Binary encoding for instructions

Assembly language programs Memory interfacing

for instructions Assembly l anguage programs Memory interfacing Digital Design — Chapter 7 — Processor Basics

Digital Design — Chapter 7 — Processor Basics

50