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N-channel 600 V - 0.56 - 7 A - TO-220 - TO-220FP - IPAK - DPAK second generation MDmesh Power MOSFET
Features
Type STD8NM60N STD8NM60N-1 STF8NM60N STP8NM60N VDSS (@Tjmax) 650 V 650 V 650 V 650 V RDS(on) max <0.65 <0.65 <0.65 <0.65 ID
3
3 2 1
1 2
7A 7A 7 A(1) 7A
IPAK
TO-220
3 1
1 3 2
100% avalanche tested Low input capacitance and gate charge Low gate input resistance
DPAK
TO-220FP
Application
Figure 1.
Switching applications
Description
This series of devices implements second generation MDmesh technology. This revolutionary Power MOSFET associates a new vertical structure to the Companys strip layout to yield one of the worlds lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters.
Table 1.
Device summary
Marking D8NM60N D8NM60N-1 F8NM60N P8NM60N Package DPAK IPAK TO-220FP TO-220 Packaging Tape & reel Tube Tube Tube
January 2008
Rev 2
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www.st.com 17
Contents
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................ 6
3 4 5 6
Test circuit
................................................ 9
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Electrical ratings
Electrical ratings
Table 2.
Symbol
Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25 C Drain current (continuous) at TC = 100 C Drain current (pulsed) Total dissipation at TC = 25 C Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s;TC = 25 C) Peak diode recovery voltage slope Operating junction temperature Storage temperature
1. Limited only by maximum temperature allowed 2. Pulse width limited by safe operating area 3. ISD 7A, di/dt 400A/s, VDD = 80% V(BR)DSS
Table 3.
Symbol
Thermal data
Value Parameter TO-220 DPAK/IPAK 1.78 62.5 300 Unit TO-220FP 5 C/W C/W C
Rthj-case Rthj-amb Tl
Thermal resistance junction-case Thermal resistance junction-amb Maximum lead temperature for soldering purpose
Table 4.
Symbol IAS EAS
Avalanche characteristics
Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj = 25 C, ID = IAS, VDD = 50 V) Max value 2.5 200 Unit A mJ
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Electrical characteristics
Electrical characteristics
(TCASE=25 C unless otherwise specified) Table 5.
Symbol V(BR)DSS dv/dt(1)
On/off states
Parameter Drain-source breakdown voltage Drain-source voltage slope Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 1 mA, VGS = 0 VDD = 480 V, ID = 7 A, VGS =10 V VDS = Max rating, VDS = Max rating,Tc = 125 C VGS = 20 V VDS = VGS, ID = 250 A VGS = 10V, ID = 3.5 A 2 3 0.56 Min. 600 38 1 100 100 4 0.65 Typ. Max. Unit V V/ns A A nA V
Table 6.
Symbol gfs(1) Ciss Coss Crss Coss eq.(2)
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Equivalent output capacitance Gate input resistance Test conditions VDS = 15 V, ID= 3.5 A Min. Typ. Max. 15 560 37 2 153 Unit S pF pF pF pF
VGS = 0, VDS = 0 to 480 V f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain VDD = 480 V, ID = 7 A VGS = 10 V (see Figure 19)
RG Qg Qgs Qgd
1.
19 3 10
nC nC nC
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
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Electrical characteristics
Table 7.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 300 V, ID = 3.5 A, RG = 4.7 , VGS = 10 V (see Figure 18), (see Figure 23) Min. Typ. 10 12 40 10 Max. Unit ns ns ns ns
Table 8.
Symbol ISD ISDM (1) VSD(2) trr Qrr IRRM trr Qrr IRRM
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300s, duty cycle 1.5%
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Electrical characteristics
2.1
Figure 2.
Figure 4.
Figure 6.
Figure 7.
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Figure 12. Gate charge vs gate-source voltage Figure 13. Capacitance variations
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Electrical characteristics
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Test circuit
Test circuit
Figure 19. Gate charge test circuit
Figure 20. Test circuit for inductive load Figure 21. Unclamped inductive load test switching and diode recovery times circuit
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mm Dim Min A b b1 c D D1 E e e1 F H1 J1 L L1 L20 L30 P Q 4.40 0.61 1.14 0.49 15.25 1.27 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 Typ Max 4.60 0.88 1.70 0.70 15.75 Min 0.173 0.024 0.044 0.019 0.6
inch Typ Max 0.181 0.034 0.066 0.027 0.62 0.050 0.409 0.106 0.202 0.051 0.256 0.107 0.551 0.154 0.645 1.137 0.151 0.116
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DIM. A B D E F F1 F2 G G1 H L2 L3 L4 L5 L6 L7
L3 L6 L7
F1 F
G1 H
F2
L2 L5
E
1 2 3
L4
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H
C A C2
L2
D
B3 B6
A1
B5
A3
=
B2
G
=
L1
0068771-E
13/17
0068772-F
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mm MIN. 6.8 10.4 1.5 1.5 1.65 7.4 2.55 3.9 7.9 1.9 40
15.7 16.3
inch MIN. MAX. 7 0.267 0.275 0.409 0.417 0.476 0.059 0.063 0.059 0.065 0.073 0.291 0.299 0.100 0.108 0.153 0.161 0.311 0.319 0.075 0.082 1.574
0.618 0.641
MAX. 10.6 12.1 1.6 1.85 7.6 2.75 4.1 8.1 2.1
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Revision history
Revision history
Table 9.
Date 29-Aug-2007 07-Jan-2008
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