It still seems that there is a little bit of confusion on how analyze the general CMOS inverter.

In
order to clarify a few things, Im going to do a full analysis on your basic CMOS inverter.
Lets first take a look at your basic schematic and make note of the constants that we will need.
If you have any questions about where these constants come from, please refer to your text, as
Im pulling many of them straight from the draft chapters.
NMOS: Vto = 0.43V
Vdsat = 0.63V
k' = 115e-6 A/V
2
= 0.4 V
0.5
= 0.06 V
-1
Cox = 6.0 fF/um
2
Co = 0.31 fF/um
Cj = 2.0 fF/um
2
Cjsw = 0.28 fF/um
PMOS: Vto = - 0.4V
Vdsat = - 1.0V
k' = - 30.0e-6 A/V
2
= - 0.4 V
0.5
= - 0.10 V
-1
Cox = 6.0 fF/um
2
Co = 0.27 fF/um
Cj = 1.9 fF/um
2
Cjsw = 0.22 fF/um
Vm = 1.0V
Ldiff = 0.6um
Now we can get started on analyzing this basic amplifier. In this analysis, we will attempt to find
the following:
a) Unloaded propagation delay
b) Propagation delay in a H => L transition when loaded by an identical inverter
c) Energy consumed from supply in a H => L transition when loaded by an identical
inverter
d) Energy consumed from supply in a L => H transition when loaded by an identical
inverter.
VDD = 2.5V
Vin Vout
(W/L) = (0.58u/
0.24u)
(W/L) = (0.58u/
0.24u)
a)
( )
phl plh p
t t t +
2
1
;
First, we must understand why there is a delay involved with this simple inverter.
The delay is caused by a number of parasitic resistances and capacitances that the
devices themselves introduce.
The resistance actually varies depending on your drain current, due to the devices
non-linear characteristics. There are actually a number of ways in which an
equivalent resistance for the MOS can be calculated. One is by using integrals. This
would ultimately lead in a very accurate answer. However, in the end, this is overkill.
As an engineer, we have programs to determine exact resistances. The hand analysis
is for a simple first order approximation by which we can predict performance and
possible pitfalls.
Thus, we can adapt a much rougher, but still relatively accurate, approximation for
the resistance by averaging the resistance at two points of interest. These points of
interest are at the beginning and the end of a transition. At this point in the analysis,
you should look at your circuit and analyze the circuit and its node voltages at the
beginning of a transition (ie. before the load capacitor begins dis/charging) and at the
end (ie. the point at which we can safely say that the output has reached a logic
high/low), which occurs at Vm.
While not totally correct, this is a good approximation that is simple to do by hand
and can give you as an engineer a good deal of insight on how your circuit may
behave.
The parasitic capacitances that load the output stage of the inverter originate mainly
from two sources:
1) Diffusion capacitances due to the intrinsic pn junctions at the source and the drain
2) Capacitances similar to your basic parallel-plate caps at your gate due to overlap
and the gate oxide.
These capacitances are relatively simple to determine if your dimensions are known.
Most of the variables are set by fabricating technology, and are given to you. The
main variable that you as an engineer can control when it comes to your capacitances
is the transistor sizing.
Note that there is an inverse relationship between your parasitic resistance and
parasitic capacitance. As one increases, the other will decrease. As a designer, you
should see this relationship and work to optimize your design so that you can
maximize your performance.
Now this delay originates from the time it takes to charge these parasitic and load (if
present) capacitances to the desired value. As your resistances and capacitances
increase, so will the time reqd to charge them.
Lets start off by calculating t
plh,
which involves the PMOS transistor:
up p eq plh
C R t
,
69 . 0
( )
E B
DS
DS
DS
DS
p eq
R R
End I
End V
Beginning I
Beginning V
R +
]
]
]

,
`

.
|
+

,
`

.
|

2
1
@
@
@
@
2
1
,
The Vdss used at this point are dependent on the value of Vm, due to the fact
that transition is marked by this Vm. For this example, lets make life easy on us
and just assume that Vm = 1.0V, as stated above.
DD DS
V Beginning V @
- Operating in Saturation;
DD M DS
V V End V @
- Operating in Linear;
( ) ( ) mA V V V
L
W
k
Beginning I
DS to SG
p
DS
2 . 0 1
2
'
@
2
+
( ) ( ) mA V
V
V V V
L
W
k End I
DS
DS
DS to SG p DS
1688 . 0 1
2
' @
2
+
]
]
]
]

k R
B
5 . 12 ;
k R
E
886 . 8 ;

k R
p eq
693 . 10
, - Eq: R
eq,p
p db n db p gd n gd up
C C C C C
, , , ,
+ + +
;
fF WC C
n o n gd
3596 . 0 2
, ,

;
fF WC C
p o p gd
3132 . 0 2
, ,

This is due to the overlap capacitance. This capacitance is also
included as an input capacitance. It is multiplied by 2 due to the
Miller Effect.
fF W L C WL C C
diff n jsw n j n db
7768 . 0 ) 2 (
, , ,
+ +
fF W L C WL C C
diff p jsw p j p db
6561 . 0 ) 2 (
, , ,
+ +
This is due to the diffusion capacitances in the source and drain
regions.
*Note: It is important to know that this diffusion capacitance varies
with the transition type due to the variance in Keq. In this example
we will neglect that effect. Come test or homework time though,
do not neglect this variance unless specifically told to do so.

fF C
up
1057 . 2
- Eq: C
up

ps s e C R t
up p eq plh
516 . 22 11 2516 . 2 69 . 0
,

- Eq: t
plh
Now lets work to calculate t
phl
using the same methodology as for t
plh
.
down n eq phl
C R t
,
69 . 0
( )
E B
DS
DS
DS
DS
n eq
R R
End I
End V
Beginning I
Beginning V
R +
]
]
]

,
`

.
|
+

,
`

.
|

2
1
@
@
@
@
2
1
,
DD DS
V Beginning V @
- Operating in Saturation;
M DS
V End V @
- Operating in Linear;
( ) ( ) mA V V V
L
W k
Beginning I
DS to GS
n
DS
6847 . 0 1
2
'
@
2
+
( ) ( ) mA V
V
V V V
L
W
k End I
DS
DS
DS to GS n DS
4625 . 0 1
2
' @
2
+
]
]
]
]

k R
B
651 . 3 ;
k R
E
162 . 2 ;

k R
n eq
906 . 2
, - Eq: R
eq,n
p db n db p gd n gd down
C C C C C
, , , ,
+ + +
;
fF WC C
n o n gd
3596 . 0 2
, ,

;
fF WC C
p o p gd
3132 . 0 2
, ,

fF W L C WL C C
diff n jsw n j n db
7768 . 0 ) 2 (
, , ,
+ +
fF W L C WL C C
diff p jsw p j p db
6561 . 0 ) 2 (
, , ,
+ +

fF C
down
1057 . 2
- Eq: C
down

ps s e C R t
down n eq phl
119 . 6 12 119 . 6 69 . 0
,

- Eq: t
plh
Now that we have found the two necessary propagation delays, namely for the L => H
and the H => L transition, it is now possible to determine your average propagation
delay:
( ) ps s e t t t
phl plh p
32 . 14 11 432 . 1
2
1
+
b) To find the propagation delay when loaded with an identical inverter, the calculations
are actually relatively trivial. The hard work was done in part a, where the equivalent
resistances had to be determined.
In order to determine the new propagation delay, it is necessary to find the load that
his inverter represents. This is not unlike your homework problem in assignment #3
to determine the input capacitance.
The input capacitance consists of the gate-drain, gate-source, and gate-channel
capacitances:
( ) ( )
gc
n
gs gd
p
gs gd in
C C C C C C + + + + 2 2
; Multiply gate-drain due to Miller effect
fF WLC C
fF W C C C
fF W C C C
ox gc
n o n gs n gd
p o p gs p gd
8352 . 0
1798 . 0
1566 . 0
, , ,
, , ,

fF C
in
8536 . 2
- Eq: C
in
Using this value for C
in
, it is now possible to find your new load capacitance. The
intrinsic load of the driving inverter remains the same.
( ) ps s e C C R t
L n eq phl
41 . 14 11 441 . 1 69 . 0
int ,
+
*Note: If we wanted to calculate the average propagation delay with this new load, it
would be necessary to determine both the new t
plh
and t
phl
and then to take the average
of these new values.
c) We know from the readings and from Prof. Rabaeys lectures that:
( ) J e V C C E
L
14 01575 . 3
2
int
+
This energy is used in two ways:
1) Half is dissipated in storing the capacitor
2) The other half is stored on the capacitor, and eventually discharged in a high-
to-low transition.
d) There is no energy consumed from the supply in a high-to-low transition. As
previously discussed, the remaining charge stored on the load capacitor is dissipated.