7th Sem, VLSI Lab Manual STEPS IN LINUX TERMINAL Linux Terminal Steps: Username: student01 Password: student01

1. Open Terminal from Desktop i.e. Right Click in the center of plane Desktop and use Open Terminal 2. Start the License Server 3. Check the License Manager Status 4. Create Directory with Student USN as Directory Name 5. Inside Student USN Directory Create Workspace directory 6. Copy Library files (i.e. tsmc018_typ.syn and adk.v) from /home/student01/libraries/ 7. Here are some Commands in Steps 1 8. Follow the below Steps 2 to execute front end programs Note: $ Linux prompt Just like C:\> MS DOS prompt Linux is Case sensitive Always use only Small Letters/Alphabets

2011-12

Space Character/Symbol/Space bar

Carriage Return/Enter key Symbol/Enter key

Steps 1:

$ source.cshrc $ Lmstat $ mkdir1ce01ec001 $ cd1ce01ec001 /1ce01ec001$ vlibwork /1ce01ec001$ cp/home/student01/libraries/*. /1ce01ec001$ viinverter.v /1ce01ec001$ vloginverter.vinverter_test.v /1ce01ec001$ vloginverter_net.vinverter_gatetest.vadk.v /1ce01ec001$ vsimcinverter_testnovopt /1ce01ec001$ vsiminverter_testnovopt Menu Mode /1ce01ec001$ spectrum /1ce01ec001$ ls /1ce01ec001$ cd.. $ pwd $ cd\ $ pwd--help :wproj1.v $ vi--help $ exit Vi editors basic commands
:q Quit VI. If there have been changes made, the editor will issue a warning message. :q! Quit VI without saving changes. :viproj1.vStarts editing a new file. If changes have not been saved, the editor will give you awarning. :w Write out the current file. :wproj2.v Write the buffer to the filename specified. :wq Write the buffer and quit. :wq! Write the buffer and force quit.
Rest of the commands please follow STEPS 2
Insert

or
I

Insert Mode

Esc

--Insert--

Vi editor

Dept. of E&C, CEC

SKLN, RCVK

7th Sem, VLSI Lab Manual STEPS IN LINUX TERMINAL 2011-12 Steps 2: 1. Create Mainmodule Verilog $ visync_counter.v 2. Check Syntax error of Only Mainmodule Verilog $ vlogsync_counter.v 3. Create Testbench to test Mainmodule Verilog $ visync_counter_testbench.v 4. Check Syntax error of Only Testbench $ vlogsync_counter_testbench.v 5. Check compatibility of both Top/Mainmodule and Testbench together to obtain Top-module name $ vlogsync_counter.vsync_counter_testbench.v 6. Simulate Testbench in Text mode using Top-module name in Vsim $ vsimcsync_counter_testbenchnovopt VSIM1> run-all 7. Simulate Testbench in GUI/Graphical mode in Modelsim $ vsimsync_counter_testbenchnovopt 8. Generate SDF and Netlist file from Spectrum using constraints provided $ spectrum <leonardo 1> load_librarytsmc018_typ.syn <leonardo 2> read-formatverilogsync_counter.v <leonardo 3> setinput2register 2.00 <leonardo 4> setinput2output 3.00 <leonardo 5> setregister2output 3.00 <leonardo 6> setregister2register 3.20 <leonardo 7> clock_cycle3.2clock <leonardo 8> set_attribute-nameARRIVAL_TIME-value"0.4"-portreset <leonardo 9> set_attribute-nameARRIVAL_TIME-value"0.4"-portdown <leonardo 10> set_attribute-nameARRIVAL_TIME-value"0.4"-portup <leonardo 11> optimize <leonardo 12> write-formatverilogsync_counter_netlist.v <leonardo 13> write-formatsdfsync_counter.sdf <leonardo 14> report_delay >delay.rpt <leonardo 15> report_area>area.rpt <leonardo 16> exit 9. Create Gatelevel Testbench to test Mainmodule Verilog using 180 nm Technology $ visync_counter_gatetestbench.v 10. Check Syntax error of Only Gatelevel Testbench $ vlogsync_counter_gatetestbench.v 11. Check compatibility of Netlistfile, Gatelevel Testbench and adk.v library together to obtain Top-module name w.r.t. 180 nm Technology $ vlogsync_counter_netlist.vsync_counter_gatetestbench.vadk.v 12. Simulate Gatelevel Testbench in Text mode using Top-module name in Vsim $ vsimcsync_counter_gatetestbenchnovopt run-all 13. Simulate Gatelevel Testbench in GUI/Graphical mode in Modelsim using Top-module name $ vsimsync_counter_gatetestbenchnovopt 14. To Exit the Linux Terminal $ exit

Dept. of E&C, CEC

SKLN, RCVK