7th Sem, VLSI Lab Manual LEONARDO SPECTRUM CONSTRAINTS sync_counter.tcl load_library tsmc018_typ.syn tflipflop.

tcl read -format verilog sync_counter.v load_library tsmc018_typ.syn set input2register 2.00 read -format verilog tflipflop.v set input2output 3.00 clock_cycle 1 clock_i set register2output 3.00 set input2register 0.5 set register2register 3.20 set register2register 1 clock_cycle 3.2 clock set register2output 0.5 set_attribute -name ARRIVAL_TIME -value "0.4" -port reset optimize set_attribute -name ARRIVAL_TIME -value "0.4" -port down write -format verilog tflipflop_netlist.v set_attribute -name ARRIVAL_TIME -value "0.4" -port up write -format sdf tflipflop.sdf optimize write -format verilog sync_counter_netlist.v buffer.tcl write -format sdf sync_counter.sdf load_library tsmc018_typ.syn report_delay > delay.rpt read -format verilog buffer.v report_area > area.rpt set input2output 0.6 optimize Async_counter.tcl write -format verilog buffer_netlist.v load_library tsmc018_typ.syn write -format sdf buffer.sdf read -format verilog Async_counter.v elaborate serial_adder.tcl set input2register 2.00 load_library tsmc018_typ.syn set input2output 3.00 read -format verilog full_adder.v set register2output 3.00 read -format verilog serial_adder_4bit.v set register2register 3.20 set input2output 1 clock_cycle 3.2 Clock optimize set_attribute -name ARRIVAL_TIME -value "0.4" -port Reset write -format verilog serialadder_netlist.v optimize write -format sdf serialadder.sdf write -format verilog Async_counter_netlist.v write -format sdf Async_counter.sdf sar.tcl report_delay > delay.rpt load_library tsmc018_typ.syn report_area > area.rpt read -format verilog sar.v set input2register 2.00 dflipflop.tcl set input2output 3.00 load_library tsmc018_typ.syn set register2output 3.00 read -format verilog dflipflop.v set register2register 3.20 optimize clock_cycle 3.2 clock_i write -format verilog dflipflop_netlist.v optimize write -format sdf dflipflop.sdf write -format verilog sar_netlist.v write -format sdf sar.sdf master_slave.tcl report_delay > delay.rpt load_library tsmc018_typ.syn report_area > area.rpt read -format verilog dflipflop.v read -format verilog masterslave_flipflop.v parllel_adder.tcl clock_cycle 1 clock_i load_library tsmc018_typ.syn set input2register 0.5 read -format verilog parllel_adder.v set register2register 1 set input2output 1 set register2output 0.5 optimize optimize write -format verilog parlleladder_netlist.v write -format verilog master_slave_netlist.v write -format sdf parlleladder.sdf write -format sdf masterslave.sdf tgate.tcl rsflipflop.tcl load_library tsmc018_typ.syn load_library tsmc018_typ.syn read -format verilog tgate.v read -format verilog dflipflop.v optimize read -format verilog rsflipflop.v write -format verilog tgate_netlist.v synthesize write -format sdf tgate.sdf optimize write -format verilog rsflipflop_netlist.v write -format sdf rsflipflop.sdf Dept. of E&C, CEC 1

2011-12

SKLN, RCVK

7th Sem, VLSI Lab Manual inverter_syn.tcl load_library tsmc018_typ.syn read -format verilog inverter.v set input2output 0.5 optimize write -format verilog inverter_netlist.v write -format sdf inverter.sdf basic_gate.tcl load_library tsmc018_typ.syn read -format verilog and.v present_design set input2output 1 optimize write -format verilog basic_gates_and.v write -format sdf basic_gates_and.sdf report_delay > and_delay.rpt read -format verilog or.v present_design set input2output 1 optimize write -format verilog basic_gates_or.v write -format sdf basic_gates_or.sdf report_delay > or_delay.rpt read -format verilog nand.v present_design set input2output 1 optimize write -format verilog basic_gates_nand.v write -format sdf basic_gates_nand.sdf report_delay > nand_delay.rpt read -format verilog nor.v present_design set input2output 1 optimize write -format verilog basic_gates_nor.v write -format sdf basic_gates_nor.sdf report_delay > nor_delay.rpt read -format verilog xor.v present_design set input2output 1 optimize write -format verilog basic_gates_xor.v write -format sdf basic_gates_xor.sdf report_delay > xor_delay.rpt read -format verilog xnor.v present_design set input2output 1 optimize write -format verilog basic_gates_xnor.v write -format sdf basic_gates_xnor.sdf report_delay > xnor_delay.rpt Dept. of E&C, CEC

LEONARDO SPECTRUM CONSTRAINTS

2011-12 Steps: 1. Create Mainmodule Verilog $ vi sync_counter.v 2. Check Syntax error of Only Mainmodule Verilog $ vlog sync_counter.v 3. Create Testbench to test Mainmodule Verilog $ vi sync_counter_testbench.v 4. Check Syntax error of Only Testbench $ vlog sync_counter_testbench.v 5. Check compatibility of both Top/Mainmodule and Testbench together to obtain Top-module name $ vlog sync_counter.v sync_counter_testbench.v 6. Simulate Testbench in Text mode using Top-module name in Vsim $ vsim c sync_counter_testbench novopt run -all 7. Simulate Testbench in GUI/Graphical mode in Modelsim $ vsim sync_counter_testbench novopt 8. Generate SDF and Netlist file from Spectrum using constraints provided $ spectrum
<leonardo 1> <leonardo 2> <leonardo 3> <leonardo 4> <leonardo 5> <leonardo 6> <leonardo 7> <leonardo 8> <leonardo 9> <leonardo 10> <leonardo 11> <leonardo 12> <leonardo 13> <leonardo 14> <leonardo 15> <leonardo 16>

9. Create Gatelevel Testbench to test Mainmodule Verilog using 180 nm Technology $ vi sync_counter_gatetestbench.v 10. Check Syntax error of Only Gatelevel Testbench $ vlog sync_counter_gatetestbench.v 11. Check compatibility of Netlistfile, Gatelevel Testbench and adk.v library together to obtain Topmodule name w.r.t. 180 nm Technology $ vlog sync_counter_netlist.v sync_counter_gatetestbench.v adk.v 12. Simulate Gatelevel Testbench in Text mode using Top-module name in Vsim $ vsim c sync_counter_gatetestbench novopt run -all 13. Simulate Gatelevel Testbench in GUI/Graphical mode in Modelsim using Top-module name $ vsim sync_counter_gatetestbench novopt

load_library tsmc018_typ.syn read -format verilog sync_counter.v set input2register 2.00 set input2output 3.00 set register2output 3.00 set register2register 3.20 clock_cycle 3.2 clock set_attribute -name ARRIVAL_TIME -value "0.4" -port reset set_attribute -name ARRIVAL_TIME -value "0.4" -port down set_attribute -name ARRIVAL_TIME -value "0.4" -port up optimize write -format verilog sync_counter_netlist.v write -format sdf sync_counter.sdf report_delay > delay.rpt report_area > area.rpt exit

SKLN, RCVK