TDA8929T Datasheet Circuit Diagram

INTEGRATED CIRCUITS
DATA SHEET
TDA8929T Controller class-D audio amplifier

Preliminary specication File under Integrated Circuits, IC01 2001 Dec 11
Philips Semiconductors
Preliminary specication
Controller class-D audio amplier

CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.4 9 10 11 12 13 14 14.1 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Controller Pulse width modulation frequency Protections Diagnostic temperature Diagnostic current Start-up safety test Differential audio inputs LIMITING VALUES THERMAL CHARACTERISTICS QUALITY SPECIFICATION DC CHARACTERISTICS AC CHARACTERISTICS SWITCHING CHARACTERISTICS Minimum pulse width 15 15.1 15.2 15.3 15.4 15.5 15.6 15.7 16 17 17.1 17.2 17.3 17.4 17.5 18 19 20
TDA8929T
TEST AND APPLICATION INFORMATION Test circuit BTL application Mode pin External clock Reference designs Reference design bill of material Curves measured in reference design PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS
2001 Dec 11

1 FEATURES 3 GENERAL DESCRIPTION
TDA8929T
Operating voltage from 15 to 30 V Very low quiescent current Low distortion Fixed gain of 30 dB Single-Ended (SE) or 36 dB Bridge-Tied Load (BTL) Good ripple rejection Internal switching frequency can be overruled by an external clock No switch-on or switch-off plop noise Diagnostic input for short-circuit and temperature protection Usable as a stereo Single-Ended (SE) amplifier or as a mono amplifier in Bridge-Tied Load (BTL) Start-up safety test, to protect for short-circuits at the output of the power stage to supply lines Electrostatic discharge protection (pin to pin). 2 APPLICATIONS
The TDA8929T is the controller of a two-chip set for a high efficiency class-D audio power amplifier system. The system is divided into two chips: TDA8929T; the analog controller chip in a SO24 package TDA8926J/ST/TH or TDA8927J/ST/TH; a digital power stage in a DBS17P, RDBS17P or HSOP24 power package. With this chip set a compact 2 50 W or 2 100 W audio amplifier system can be built, operating with high efficiency and very low dissipation. No heatsink is required, or depending on supply voltage and load, a very small one. The system operates over a wide supply voltage range from 15 up to 30 V and consumes a very low quiescent current.
Television sets Home-sound sets Multimedia systems All mains fed audio systems Car audio (boosters). 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8929T SO24 DESCRIPTION plastic small outline package; 24 leads; body width 7.5 mm VERSION SOT137-1
2001 Dec 11

5 QUICK REFERENCE DATA SYMBOL General; note 1 VP Iq(tot) Gv(cl) Zi Vn(o) SVRR cs VOO Gv(cl) Zi Vn(o) SVRR VOO Note 1. VP = 25 V. supply voltage total quiescent current 15 29 45 40 35 23 25 20 PARAMETER MIN. TYP.
TDA8929T
MAX. 30 30
UNIT
V mA
Stereo single-ended conguration closed-loop voltage gain input impedance noise output voltage supply voltage ripple rejection channel separation DC output offset voltage 30 68 220 50 70 36 34 280 44 31 400 150 dB k V dB dB mV
Mono bridge-tied load conguration closed-loop voltage gain input impedance noise output voltage supply voltage ripple rejection DC output offset voltage 37 200 dB k V dB mV
2001 Dec 11

6 BLOCK DIAGRAM
TDA8929T
handbook, full pagewidth
VSS1 1
VDD1 3
R fb
20
PWM1
IN1
4 V/I 5
WINDOW COMPARATOR
21
EN1
IN1+ SGND1
24 2 mute SGND SGND 23
SW1
REL1
OSC
SGND OSCILLATOR STABILIZER 19 STAB
mute 6
MANAGER
15 22
DIAGTMP DIAGCUR
MODE
MODE SGND
TDA8929T
16 EN2
SGND SGND2 IN2+ 11 mute 8 9 V/I
SGND 13 SW2
IN2
WINDOW COMPARATOR
14
REL2
17 R fb 12 VSS2(sub) 10 VDD2 18
MGW148
PWM2
VSSD
Fig.1 Block diagram.
2001 Dec 11

7 PINNING SYMBOL VSS1 SGND1 VDD1 IN1 IN1+ MODE OSC IN2+ IN2 VDD2 SGND2 VSS2(sub) SW2 REL2 DIAGTMP EN2 PWM2 VSSD PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DESCRIPTION negative analog supply voltage channel 1 signal ground channel 1 positive analog supply voltage channel 1 negative audio input channel 1 positive audio input channel 1 mode select input (standby/mute/operating) oscillator frequency adjustment, or tracking input positive audio input channel 2 negative audio input channel 2 positive analog supply voltage channel 2 signal ground channel 2 negative analog supply voltage channel 2 (substrate) digital switch output channel 2 digital control input channel 2 digital input for temperature limit error report from power stage digital control output for enable channel 2 of power stage input for feedback from PWM output power stage channel 2 negative digital supply voltage; reference for digital interface to power stage pin for a decoupling capacitor for internal stabilizer input for feedback from PWM output power stage channel 1 digital control output for enable channel 1 of power stage digital input for current error report from power stage digital control input channel 1 digital switch output channel 1
handbook, halfpage
TDA8929T
VSS1 1 SGND1 2 VDD1 3 IN1 4 IN1+ 5 MODE 6
24 SW1 23 REL1 22 DIAGCUR 21 EN1 20 PWM1 19 STAB
TDA8929T
OSC 7 IN2+ 8 IN2 9 VDD2 10 SGND2 11 VSS2(sub) 12
MGW149
18 VSSD 17 PWM2 16 EN2 15 DIAGTMP 14 REL2 13 SW2
Fig.2 Pin configuration.
STAB PWM1 EN1 DIAGCUR REL1 SW1
19 20 21 22 23 24
2001 Dec 11

8 FUNCTIONAL DESCRIPTION
TDA8929T
The amplifier system can be switched in three operating modes via the mode select pin: Standby: with a very low supply current Mute: the amplifiers are operational, but the audio signal at the output is suppressed On: amplifier fully operational with output signal. For suppressing pop noise the amplifier will remain automatically for approximately 220 ms in the mute mode before switching to operating mode. In this time the coupling capacitors at the input are fully charged. Figure 3 shows an example of a switching circuit for driving pin MODE.
The combination of the TDA8926J and the TDA8929T produces a two-channel audio power amplifier system using the class-D technology (see Fig.4). In the TDA8929T controller device the analog audio input signal is converted into a digital Pulse Width Modulation (PWM) signal. The digital power stage (TDA8926) is used for driving the low-pass filter and the loudspeaker load. It performs a level shift from the low-power digital PWM signal, at logic levels, to a high-power PWM signal that switches between the main supply lines. A second-order low-pass filter converts the PWM signal into an analog audio signal across the loudspeaker. For a description of the power stage see the specification of the TDA8926. The TDA8926 can be used for an output power of 2 50 W. The TDA8927 should be used for a higher output power of 2 100 W. 8.1 Controller
handbook, halfpage
+5 V standby/ mute R MODE R SGND

MGW150
mute/on
The controller contains (for two audio channels) two Pulse Width Modulators (PWMs), two analog feedback loops and two differential input stages. This chip also contains circuits common to both channels such as the oscillator, all reference sources, the mode functionality and a digital timing manager. The pinning of the TDA8929T and the power stage devices are designed to have very short and straight connections between the packages. For optimum performance the interconnections between the packages must be as short as possible. Using this two-chip set an audio system with two independent amplifier channels with high output power, high efficiency (90%) for the system, low distortion and a low quiescent current is obtained. The amplifiers channels can be connected in the following configurations: Mono Bridge-Tied Load (BTL) amplifier Stereo Single-Ended (SE) amplifier.
Fig.3 Mode select switch circuitry.
2001 Dec 11
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VDDA VSSA VDDA VSS1 VDD1 1 IN1 4 23 REL1 Vi(1) IN1+ 5 SGND1 2 INPUT STAGE PWM MODULATOR 24 SW1 21 EN1 mute SGND VSSA ROSC OSC 7 OSCILLATOR MANAGER STABI 19 STAB STAB 9 22 DIAGCUR TEMPERATURE SENSOR AND CURRENT PROTECTION VSS1 VDD2 12 BOOT2 POWERUP 15 SGND SGND2 11 IN2+ 8 13 SW2 Vi(2) IN2 9 17 PWM2 R fb 12 VSS2(sub) 10 VDD2 18 VSSD 8 10 VSS1 VSS2 25 V VSSA
MGU387
VDDD VDD2 VDD1 13 5 R fb 20 PWM1 REL1 2 SW1 1 EN1 4 CONTROL AND HANDSHAKE
+25 V
TDA8929T
TDA8926J
DRIVER HIGH
BOOT1
7 DRIVER LOW OUT1
15 DIAGTMP DIAG 3
VMODE
MODE 6
MODE
mute
16 EN2
EN2 14 CONTROL AND HANDSHAKE REL2 16 SW2 17
DRIVER HIGH
11 OUT2
SGND (0 V)
INPUT STAGE
PWM MODULATOR
14 REL2
DRIVER LOW
VSSA VDDA VSSD
TDA8929T
Fig.4 Typical application schematic of the class-D system using TDA8929T and the TDA8926J.

8.2 Pulse width modulation frequency 8.3.2 DIAGNOSTIC CURRENT
TDA8929T
The output signal of the power stage is a PWM signal with a carrier frequency of approximately 300 kHz. Using a second-order LC demodulation filter in the application results in an analog audio signal across the loudspeaker. This switching frequency is fixed by an external resistor ROSC connected between pin OSC and VSS. With the resistor value given in the application diagram, the carrier frequency is typical 317 kHz. The carrier frequency can be 9 10 calculated using: f osc = ------------------ [Hz] R OSC If two or more class-D systems are used in the same audio application, it is advised to have all devices working at the same switching frequency. This can be realized by connecting all OSC pins together and feed them from an external oscillator. Using an external oscillator it is necessary to force pin OSC to a DC-level above SGND for switching from the internal to an external oscillator. In this case the internal oscillator is disabled and the PWM will switch on the external frequency. The frequency range of the external oscillator must be in the range as specified in the switching characteristics. Application in a practical circuit: Internal oscillator: ROSC connected between pin OSC and VSS External oscillator: connect oscillator signal between pin OSC and pin SGND; delete ROSC. 8.3 Protections
9
This input is intended to protect against short-circuits across the loudspeaker load. In the event that the current limit in the power stage is exceeded, pin DIAGCUR must be pulled to a LOW level. A LOW level on the diagnostic current input will immediately force the output pins EN1 and EN2 to a LOW level. The power stage will shut down within less than 1 s and the high current is switched off. In this state the dissipation is very low. Every 220 ms the controller will attempt to restart the system. If there is still a short-circuit across the loudspeaker load, the system is switched off again as soon as the maximum current is exceeded. The average dissipation will be low because of this low duty factor. The actual current limiting value is set by the power stage. Depending on the type of power stage which is used, several values are possible: TDA8926TH: limit value can be externally adjusted with a resistor; maximum is 5 A TDA8927TH: limit value can be externally adjusted with a resistor; maximum is 7.5 A TDA8926J and TDA8926ST: limit value is fixed at 5 A TDA8927J and TDA8927ST: limit value is fixed at 7.5 A.
The controller is provided with two diagnostic inputs. One or both pins can be connected to the diagnostic output of one or more power stages. 8.3.1 DIAGNOSTIC TEMPERATURE
A LOW level on pin DIAGTMP will immediately force both pins EN1 and EN2 to a LOW level. The power stage shuts down and the temperature is expected to drop. If pin DIAGTMP goes HIGH, pins EN1 and EN2 will immediately go HIGH and normal operation will be maintained. Temperature hysteresis, a delay before enabling the system again, is arranged in the power stage. Internally there is a pull-up resistance to 5 V at the diagnostic input of the controller. Because the diagnostic output of the power stage is an open-drain output, diagnostic lines can be connected together (wired-OR). It should be noted that the TDA8929T itself has no temperature protection.
2001 Dec 11

8.3.3 START-UP SAFETY TEST 8.4 Differential audio inputs
TDA8929T
During the start-up sequence, when pin MODE is switched from standby to mute, the condition at the output terminals of the power stage are checked. These are the same lines as the feedback inputs of the controller. In the event of a short-circuit of one of the output terminals to VDD or VSS the start-up procedure is interrupted and the system waits for non-shorted outputs. Because the test is done before enabling the power stages, no large currents will flow in the event of a short-circuit. This system protects against short-circuits at both sides of the output filter to both supply lines. When there is a short-circuit from the outputs of the power stage to one of the supply lines, before the demodulation filter, it will also be detected by the start-up safety test. Practical use from this test feature can be found in detection of short-circuits on the printed-circuit board. Remark: this test is only operational prior to or during the start-up sequence, and not during normal operating.
For a high common mode rejection and a maximum flexibility of application, the audio inputs are fully differential. By connecting the inputs anti-parallel the phase of one of the channels is inverted, so that a load can be connected between the two output filters. In this case the system operates as a mono BTL amplifier (see Fig.5). Also in the stereo single-ended configuration it is recommended to connect the two differential inputs in anti-phase. This has advantages for the current handling of the power supply at low signal frequencies.
TDA8929T IN1 + IN1 Vi IN2 + IN2 CONTROLLER REL1 SW1 EN1 EN2 SW2 REL2 OUT2
MGW185
OUT1
POWER STAGE
SGND
Fig.5 Mono BTL application.
2001 Dec 11
10

9 LIMITING VALUES In accordance with the Absolute Maximum Rate System (IEC 60134). SYMBOL VP VMODE(sw) Tstg Tamb Tvj Ves(HBM) PARAMETER supply voltage mode select switch voltage storage temperature ambient temperature virtual junction temperature electrostatic discharge voltage (HBM) note 1 all pins with respect to VDD (class A) 500 all pins with respect to VSS (class A1) 1000 all pins with respect to GND (class B) 2500 all pins with respect to each other (class B) Ves(MM) electrostatic discharge voltage (MM) note 2 all pins with respect to VDD (class A) 100 all pins with respect to VSS (class B) all pins with respect to each other (class B) Notes 1. Human Body Model (HBM); Rs = 1500 and C = 100 pF. 2. Machine Model (MM); Rs = 10 ; C = 200 pF and L = 0.75 H. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air 100 200 all pins with respect to GND (class B) 300 2000 referenced to SGND CONDITIONS 0 55 40 MIN.
TDA8929T
MAX. 30 5.5 +150 +85 150 +500 +1000 +2500 +2000 V V
UNIT
C C C V V V V
+100 +100 +300 +200
V V V V
VALUE 65
UNIT K/W
11 QUALITY SPECIFICATION In accordance with SNW-FQ611-part D if this device is used as an audio amplifier.
2001 Dec 11
11

12 DC CHARACTERISTICS VP = 25 V; Tamb = 25 C; measured in Fig.10; unless otherwise specied. SYMBOL Supply VP Iq(tot) Istb Offset VOO VOO output offset voltage in system on and mute delta output offset voltage in system on mute supply voltage total quiescent current standby current VMODE = 0 V note 1 15 25 20 30 PARAMETER CONDITIONS MIN. TYP.
TDA8929T
MAX. 30 30 100
UNIT
V mA A mV mV
150 80
Mode select input (pin MODE); see Figs 6, 7 and 8 VMODE IMODE Vth1+ Vth1 VMODE(hys1) Vth2+ Vth2 VMODE(hys2) VI VO(STAB) ISTAB(max) VOH VOL VIH VIL Rpu(int) input voltage input current positive threshold voltage 1 negative threshold voltage 1 hysteresis voltage 1 positive threshold voltage 2 negative threshold voltage 2 hysteresis voltage 2 note 2 VMODE = 5.5 V standby mute; note 2 mute standby; note 2 (Vth1+) (Vth1) mute on; note 2 on mute; note 2 (Vth2+) (Vth2) note 2 0 0.8 3.0 11 10 1.6 1.0 600 3.8 3.2 600 5.5 1000 2.0 4.0 15 0.8 1.5 V A V V mV V V mV
Audio inputs (pins IN1+, IN1, IN2+ and IN2) DC input voltage 0 V
Internal stabilizer (pin STAB) stabilizer output voltage mute and on; note 3 13 VSTAB 0.7 VSTAB 12 V mA
maximum current on pin STAB mute and on
Enable outputs (pins EN1 and EN2) HIGH-level output voltage LOW-level output voltage referenced to VSS VSTAB 1.6 referenced to VSS 0 no errors; note 3 note 3 0 V V
Current diagnose input (pin DIAGCUR with internal pull-up resistance) HIGH-level input voltage LOW-level input voltage internal pull-up resistance to internal digital supply V V k
Temperature diagnose input (pin DIAGTMP with internal pull-up resistance) VIH VIL HIGH-level input voltage LOW-level input voltage no errors; note 3 note 3 4 0 5.5 1.5 V V
2001 Dec 11
12
TDA8929T
SYMBOL Rpu(int)
PARAMETER internal pull-up resistance to internal digital supply
CONDITIONS
MIN. 12
TYP.
MAX.
UNIT k
Switch outputs (pins SW1 and SW2) VOH VOL VIH VIL Notes 1. The circuit is DC adjusted at VP = 15 to 30 V. 2. Referenced to SGND (0 V). 3. Referenced to VSS. 13 AC CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT HIGH-level output voltage LOW-level output voltage note 3 note 3 VSTAB 1.6 0 VSTAB 0.7 0.8 V V
Control inputs (pins REL1 and REL2) HIGH-level input voltage LOW-level input voltage note 3 note 3 10 0 VSTAB 2 V V
Stereo single-ended application; note 1 THD total harmonic distortion Po = 1 W; note 2 fi = 1 kHz fi = 10 kHz Gv(cl) SVRR closed-loop voltage gain supply voltage ripple rejection on; fi = 100 Hz; note 3 on; fi = 1 kHz; note 3 mute; fi = 100 Hz; note 3 standby; fi = 100 Hz; note 3 Zi Vn(o) input impedance noise output voltage on; Rs = 0 ; B = 22 Hz to 22 kHz on; Rs = 10 k; B = 22 Hz to 22 kHz mute; note 4 cs Gv Vo CMRR channel separation channel unbalance output signal common mode rejection ratio mute; Vi = Vi(max) = 1 V (RMS) Vi = 1 V (RMS) Po = 1 W; note 2 fi = 1 kHz fi = 10 kHz Gv(cl) closed-loop voltage gain 35 0.01 0.1 36 0.05 37 % % dB Po = 10 W; Rs = 0 29 40 45 0.01 0.1 30 55 50 55 80 68 220 230 220 70 75 0.05 31 400 1 400 % % dB dB dB dB dB k V V V dB dB V dB
Mono BTL application; note 5 THD total harmonic distortion
2001 Dec 11
13
TDA8929T
SYMBOL SVRR
PARAMETER supply voltage ripple rejection
CONDITIONS on; fi = 100 Hz; note 3 on; fi = 1 kHz; note 3 mute; fi = 100 Hz; note 3 standby; fi = 100 Hz; note 3
MIN. 36 23
TYP. 49 44 49 80 34 280 300 280 75
MAX. 500 500
UNIT dB dB dB dB k V V V V dB
Zi Vn(o)
input impedance noise output voltage on; Rs = 0 ; B = 22 Hz to 22 kHz on; Rs = 10 k; B = 22 Hz to 22 kHz mute; note 4
Vo CMRR Notes
output signal common mode rejection ratio
mute; Vi = Vi(max) = 1 V (RMS) Vi = 1 V (RMS)
1. VP = 25 V; fi = 1 kHz; Tamb = 25 C; measured in Fig.10; unless otherwise specified. 2. THD is measured in a bandwidth of 22 Hz to 22 kHz. When distortion is measured using a low-order low-pass filter a significantly higher value will be found, due to the switching frequency outside the audio band. 3. Vripple = Vripple(max) = 2 V (p-p); Rs = 0 . 4. B = 22 Hz to 22 kHz and independent of Rs. 5. VP = 25 V; fi = 1 kHz; Tamb = 25 C; measured in reference design in Fig.12; unless otherwise specified.
on
mute
standby Vth1 Vth1+ Vth2 Vth2+ VMODE

MGW334
VMODE(hys1)
VMODE(hys2)
Fig.6 Mode pin selection.
2001 Dec 11
14
TDA8929T
audio
switching VEN VSTAB VSS VMODE on 4V
2V
mute
0 V (SGND)
standby 110 ms >110 ms

MGW152
When switching from standby to mute there is a delay of 110 ms before the output starts switching. The audio signal is available after the mode pin has been set to on, but not earlier than 220 ms after switching to mute.
Fig.7 Mode pin timing from standby to on via mute.
audio
switching VEN VSTAB VSS VMODE on 4V
0 V (SGND)
standby 110 ms 110 ms

MGW151
When switching from standby to on there is a delay of 110 ms before the output starts switching. After a second delay of 110 ms the audio signal is available.
Fig.8 Mode pin timing from standby to on.
2001 Dec 11
15

14 SWITCHING CHARACTERISTICS VP = 25 V; Tamb = 25 C; measured in Fig.10; unless otherwise specied. SYMBOL Switching frequency fosc oscillator frequency ROSC = 30.0 k ROSC = 27 k; see Fig.12 fosc(r) VOSC VOSC(trip) ftrack VOSC(ext) Notes 1. Frequency set with ROSC, according to the formula in the functional description. oscillator frequency range maximum voltage at pin OSC frequency range for tracking voltage at pin OSC for tracking note 1 frequency tracking frequency tracking note 2 309 210 200 317 360 5 PARAMETER CONDITIONS MIN. TYP.
TDA8929T
MAX.
UNIT
329 600 SGND + 12 600
kHz kHz kHz V V kHz V
trip level at pin OSC for tracking frequency tracking
SGND + 2.5
2. For tracking the external oscillator has to switch around SGND + 2.5 V with a minimum voltage of VOSC(ext). 14.1 Minimum pulse width
The minimum obtainable pulse width of the PWM output signal of a class-D system, sets the maximum output voltage swing after the demodulation filter and also the maximum output power. Delays in the power stages are the main cause for the minimum pulse width being not equal to zero. The TDA8926 and TDA8927 power stages have a minimum pulse width of tW(min) = 220 ns (typical). Using the TDA8929T controller, the effective minimum pulse is reduced by a factor of two during clipping. For the calculation of the maximum output power at clipping the effective minimum pulse width during clipping is 0.5tW(min). For the practical useable minimum and maximum duty factor () which determines the maximum output power: t W(min) f osc t W(min) f osc ------------------------------- 100% < < 1 ------------------------------ 100% - 2 2 Using the typical values of the TDA8926 and TDA8927 power stages: 3.5% < < 96.5%.
2001 Dec 11
16

15 TEST AND APPLICATION INFORMATION 15.1 Test circuit
TDA8929T
The low-pass filter performs the demodulation, so that the audio signal can be measured with an audio analyzer. For measuring low distortion values, the speed of the level shifter is important. Special care has to be taken at a sufficient supply decoupling and output waveforms without ringing. The handshake with the power stage is simulated by a direct connection of the release inputs (REL1 and REL2) with the switch outputs (SW1 and SW2) of the controller. The enable outputs (EN1 and EN2) for waking-up the power stage are not used here, only the output level and timing are measured.
The test diagram in Fig.10 can be used for stand alone testing of the controller. Audio and mode input pins are configured as in the application. For the simulation of a switching output power stage a simple level shifter can be used. It converts the digital PWM signal from the controller (switching between VSS and VSS + 12 V level) to a PWM signal switching between VDD and VSS. A proposal for a simple level shifting circuit is given in Fig.9.
VDD 2 k 10 BST82 +5 V 1.33 k switch 0/12 V 20 k 74LV14 VSS

MGW154
33 PHC2300 10 nF 10 42 PWM
10 k VSS
Fig.9 Level shifter.
2001 Dec 11
17
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dbook, full pagewidth
2001 Dec 11
220 nF Vi(L) 220 nF 100 nF VSS 30 k
100 nF VSS 47 F VSS1 1 VDD1 3 R fb VDD
20
PWM1 VDD
IN1 4 IN1+ 5 SGND1 2 V/I
WINDOW COMPARATOR
21
EN1
V LEVEL SHIFTER 0/12 V 30 V/+30 V PWM 30 kHz LOW-PASS audio left audio analyzer V VSS V
24 mute SGND SGND 23
SW1
REL1
SGND VDD
OSC 7
SGND OSCILLATOR STABILIZER 19
STAB
100 nF VSS
Vp SGND
mute MODE 6
MANAGER
15 22
DIAGTMP DIAGCUR
MODE SGND
Vp
18
VMODE SGND 220 nF Vi(R) 220 nF
TDA8929T
16 EN2 V VDD
VSS
SGND SGND2 11 mute IN2+ 8 IN2 9 V/I
SGND 13 SW2 LEVEL SHIFTER 0/12 V WINDOW COMPARATOR 14 REL2 VSS 17 R fb PWM2
MGW153
PWM
30 V/+30 V
30 kHz LOW-PASS
audio right audio analyzer V
SGND
12 VSS2(sub) 47 F VSS 100 nF
10 VDD2
18 VSSD
TDA8929T
VDD
VSS
Fig.10 Test diagram.

15.2 BTL application 15.4 External clock
TDA8929T
When using the system in a mono BTL application (for more output power), the inputs of both channels must be connected in parallel. The phase of one the inputs must be inverted (see Fig.5). In principle the loudspeaker can be connected between the outputs of the two single-ended demodulation filters. For improving the common mode behavior of the filter, the configuration in Fig.12 is advised. 15.3 Mode pin
Figure 11 shows an external clock oscillator circuit. 15.5 Reference designs
The reference design for a two-chip class-D audio amplifier for TDA8926J or TDA8927J and TDA8929T is shown in Fig.12. The Printed-Circuit Board (PCB) layout is shown in Fig.13. The bill of materials is given in Table 1. The reference design for a two-chip class-D audio amplifier for TDA8926TH or TDA8927TH and TDA8929T is shown in Fig.14. The PCB layout is shown in Fig.15.
For correct operation the switching voltage on pin MODE should be de-bounced. If this pin is driven by a mechanical switch an appropriate de-bouncing low-pass filter should be used. If pin MODE is driven by an electronic circuit or microcontroller then it should remain, for at least 100 ms, at the mute voltage level (Vth1+) before switching back to the standby voltage level.
VDDA J1 120 pF R1 2 9.1 k 3 4 5 6 7 12 HEF4047B 11 10 9 8 D1 5V6 C44 220 nF on mute off 13 C3 1 14 R19 5 k mode select R20 39 k S1 MODE 6
TDA8929T
GND external clock
OSC
7
MGW155
Fig.11 External oscillator circuit.
2001 Dec 11
19
C25 470 nF
VDDA R19 39 k
mode select
VDDA R20 39 k 3 MODE 6 S1 C44 220 nF R1 VSSA 27 k C3 220 nF SGND1 GND SGND2 2 OSC
C1 C2
220 nF 220 nF VSSA
VDDD C10 560 pF R11 5.6 SW2 REL2 EN2 VDDD R24 200 k C4 220 nF D2 (7.5 V) 17 16 14 U1 12 11 OUT2 C8 15 nF
VSSD C11 560 pF R12 5.6
VDD1 VDD2 10
VSS2 VSS1 12 1 PWM2 17 SW2 13 REL2 14 EN2 16
QGND C18 1 nF
D1 (5.6 V)
on mute off
L2
OUT2
1 2
Sumida 33 H CDRH127-330 R15 24 C15 220 nF C19 1 nF QGND
4 or 8 SE
GND
U2
BOOT2 VDD1 VDD2 C7 220 nF VSS2 VSS1 C6 220 nF C14 470 nF VDDD
OUT2+
TDA8929T
19
STAB
POWERUP C5 STAB
15 9
18 11 22 5 CONTROLLER
VSSD
TDA8926J or TDA8927J
5 13
OUT2
2
VSSA VSSD C43 R10 180 pF 1 k
GND
1
220 nF DIAG
8 BTL
10 3 POWER STAGE 8
IN1+ C22 330 pF
DIAGCUR
VSSD
C17 220 nF C16 470 nF R16 24
OUT1+ QGND C20 1 nF
IN1 IN2+
4 8
21 23 24
EN1 REL1 SW1 PWM1
EN1 REL1 SW1
4 2 1
BOOT1 C9 15 nF Sumida 33 H CDRH127-330 L4 R13 5.6 C12 560 pF R14 5.6 C13 560 pF VSSD
OUT1
2 1
J5 J6 C24 470 nF R5 10 k C28 1 nF C26 470 nF R4 10 k
C23 330 pF
OUT1 7
4 or 8 SE
IN2
9 15
20
C21 1 nF QGND
OUT1+
C27 470 nF R6 10 k C29 1 nF +25 V R7 10 k
outputs
n.c. QGND C30 1 nF VDD 1 2 3 VSS C31 1 nF QGND R22 9.1 k bead L6 C33 220 nF C35 1500 F (35 V) VSSD C38 220 nF C39 220 nF L5 bead R21 10 k C32 220 nF C34 1500 F (35 V) VDDD C36 220 nF C37 220 nF L7 bead
20
VDDD VDDA C40 47 F (35 V) GND C41 47 F (35 V) VSSA
input 1 J1 QGND J2 VSS J3 J4
input 2
GND 25 V
QGND
inputs
power supply
MLD633
TDA8929T
R21 and R22 are only necessary in BTL applications with asymmetrical supply. BTL: remove R6, R7, C23, C26 and C27 and close J5 and J6. C22 and C23 influence the low-pass frequency response and should be tuned with the real load (loudspeaker). Inputs floating or inputs referenced to QGND (close J1 and J4) or referenced to VSS (close J2 and J3) for an input signal ground reference.
Fig.12 Two-chip class-D audio amplifier application diagram for TDA8926J or TDA8927J and TDA8929T.
2001 Dec 11
C16 C14
TDA8926J/27J & TDA8929T

U1 D1 C24 C34 C35 C41 L7 D2 L6 C27 C40 C25 C26
state of D art Version 21 03-2001

L5 S1 ON MUTE OFF
Out1
Out2
VDD
Silk screen top, top view
GND
VSS
In1
In2
Copper top, top view
21
L4 C6 R16 C17 C15 R15 C9 C32 C12 R13 C5 R11 C33 C10 C8 C7 C43 C13 R10 R14 U2 R12 C11 C4 C3 C39 R1 C2 R5 R19 C1 R20 C38 C36 C22 C23 C37 J5 J6 C44 R24 L2
In1
R21 R22 C28 VDD GND VSS C31 J2 J1
In2
R7 R6
Out1
C21 C20
Out2
C19
R4 C29 J3 J4
TDA8929T
C18 C30
QGND
MLD634
Silk screen bottom, top view
Copper bottom, top view
Fig.13 Printed-circuit board layout for TDA8926J or TDA8927J and TDA8929T.
VDDA R1 30 k on mute off
mode select
VDDA R2 39 k 3 6
C11 C12
100 nF 100 nF VSSA VSS(sub) SW2 REL2 EN2 VDDD R18 200 k C13 100 nF VSSA C15 180 pF D2 (7.5 V) VSSD R8 1 k EN1 REL1 SW1 PWM1 VSSD LIM 17 1, 12, 18, 20 n.c. EN1 REL1 SW1 POWERUP C14 STAB
VDDD C24 560 pF VSSD 19 16 15 13 U1 10 9 OUT2 C26 15 nF R12 5.6
VSSD C25 560 pF R13 5.6 L1 bead
VDD1 VDD2 MODE 10
VSS2 VSS1 12 1 PWM2 17 SW2 13 REL2 14 EN2 16
QGND C40 1 nF
D1 (5.6 V)
S1
C1 220 nF R3 OSC
L2 Sumida 33 H CDRH127-330 C36 470 nF VDDD R16 5.6 C38 220 nF
OUT2
1 2
4 or 8 SE
GND VSSA
27 k C2 220 nF SGND1 GND SGND2 2
U2
BOOT2 VDD1 VDD2 C27 100 nF VSS2 VSS1 C28 100 nF C29 100 nF C31 1500 F (35 V) C32 1500 F (35 V)
C41 1 nF QGND
OUT2+
TDA8929T
19
STAB
14 TDA8926TH 6 7
18 11 22
VSSD
or 11 TDA8927TH
8
OUT2
2
100 nF STAB DIAG
GND C30 100 nF

1
8 BTL
IN1+ C3 330 pF
DIAGCUR
CONTROLLER
23 POWER STAGE
VSSD C37 470 nF C33 15 nF L3 bead R15 5.6 C35 560 pF Sumida 33 H CDRH127-330 L4 R14 5.6
C39 220 nF R17 5.6
OUT1+ QGND C42 1 nF
IN1 IN2+
4 8
21 23 24
24 22 21
BOOT1
OUT1
2 1
J5 J6 C5 1 F C6 1 F R4 10 k C9 1 nF C7 1 F R5 10 k
C4 330 pF
OUT1 4
4 or 8 SE
22
input 1 J1 QGND J2 VSS
IN2
9 15
20
C43 1 nF QGND
OUT1+
C8 1 F R6 10 k C10 1 nF R7 10 k
n.c.
C34 560 pF
outputs
VDDD VSSD QGND C16 1 nF +25 V VDD 1 GND 25 V 2 3 VSS C17 1 nF QGND QGND L5 bead VDDD R9 10 k L7 bead R11 5.6 C18 100 nF C19 100 nF C22 47 F (35 V) GND R10 9.1 k bead L6 VSSD C20 100 nF C21 100 nF C23 47 F (35 V) VSSA VDDA
input 2 J3 J4 QGND
inputs
power supply
MGW232
TDA8929T
R9 and R10 are only necessary in BTL applications with asymmetrical supply. BTL: remove R6, R7, C4, C7 and C8 and close J5 and J6. Demodulation coils L2 and L4 should be matched in BTL. Inputs floating or inputs referenced to QGND (close J1 and J4) or referenced to VSS (close J2 and J3).
Fig.14 Two-chip class-D audio amplifier application diagram for TDA8926TH or TDA8927TH and TDA8929T.
dbook, full pagewidth
2001 Dec 11
C37 C31 L3
TDA8926TH/27TH TDA8929T
C22
D1 C23
C36
L1 C32 L6 L5
State of D art Version 2CTH1
Out1
Out2
S1 ON MU OFF
VDD GND VSS
In2
In1
Silk screen top, top view
Copper top, top view
23
L4 C29 C14 C30 L5 C25 R13 R12 C26 C24 R9 R10 C10 J2 C43 C42 C41 C40 C16 C17 QGND J4 J3 J1 C13 L7 R11 C9 R7 R6 C2 R3 C8 C7 R4 R5 R14 R15 C35 C34 Jan 2001 C33 U1 C28 C27 R8 C1 C15 C11 C20 R1 R2 U2 C3 C18 C4 C12 C19 C21 J6 J5 C5 C6 R17 C39 C38 R16
MGW147
Silk screen bottom, top view
Copper bottom, top view
TDA8929T
Fig.15 Printed-circuit board layout for TDA8926TH or TDA8927TH and TDA8929T.

15.6 Reference design bill of material
TDA8929T
Table 1
Two-chip class-D audio amplier PCB (Version 2.1; 03-2001) for TDA8926J or TDA8927J and TDA8929T (see Figs 12 and 13) DESCRIPTION Cinch input connectors VALUE COMMENTS 2 Farnell: 152-396 2 Augat 5KEV-02; 1 Augat 5KEV-03 PCB switch Knitter ATE 1 E M-O-M TDA8926J/27J TDA8929T 33 H 220 nF/63 V 220 nF/63 V 220 nF/63 V 220 nF/63 V 220 nF/63 V 15 nF/50 V 560 pF/100 V 470 nF/63 V 220 nF/63 V 1 nF/50 V 330 pF/50 V 470 nF/63 V 1 nF/50 V 220 nF/63 V 1500 F/35 V 220 nF/63 V 47 F/35 V 180 pF/50 V 220 nF/63 V BZX79C5V6 BZX79C7V5 27 k 24 DBS17P package SO24 package 2 Sumida CDRH127-330 3 Murata BL01RN1-A62 2 SMD1206 SMD1206 SMD1206 SMD1206 SMD1206 2 SMD0805 4 SMD0805 2 MKT 2 SMD1206 4 SMD0805 2 SMD1206 4 MKT 2 SMD0805 2 SMD1206 2 Rubycon ZL very low ESR (large switching currents) 4 SMD1206 2 Rubycon ZA low ESR SMD1206 SMD1206 DO-35 DO-35 SMD1206
COMPONENT In1 and In2
Out1, Out2, VDD, supply/output connectors GND and VSS S1 U1 U2 L2 and L4 L5, L6 and L7 C1 and C2 C3 C4 C5 C6 and C7 C8 and C9 C10, C11, C12 and C13 C14 and C16 C15 and C17 C18, C19, C20 and C21 C22 and C23 C24, C25, C26 and C27 C28, C29, C30 and C31 C32 and C33 C34 and C35 C36, C37, C38 and C39 C40 and C41 C43 C44 D1 D2 R1 2001 Dec 11 on/mute/off switch power stage IC controller IC demodulation lter coils power supply ferrite beads supply decoupling capacitors for VDD to VSS of the controller clock decoupling capacitor 12 V decoupling capacitor of the controller 12 V decoupling capacitor of the power stage supply decoupling capacitors for VDD to VSS of the power stage bootstrap capacitors snubber capacitors demodulation lter capacitors resonance suppress capacitors common mode HF coupling capacitors input lter capacitors input capacitors common mode HF coupling capacitors power supply decoupling capacitors power supply electrolytic capacitors analog supply decoupling capacitors analog supply electrolytic capacitors diagnostic capacitor mode capacitor 5.6 V zener diode 7.5 V zener diode clock adjustment resistor
TDA8929T
COMPONENT R4, R5, R6 and R7 R10 R11, R12, R13 and R14 R15 and R16 R19 R20 R21 R22 R24
DESCRIPTION input resistors diagnostic resistor snubber resistors resonance suppression resistors mode select resistor mute select resistor resistor needed when using an asymmetrical supply resistor needed when using an asymmetrical supply bias resistor for powering-up the power stage
VALUE 10 k 1 k 5.6 ; >0.25 W 24 39 k 39 k 10 k 9.1 k 200 k
COMMENTS 4 SMD1206 SMD1206 4 SMD1206 2 SMD1206 SMD1206 SMD1206 SMD1206 SMD1206 SMD1206
15.7
Curves measured in reference design
102 handbook, halfpage THD+N (%) 10
MLD627
MLD628
1
(1)
101
101
(2)
(1)
102
(3)
102
(2)
103 2 10
101
10
102 103 Po (W)
103 10
102
103
104
f i (Hz)
105
2 8 SE; VP = 25 V: (1) 10 kHz. (2) 1 kHz. (3) 100 Hz.
2 8 SE; VP = 25 V: (1) Po = 10 W. (2) Po = 1 W.
Fig.16 THD + N as a function of output power.
Fig.17 THD + N as a function of input frequency.
2001 Dec 11
25
TDA8929T
MLD629
MLD630
1
(1)
1
(1)
101
101
(2)
(2)
102
(3)
102
103 2 10
101
10
102 103 Po (W)
103 10
102
103
104
f i (Hz)
105
2 4 SE; VP = 25 V: (1) 10 kHz. (2) 1 kHz. (3) 100 Hz.
2 4 SE; VP = 25 V: (1) Po = 10 W. (2) Po = 1 W.
MLD631
MLD632
1
(1)
101
(2)
101
(1)
(2)
102
(3)
102
103 2 10
101
10
102 103 Po (W)
103 10
102
103
104
f i (Hz)
105
1 8 BTL; VP = 25 V: (1) 10 kHz. (2) 1 kHz. (3) 100 Hz.
1 8 BTL; VP = 25 V: (1) Po = 10 W. (2) Po = 1 W.
2001 Dec 11
26
TDA8929T
handbook, halfpage
25
MLD609
handbook, halfpage
100
MLD610
P (W) 20
(%)
(3)
(1) (2)
80
15
(1) (2)
60
10
40
(3)
20
0 102
101
10
103 102 Po (W)
0 0 30 60 90 120 150 Po (W)
VP = 25 V; fi = 1 kHz: (1) 2 4 SE. (2) 1 8 BTL. (3) 2 8 SE.
Fig.22 Power dissipation as a function of output power.
VP = 25 V; fi = 1 kHz: (1) 2 4 SE. (2) 1 8 BTL. (3) 2 8 SE.
Fig.23 Efficiency as a function of output power.
handbook, halfpage
200 Po
MLD611
handbook, halfpage
(2)
200 Po
MLD612
(W) 160
(2)
(W) 160
120
(1)
120
(1) (3) (3)
80
80
(4)
(4)
40
40
0 10
15
20
25
30 VP (V)
35
0 10
15
20
25
30 VP (V)
35
THD + N = 0.5%; fi = 1 kHz: (1) 1 4 BTL. (2) 1 8 BTL. (3) 2 4 SE. (4) 2 8 SE.
THD + N = 10%; fi = 1 kHz: (1) 1 4 BTL. (2) 1 8 BTL. (3) 2 4 SE. (4) 2 8 SE.
Fig.24 Output power as a function of supply voltage.
Fig.25 Output power as a function of supply voltage.
2001 Dec 11
27
TDA8929T
handbook, halfpage
MLD613
cs (dB)
handbook, halfpage
MLD614
cs (dB)
20
20
40
40
60
(1)
60
(1)
80
(2)
80
(2)
100
10
102
103
104
f i (Hz)
105
100
10
102
103
104
f i (Hz)
105
2 8 SE; VP = 25 V: (1) Po = 10 W. (2) Po = 1 W.
2 4 SE; VP = 25 V: (1) Po = 10 W. (2) Po = 1 W.
Fig.26 Channel separation as a function of input frequency.
Fig.27 Channel separation as a function of input frequency.
handbook, halfpage
45
MLD615
handbook, halfpage
45
MLD616
G (dB) 40
G (dB) 40
(1)
35
(1)
35
(2)
30
(2)
30
(3)
25
(3)
25
20
10
102
103
104
f i (Hz)
105
20
10
102
103
104
f i (Hz)
105
VP = 25 V; Vi = 100 mV; Rs = 10 k/Ci = 330 pF: (1) 1 8 BTL. (2) 2 8 SE. (3) 2 4 SE.
VP = 25 V; Vi = 100 mV; Rs = 0 : (1) 1 8 BTL. (2) 2 8 SE. (3) 2 4 SE.
Fig.28 Gain as a function of input frequency.
Fig.29 Gain as a function of input frequency.
2001 Dec 11
28
TDA8929T
handbook, halfpage
MLD617
handbook, halfpage
MLD618
SVRR (dB) 20
SVRR (dB) 20
40
(1)
40
(1)
60
(2) (3)
60
(2) (3)
80
80
100
10
102
103
104
f i (Hz)
105
100
5 4 Vripple (V)
VP = 25 V; Vripple = 2 V (p-p) with respect to GND: (1) Both supply lines in anti-phase. (2) Both supply lines in phase. (3) One supply line rippled.
VP = 25 V; Vripple with respect to GND: (1) fripple = 1 kHz. (2) fripple = 100 Hz. (3) fripple = 10 Hz.
Fig.30 SVRR as a function of input frequency.
Fig.31 SVRR as a function of Vripple (p-p).
handbook, halfpage
100 Iq
MLD619
handbook, halfpage
380
MLD620
(mA) 80
fclk (kHz)
372
60
364
40
356
20
348
0 0 10 20 30 37.5 VP (V)
340 0 10 20 30 VP (V) 40
RL = open.
RL = open.
Fig.32 Quiescent current as a function of supply voltage.
Fig.33 Clock frequency as a function of supply voltage.
2001 Dec 11
29
TDA8929T
handbook, halfpage
5 Vripple (V) 4
MLD621
MLD622
handbook, halfpage
SVRR (%) 4
3
(1)
(1)
(2)
(2)
0 102
101
10
Po (W)
102
0 10
102
103
f i (Hz)
104
VP = 25 V; 1500 F per supply line; fi = 10 Hz: (1) 1 4 SE. (2) 1 8 SE.
Fig.34 Supply voltage ripple as a function of output power.
VP = 25 V; 1500 F per supply line: (1) Po = 30 W into 1 4 SE. (2) Po = 15 W into 1 8 SE.
Fig.35 SVRR as a function of input frequency.
handbook, halfpage
10
MLD623
handbook, halfpage
THD+N (%) 1
(1)
50 Po 40
MLD624
(W)
30 101
(2) (3)
20
102
10
103 100
200
300
400
500 600 fclk (kHz)
0 100
200
300
400
500 600 fclk (kHz)
VP = 25 V; Po = 1 W in 2 8 : (1) 10 kHz. (2) 1 kHz. (3) 100 Hz.
VP = 25 V; RL = 2 8 ; fi = 1 kHz; THD + N = 10%.
Fig.36 THD + N as a function of clock frequency.
Fig.37 Output power as a function of clock frequency.
2001 Dec 11
30
TDA8929T
handbook, halfpage
150 Iq 120
MLD625
handbook, halfpage
1000
MLD626
Vr(PWM) (mV) 800
(mA)
90
600
60
400
30
200
0 100
200
300
400
500 600 fclk (kHz)
0 100
200
300
400
500 600 fclk (kHz)
VP = 25 V; RL = open.
VP = 25 V; RL = 2 8 .
Fig.38 Quiescent current as a function of clock frequency.
Fig.39 PWM residual voltage as a function of clock frequency.
2001 Dec 11
31

16 PACKAGE OUTLINE SO24: plastic small outline package; 24 leads; body width 7.5 mm
TDA8929T
SOT137-1
A X
c y HE v M A
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 w M detail X (A 3) A
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-05-22 99-12-27
2001 Dec 11
32

17 SOLDERING 17.1 Introduction to soldering surface mount packages
TDA8929T
If wave soldering is used the following conditions must be observed for optimal results: Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. For packages with leads on two sides and a pitch (e): larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 17.2 Reow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 17.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2001 Dec 11
33

17.5 Suitability of surface mount IC packages for wave and reow soldering methods
TDA8929T
SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2001 Dec 11
34

18 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
TDA8929T
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specication in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specication without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notication (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualication
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 19 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 20 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2001 Dec 11
35
Philips Semiconductors a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales ofces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Koninklijke Philips Electronics N.V. 2001
SCA73
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/01/pp36
Date of release: 2001
Dec 11
Document order number:
9397 750 08189

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INTEGRATED CIRCUITS

TDA8929T Controller class-D audio amplifier

Controller class-D audio amplier

Controller class-D audio amplier

Controller class-D audio amplier

Controller class-D audio amplier

handbook, full pagewidth

24 2 mute SGND SGND 23

SGND OSCILLATOR STABILIZER 19 STAB

SGND SGND2 IN2+ 11 mute 8 9 V/I

Fig.1 Block diagram.

Controller class-D audio amplier

VSS1 1 SGND1 2 VDD1 3 IN1 4 IN1+ 5 MODE 6

24 SW1 23 REL1 22 DIAGCUR 21 EN1 20 PWM1 19 STAB

18 VSSD 17 PWM2 16 EN2 15 DIAGTMP 14 REL2 13 SW2

Fig.2 Pin configuration.

STAB PWM1 EN1 DIAGCUR REL1 SW1

Controller class-D audio amplier

+5 V standby/ mute R MODE R SGND

Fig.3 Mode select switch circuitry.

Controller class-D audio amplier

7 DRIVER LOW OUT1

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EN2 14 CONTROL AND HANDSHAKE REL2 16 SW2 17

VSSA VDDA VSSD

Controller class-D audio amplier

Controller class-D audio amplier

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Fig.5 Mono BTL application.

Controller class-D audio amplier

MAX. 30 5.5 +150 +85 150 +500 +1000 +2500 +2000 V V

+100 +100 +300 +200

Controller class-D audio amplier

maximum current on pin STAB mute and on

Controller class-D audio amplier

PARAMETER internal pull-up resistance to internal digital supply

Mono BTL application; note 5 THD total harmonic distortion

Controller class-D audio amplier

PARAMETER supply voltage ripple rejection

TYP. 49 44 49 80 34 280 300 280 75

MAX. 500 500

output signal common mode rejection ratio

mute; Vi = Vi(max) = 1 V (RMS) Vi = 1 V (RMS)

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standby Vth1 Vth1+ Vth2 Vth2+ VMODE

Fig.6 Mode pin selection.

Controller class-D audio amplier

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switching VEN VSTAB VSS VMODE on 4V

standby 110 ms >110 ms

Fig.7 Mode pin timing from standby to on via mute.

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switching VEN VSTAB VSS VMODE on 4V

standby 110 ms 110 ms

Fig.8 Mode pin timing from standby to on.

Controller class-D audio amplier

329 600 SGND + 12 600

kHz kHz kHz V V kHz V

trip level at pin OSC for tracking frequency tracking

Controller class-D audio amplier

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VDD 2 k 10 BST82 +5 V 1.33 k switch 0/12 V 20 k 74LV14 VSS

Fig.9 Level shifter.