NATIONAL INSTITUTE OF TECHNOLOGY AGARTALA

Department of Electronics & Communication Engineering Course Structure for M. Tech, Microelectronics & VLSI Design

Microelectronics & VLSI Design

Semester 1 Subject 1. Semiconductor Device Modeling 2. VLSI Fabrication Technology 3. VLSI Circuits 4. Elective - 1 5. Elective - 2 Laboratory_I Laboratory_II L 3 3 3 3 3 0 0 15 3 3 3 3 3 0 0 0 15 Assignment 1 1 1 1 1 0 0 5 1 1 1 1 1 0 0 0 5 P 0 0 0 0 0 3 3 6 0 0 0 0 0 3 3 0 6 Cr. 4 4 4 4 4 2 2 24 4 4 4 4 4 2 2 1 25

Total
2 1. VLSI CAD System Design 2. VLSI Based Chip design for Signal/Image Processing 3. Low Power VLSI Design 4. Elective - 1 5. Elective - 2 Laboratory-III Laboratory-IV Comprehensive Viva-voce

Total
3RD SEMESTER SL 1 SUBJECT Project & Thesis L 0 0

Total
4TH SEMESTER SL 1 SUBJECT Project & Thesis

T 0 0

P 0 0

Seminar Full Full

Cr. 15 15

Total

L 0 0

T 0 0

P 0 0

Seminar Full Full

Cr. 20 20

Electives
Semester 1 Subject 1. Nanoelectronics 2. Renewable energy 3. Optoelectronics Device and Circuits 4. Semiconductor Memories 5. VLSI interconnects 1. Embedded System 2. Laser Science and Technology. 2. Testing and Verification 3. Mixed signal design 4. Hybrid Integrated Circuits 6. Technology CAD

Laboratory Laboratory-I Laboratory-II Laboratory-III Laboratory-V

Subject Microelectronics Lab Solid-State Circuit Lab VLSI Design Lab I (Cadence) VLSI Design Lab-II(Xilinx and others) (a) Digital Signal Processing Lab (b) Embedded System Lab

M.Tech Degree will be awarded only after earning atleast 80 Credits out of the following baskets:
(a) Compulsory (b) Interdisciplinary Subjects (c) Laboratory (e) Comprehensive Viva voce =24 Credit >=16 Credits =08 Credits =01 Credits

(f) Project & Thesis

= 35 Credits

1st Semester
Semiconductor Device Modeling
Review of semiconductor physics: Quantum foundation, Carrier scattering, high field effects; P- N junction diode modeling: Static model, Large signal model and SPICE models; BJT modeling: Ebers Moll, Static, large-signal, small- signal models. Gummel - Poon model. Temperature and area effects. Power BJT model, SPICE models, Limitations of GP model; Advanced Bipolar models: VBIC, HICUM and MEXTARM; Models for metal-semiconductor contacts and heterojunctions. MOSFET - quantum theory of 2DEG, MOS Transistors: LEVEL 1, LEVEL 2 ,LEVEL 3, BSIM, HISIMVEKV Models, Threshold voltage modeling. Punch through. Carrier velocity modeling. Short channel effects. Channel length modulation. Barrier lowering, Hot carrier effects. Mobility modeling, Model parameters; Analytical and Numerical modeling of BJT and MOS transistors: Introduction to various simulation techniques, Noise modeling; Modeling of heterostructure devices. MESFET -Shockley, velocity saturation and universal models. HEFT - Basic and universal models. REFERENCES 1. Solid State Electronics Device, Ben G. Streetman, Sanjay Banerjee, Pearson Prentice Hall, 2009. 2. MOSFET Modeling and & BSIM3 Users Guide, Y. Chang and C.Hu(Available in internet), Kluwer Academic Publisher. 3. Semiconductor Device Modeling with SPICE G. Massobrio and P. Antognetti, McGraw-Hill, 1998. 4. Operation and Modeling of the MOS Transistor, Y. P. Tsividis, McGraw-Hill. 5. 1. Semiconductor Devices Physics and Technology, Author: Sze, S.M.; Notes: Wiley, 1985

VLSI Fabrication Technology

Cleanroom technology - Clean room concept Growth of single crystal Si, surface contamination, cleaning & etching, Dry etching (RIE) (Laboratory Practices: Cleaning of p-type & n-type Si-wafer by solvent method & RCA cleaning) Oxidation Growth mechanism and kinetic oxidation, oxidation techniques and systems, oxide properties, oxide induced defects, charactrisation of oxide films, Use of thermal oxide and CVD oxide; growth and properties of dry and wet oxide, dopant distribution, oxide quality; (Laboratory Practices : Fabrication of MOS capacitor) Solid State Diffusion Fick's equation, atomic diffusion mechanisms, measurement techniques, diffusion in polysilicon and silicon di-oxide diffusion systems. Ion implantation Range theory, Equipments, annealing, shallow junction, high energy implementation. Lithography Optical lithography, E-beam lithography, Some Advanced lithographic techniques. Physical Vapour Deposition E-beam evaporator, CVD, PECVD, MOCVD. Metallisation - Different types of metallisation, uses & desired properties. (Laboratory Practices : Metallisation & Schottky diode fabrication)

REFERENCES 1. Semiconductor Device Technology, Author: S.K.Gandhi Notes: Wiley, 19 2. An Introduction to Semiconductor Microtechnology, Author: Morgan, D.V., and Board, K 3. The National Technology Roadmap for Semiconductors , Notes: Semiconductors Industry Association, SIA, 1994 4. Electrical and Electronic Engineering Series VLSI Technology, Author: Sze, S.M. Notes: McgrawHill International Editions.

VLSI Circuits
Module 1: CMOS logic: PMOS, NMOS and CMOS, Electrical characteristics, operation of MOS transistors as a switch and an amplifier, MOS inverter, -based design rules and layout, delay analysis, BiCMOS Design. Module 2: MOS combinational circuit: Pass transistor logic, advantages and problems in PTL, Delay through Interconnects-RC Delay models, Elmore delay model, pass-transistor logic families, MOS dynamic circuits(single and two-phase dynamic circuits),CMOS dynamic circuit (Domino and NORA Logic) Module 3: Timing strategies: clock jitter, clock skew, clock tree synthesis, rise time fall time, Set up & hold time violations, Static timing analysis (STA), Architectural design Module 4: Analog VLSI- Single stage amplifier (common source, source follower, common-gate, cascade stage), Differential Amplifier, Current mirrors, CMOS operational amplifiers (MOS and BJT)one-stage op-amps and two stage op-amps. REFERENCES: 1. Digital Integrated Circuits: A Design Perspective, Rabaey, Prentice-Hall of India Private Limited. 2. Design of Analog CMOS Integrated Circuits, Razavi, Behzad, Tata McGraw - Hill, New Delhi.

2nd Semester
VLSI CAD System Design
Module 1: Different types of VLSI design styles: Full custom, standard cell based, gate array based, programmable logic, field programmable gate arrays etc. VLSI Design flow. High level design (scheduling, allocation and binding), CAD tools for VLSI design. Module 2: Logical effort, path effort, logical effort calculation for different gates and circuits, logical effort to estimate minimum path delay, Logical effort of optimum transistor sizing, Module 3: VLSI Design automation-partitioning (problem formulation, cost function, different partitioning approach, Kernighan-Lin, Fiduccia Mattheyses and simulated annealing heuristic for partition), Floor planning( problem definition, cost function, modeling floor planning problem, approach to solve floor planning), Placement (problem definition, cost function, approach to solve floor planning), Global routing, Detailed routing-Maze routing, Channel routing. Module 4: Combinational & sequential logic synthesis issues and algorithms are discussed. Importance of VLSI testing, Fault modeling, Design for testability, Fault simulation, Test generation. REFERENCES 1. High-Level Synthesis : from Algorithm to Digital Circuit, P. Coussy and A. Morawiec, Springer, 2008. 2. I. Sutherland, B. Sproull and D. Harris, Logical Effort : Designing Fast CMOS Circuits, Elsevier 3. Algorithms for VLSI Physical Design Automatio, Sherwani, Naveed, Publisher: KAP. 4. VLSI Physical Design Automation Theory and Practice, Sait, Sadiq M; Youssef, Habib, World Scientific

VLSI Based Chip design for Signal/Image Processing

Non-linear signal processing; non-linear filters; Non-Gaussian models, Generalized Gaussian and Stable distributions, robust estimation. Medium smoothers, Rank-order filters, Weighted Median Smoother. Introduction to order statistics, joint densities, momemts. Weighted medium filtering; Link between linear and non-linear smoothers and filters, Mallows Theorem. Generalized median filtering: L-estimator; tefilter, optimality Zero-crossing (ZC) based spectral analysis, dominant frequency principle; ZC and level-crossing based signal decomposition; Auditory models. Representation of two dimensional signals; Sampling, quantization and reconstruction; Digital images; Human visual perception; Transforms : DFT, DCT, KLT, Wavelet; Filtering; Edge detection; Image restoration; Compression; Segmentation; Applications. Books of ADP: 1. Digital Signal Processing with Field Programmable Arrays, Meyer-Baese, Uwe, Springer, 2006. 2. VLSI Digital Signal Processing Systems Design Implementation, Parhi, Keshab K, JohnWiley. 3. G. R. Arce, Non-linear signal processing: A statistical approach, Wiley 2004. 4. J. Astola and P. Kuosmanen, Fundamentals of non-linear digital filtering, CRC Press, 1997. 5. B. Kedem, Time series analysis by higher order crossings, IEEE Press, 1994.

6. F. Maravasti, A unified approach to zero-crossings and non-uniform sampling,1990. Books of DIP: 1. Anil K Jain, Fundamentals of Digital Image Processing, Prentice-Hall,1989. 2. Gonzales R. C., and Woods R.E., Digital Image Processing, Addison-Wesley, 1993.

Low Power VLSI Design

Low-Power Design Methodologi es: an Overview: Why Low-Power? Basics of MOS circuits: MOS Transistor structure and device modeling,MOS inverters characteristics, delay and power estimation; Sources of power dissipation: Dynamic Power Dissipation, Static Power Dissipation and Degrees of Freedom, Parameters involved in power dissipation, switching activity and power estimation techniques. Dynamic CMOS circuits, Pass-transistor circuits. Binary Decision Diagram representation of Boolean function and low power synthesis. Supply Voltage Scaling Approaches: Device feature size scaling, Multi-Vdd Circuits, Architectural level approaches, High-level transformations, Dynamic voltage scaling and Power Management, Switched Capacitance Minimization Approaches: Hw/ Sw Tradeoff, Bus Encoding, 2s complement Vs Sign Magnitude Architectural optimization, Clock Gating , Power Gating and low power logic styles like adiabatic logic circuit, Low power BICMOS circuit design, Low Power logic synthesis and optimization. Low power physical design, Low power gate level design Leakage Power minimization Approaches such as VTCMOS, MTCMOS, DTCMOS, Transistor stacking and others. Battery-aware Synthesis and Variation tolerant design. REFERENCES: 1. K.Roy and S.C. Prasad , LOW POWER CMOS VLSI circuit design, Wiley,2000 2. Dimitrios Soudris, Chirstian Pignet, Costas Goutis, DESIGNING CMOS CIRCUITS FOR LOW POWER, Kluwer,2002 3. J.B. Kuo and J.H Lou, Low voltage CMOS VLSI Circuits,Wiley 1999. 4. A.P.Chandrakasan and R.W. Broadersen, Low power digital CMOS design, Kluwer, 1995. 5. Gary Yeap, Practical low power digital VLSI design, Kluwer,1998. 6. Abdellatif Bellaouar,Mohamed.I. Elmasry, Low power digital VLSI design,s Kluwer, 1995. 7. James B. Kuo, Shin chia Lin, Low voltage SOI CMOS VLSI Devices and Circuits. John Wiley and sons, inc 2001

Elective 1st Semester

Nanoelectronics
Shrink-down approaches: Introduction, CMOS Scaling, The nanoscale MOSFET, Finfets, Vertical MOSFETs, limits to scaling, system integration limits (interconnect issues etc.), Resonant Tunneling Transistors, Single electron transistors, new storage, optoelectronic, and spintronics devices. Quantum structures quantum wells, quantum wires and quantum dots, Single electron devices charge quantization, energy quantization, Coulomb blockade, Coulomb staircase, Bloch oscillations Heterostructure based devices Type I, II and III heterojunctions, Si-Ge heterostructure, heterostructures of III-V and II-VI compounds - resonant tunneling devices. Carbon nanotubes based devices CNFET, characteristics, Spin-based devices spin FET, characteristics. REFERENCES 1. Introduction to Nanotechnology, C.P. Poole Jr., F.J. Owens,Wiley (2003). 2: Nanoelectronics and Information Technology (Advanced Electronic Materials and Novel Devices), Waser Ranier, Wiley-VCH (2003) 3. Nanosystems, K.E. Drexler, Wiley (1992) 4. The Physics of Low-Dimensional Semiconductors, John H. Davies, Cambridge University Press, 1998 5. Mircea Dragoman and Daniela Dragoman: Nanoelectronics Principles & devices; Artech House ublishers, 2005 6. Karl Goser: Nanoelectronics and Nanosystems: From Transistors to Molecular and Quantum Devices, Springer 2005 7. Mark Lundstrom and Jing Guo: Nanoscale Transistors: Device Physics, Modeling and Simulation, Springer, 2005 8. Vladimir V Mitin, Viatcheslav A Kochelap and Michael A Stroscio:Quantum heterostructures; Cambridge University Press, 1999 9. S M Sze (Ed): High speed semiconductor devices, Wiley, 1990.

Renewable energy
Energy Scenario,Non renewable reserves and resources; renewable resources, Transformation of Energy. Solar Power: Solar thermal and Solar PV systems,Solar processes and spectral composition of solar radiation; Radiation flux at the Earths surface. Solar collectors. Types and performance characteristics. photovoltaic cell-characteristics equivalent circuit photo voltaic for battery charging.Applications. Wind Power : wind statistics, energy in the wind, aerodynamics, rotor types,forces eveloped by blades, aerodynamic models, braking systems, tower, control and monitoring system, power performance Wind driven induction generators-power circle diagram-steady state performance modeling-integration issues impact on central generation- transmission and distribution systems wind farm electrical design.

Wind-diesel systems-fuel savings-permanent magnet alternators modeling steady state equivalent circuit-self-excited induction generators integrated wind-solar Tidal Power: Wave characteristics. Conversion systems and their performance features. Application, Geothermal Power: Biological conversion of Energy Hydel Power: Micro and Mini hydros Biogas and Biomass Energy Integrated Renewable Energy systems, Energy storage techniques REFERENCES 1. John F.Walker & Jenkins. N , Wind energy Technology , John Wiley and sons, chichester, U.K,1997. 2. Van Overstraeton and Mertens R.P., Physics, Technology and use of Photovoltaics, Adam Hilger, Bristol,1996. 3. Freries LL , Wind Energy Conversion Systems, Prentice Hall, U.K., 1990.

Optoelectronics Device and Circuits

LCD, LED & Lasers. Photodetectors: PIN, APD, superlattice structure, Photo-transistor, OPFET. Optical amplifier: Fiber amplifier, Brillouin amplifier, Raman amplifier, Optical switching devices, Kerr cell and Golay cell, optical fiber and wave guiding structures.

Semiconductor Memories
1. Random Access Memory Technologies Static Random Access Memories (SRAMs): SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit OperationBipolar SRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies- Application Specific SRAMs. Dynamic Random Access Memories (DRAMs): DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Strucutures. BiCMOS DRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and ArchitectureApplication Specific DRAMs. 2.Nonvolatile Memories Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)- Bipolar PROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating- Gate EPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)- EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-Advanced Flash Memory Architecture. 3. Memory Fault Modeling, Testing and Memory Design for Testability and Fault Tolerance RAM Fault Modeling, Electrical Testing, Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing.

4. Semiconductor Memory Reliability and Radiation Effects General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory ReliabilityReliability. Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test StructuresReliability Screening andQualification. Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening. Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures. 5. Advanced Memory Technologies and High-Density Memory Packaging Technologies Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog MemoriesMagnetoresistive Random Access Memories (MRAMs)-Experimental Memory Devices. Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions. REFERENCES: 1. Ashok K.Sharma, " Semiconductor Memories Technology, Testing and Reliability ", Prentice-Hall of India Private Limited, New Delhi, 1997.

VLSI interconnects
Introduction: Moores law, Technological trends, Interconnect scaling, 3D-interconnect view; Interconnect delay modeling: Typical interconnect structure, Extraction of interconnect parameters, modeling interconnect drivers, switch-level RC model, effective capacitance modeling; Interconnection Length Prediction: Rents rule & parameter, Technology extrapolation, performance prediction, Interconnect-power & power modeling; Inductance of Interconnects: Increasing the effects of inductance, skin effect and its influence on resistance and inductance, Partial element equivalent circuit (PEEC) method; Driving interconnect for circuit speed optimization: Evolution of the speed optimization problem, logical effort method, Wire sizing, spacing. Driving RC trees; Crosstalk noise: Crosstalk configuration, DC noise margins, Reasons for high delay uncertainty, switch factor modeling of delay uncertainty, Buffer insertion for noise; Routing topology generation for speed optimization: New approaches in routing topology generation. Width optimization based on separability /monotonicity properties.

Elective 2nd Semester

Embedded Systems
Introduction to Embedded Systems: Characteristics of Embedded systems, Software embedded into a system. General ideas of Processor and Memory organization - Processor and memory selection, interfacing to Memory and I/O devices- Devices and Buses- Device Drivers and Interrupt Servicing mechanisms, Hardware software partitioning of tasks. Microcontrollers: Brief review of the 8 bit microcontroller 8051, Microchip PIC, ARM processors Programming, CPU Block diagram, Memory Organization, SFR s, Ports and Interfacing. High Speed Input, High Speed Output, Interrupts, ADC, PWM, Timers, Watch Dog Timer, Serial Port, I/O Port. -Introduction to a 16 bit micro controller 80186, Embedded C. Digital Signal Processors: DSP/16bit processor based embedded controllers; FPGA based embedded controllers. Inter-process Communication and Synchronization of Processes, Tasks and Threads: Multiple Processes in an Application - Data sharing by multiple tasks and routines- Inter Process Communication. Embedded Systems Software: Introduction to Operating Systems, Real Time Operating Systems, Study of VX works.

BOOKS:
1. Santanu Chattopadhyay, Embedded System Design 2. Peter Marwedel, Embedded Syaytem Design, Springer, Indian Ed. 3 Andrew N. Sloss, Dominic Symes, Chris Wright. ARM System Developers Guide: Designing and Optimizing System Software, Elsevier. 4. Richard Barnett, Larry OCull, Sarah Cox, Embedded C Programming and the Microchip PIC,Delmar Cengage Learning. 5. Microchip PIC manual- PIC16F87XA Datasheet. 6. 8051 microcontroller: Architecture, Programming & Applications, 1st Edition; by: Ayala, Kenneth J 7. Ajay V. DeshMukh , Microcontrollers -Theory and Applications, Tata Mc Graw Hill Publications 8. Rajkamal; Embedded Systems Architecture; Programming and Design; Tata McGraw Hill Publications. 9. Intel Manual for 80186 10 Charles Roth, Digital system design using VHDL, Indian Reprint , Thomson Book 11. P Lapsley, DSP Processor Fundamentals -Architecture and Features, Chand Publications 12. Hamid.A.Toliyat and Steven G.Campbell DSP Based Electro Mechanical Motion Control CRC Press New York, 2004. 13. Wayne Wolf, FPGA based system design , Prentice hall, 2004. 14. Real-time Systems - Jane Liu, PH 2000. 15. Real-Time Systems Design and Analysis : An Engineer's Handbook: Phillip A Laplante 16. VxWorks Programmers guide. 17. VxWorks Reference manual.

18. Embedded Software Primer - Simon, David E.

Laser Science and Technology

Monochromaticity, directionality, laser speckle, polarization, coherence, active medium, laser pumping, optical resonator, ruby, Nd-YAG lasers, gas and semiconductor lasers, modes, gain oscillation, power output, threshold, single mode operation, Q-switching, mode locking, instabilities, laser fabrication, laser applications in communication, industries, etc

Testing and Verification

Module 1: Scope of testing and verification in VLSI design process. Issues in test and verification of complex chips, embedded cores and SOCs. Module 2: Fundamentals of VLSI testing Fault models. Automatic test pattern generation. Design for testability. Scan design. Test interface and boundary scan. System testing and test for SOCs. Delay fault testing. Module 3: BIST for testing of logic and memories. Test automation. Design verification techniques based on simulation, analytical and formal approaches. Module 4: Functional verification. Timing verification. Formal verification. Basics of equivalence checking and model checking. Hardware emulation. Text Books 1. M. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing for Digital, Memory and MixedSignal VLSI Circuits", Kluwer Academic Publishers, 2000. 2. M. Abramovici, M. A. Breuer and A. D. Friedman, "Digital Systems Testing and Testable Design", IEEE Press, 1990. 3. T.Kropf, "Introduction to Formal Hardware Verification", Springer Verlag, 2000. 4. P. Rashinkar, Paterson and L. Singh, "System-on-a-Chip Verification-Methodology and Techniques", Kluwer Academic Publishers, 2001. 5. Principles of CMOS VLSI Design, Second Edition, Neil H. E. Weste and Kamran Eshraghian, Addison Wesley, 1993. 6. Principles of CMOS VLSI Design, Third Edition, Neil H. E. Weste and David Harris, Addison Wesley, 2004.

Mixed Signal Circuit Design

BiCMOS: Devices and Technology. Basic Analog and Digital Subcircuits. Current Mode Signal Processing: Current Mode circuits, Continuous Time and Sampled Data Signal Processing. ADC and DACs: Nyquist and Over sampled Converters. Analog VLSI Interconnects: Physics and Scaling of Interconnects. Statistical Modelling of Devices and Circuits. Analog Computer Aided Design. Analog and Mixed Analog and Digital Circuits Layout.

Hybrid Integrated Circuits

Monolithic, thin-film and thick-film circuits, hybridization components, circuits and Layout design, fabrication techniques. Bonding and interconnections, packaging, system partitioning. Reliability of hybrid integrated circuits and their applications.

Technology CAD
Introduction and overview; History and structures; The role of TCAD for Semiconductor technology development ; TCAD principles; Tool integration; Structure editing and mesh generation; Process technology Si, SiGe, III-V semiconductors; Process simulation general; Simulation of device characteristics; Device level simulation challenges; Introducing new device models; Heterojunction device modeling; Simulation of silicon germanium HBTs; Simulation of heterostructure FETs; Simulation of AlGaAs/ GaAs devices; VWF automation tools; Example of VWF methodology; Extraction of DC and AC SPICE model parameters; Small signal AC analysis for CMOS and bipolar transistors; Application of mixed-mode simulation; TCAD calibration procedure; Integration into the CADENCE design framework.