PIC16F84X

PIC16F8X
18-pin Flash/EEPROM 8-Bit Microcontrollers

Devices Included in this Data Sheet:
PIC16F83 PIC16F84 PIC16CR83 PIC16CR84 Extended voltage range devices available (PIC16LF8X, PIC16LCR8X)
Pin Diagrams
PDIP, SOIC
RA2 RA3 RA4/T0CKI MCLR VSS RB0/INT RB1 RB2 RB3
1
18 17 16 15 14 13 12 11 10
RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
2 3 4 5 6 7 8 9
PIC16F8X PIC16CR8X
High Performance RISC CPU Features:

Only 35 single word instructions to learn All instructions single cycle except for program branches which are two-cycle Operating speed: DC - 10 MHz clock input DC - 400 ns instruction cycle
Device PIC16F83 PIC16F84 Program Memory (words) 512 Flash 1 K Flash Data Data RAM EEPROM (bytes) (bytes) 36 68 36 68 64 64 64 64 Max. Freq (MHz) 10 10 10 10
Special Microcontroller Features:

In-Circuit Serial Programming (ICSP) - via two pins (ROM devices support only Data EEPROM programming) Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Code-protection Power saving SLEEP mode Selectable oscillator options
PIC16CR83 512 ROM PIC16CR84 1 K ROM
14-bit wide instructions 8-bit wide data path 15 special function hardware registers Eight-level deep hardware stack Direct, indirect and relative addressing modes Four interrupt sources: - External RB0/INT pin - TMR0 timer overflow - PORTB<7:4> interrupt on change - Data EEPROM write complete 1000 erase/write cycles Flash program memory 10,000,000 erase/write cycles EEPROM data memory EEPROM Data Retention > 40 years
CMOS Flash/EEPROM Technology:

Low-power, high-speed technology Fully static design Wide operating voltage range: - Commercial: 2.0V to 6.0V - Industrial: 2.0V to 6.0V Low power consumption: - < 2 mA typical @ 5V, 4 MHz - 15 A typical @ 2V, 32 kHz - < 1 A typical standby current @ 2V
Peripheral Features:
13 I/O pins with individual direction control High current sink/source for direct LED drive - 25 mA sink max. per pin - 20 mA source max. per pin TMR0: 8-bit timer/counter with 8-bit programmable prescaler
1998 Microchip Technology Inc.
DS30430C-page 1
PIC16F8X
1.0 GENERAL DESCRIPTION
The PIC16F8X is a group in the PIC16CXX family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers. This group contains the following devices: PIC16F83 PIC16F84 PIC16CR83 PIC16CR84 Table 1-1 lists the features of the PIC16F8X. A simplified block diagram of the PIC16F8X is shown in Figure 3-1. The PIC16F8X fits perfectly in applications ranging from high speed automotive and appliance motor control to low-power remote sensors, electronic locks, security devices and smart cards. The Flash/EEPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, security codes, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high performance, ease-of-use and I/O flexibility make the PIC16F8X very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions; serial communication; capture, compare and PWM functions; and co-processor applications). The serial in-system programming feature (via two pins) offers flexibility of customizing the product after complete assembly and testing. This feature can be used to serialize a product, store calibration data, or program the device with the current firmware before shipping.
All PICmicro microcontrollers employ an advanced RISC architecture. PIC16F8X devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with a separate 8-bit wide data bus. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set is used to achieve a very high performance level. PIC16F8X microcontrollers typically achieve a 2:1 code compression and up to a 4:1 speed improvement (at 20 MHz) over other 8-bit microcontrollers in their class. The PIC16F8X has up to 68 bytes of RAM, 64 bytes of Data EEPROM memory, and 13 I/O pins. A timer/ counter is also available. The PIC16CXX family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power saving. The user can wake the chip from sleep through several external and internal interrupts and resets. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup. The devices with Flash program memory allow the same device package to be used for prototyping and production. In-circuit reprogrammability allows the code to be updated without the device being removed from the end application. This is useful in the development of many applications where the device may not be easily accessible, but the prototypes may require code updates. This is also useful for remote applications where the code may need to be updated (such as rate information).
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X family of microcontrollers will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for PIC16C5X devices can be easily ported to PIC16F8X devices (Appendix B).
1.2
Development Support
The PIC16CXX family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A C compiler and fuzzy logic support tools are also available.
DS30430C-page 3
PIC16F8X
TABLE 1-1 PIC16F8X FAMILY OF DEVICES
PIC16F83 Clock Maximum Frequency of Operation (MHz) Flash Program Memory EEPROM Program Memory Memory ROM Program Memory Data Memory (bytes) Data EEPROM (bytes) Peripherals Timer Module(s) Interrupt Sources I/O Pins Features Voltage Range (Volts) Packages 10 512 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC 10 512 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC PIC16CR83 10 1K 68 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC PIC16F84 10 1K 68 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC PIC16CR84
All PICmicro Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16F8X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30430C-page 4
PIC16F8X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture. This architecture has the program and data accessed from separate memories. So the device has a program memory bus and a data memory bus. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory (accesses over the same bus). Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. PIC16CXX opcodes are 14-bits wide, enabling single word instructions. The full 14-bit wide program memory bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions execute in a single cycle except for program branches. The PIC16F83 and PIC16CR83 address 512 x 14 of program memory, and the PIC16F84 and PIC16CR84 address 1K x 14 program memory. All program memory is internal. The PIC16CXX can directly or indirectly address its register files or data memory. All special function registers including the program counter are mapped in the data memory. An orthogonal (symmetrical) instruction set makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of special optimal situations make programming with the PIC16CXX simple yet efficient. In addition, the learning curve is reduced significantly.
DS30430C-page 7
PIC16F8X
PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are twos complement in nature. In two-operand instructions, typically one operand is the working register (W register), and the other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. A simplified block diagram for the PIC16F8X is shown in Figure 3-1, its corresponding pin description is shown in Table 3-1.
FIGURE 3-1:
PIC16F8X BLOCK DIAGRAM

13 Data Bus Program Counter 8 EEPROM Data Memory RAM File Registers PIC16F83/CR83 36 x 8 PIC16F84/CR84 68 x 8 7 RAM Addr
Flash/ROM Program Memory PIC16F83/CR83 512 x 14 PIC16F84/CR84 1K x 14 Program Bus 14
8 Level Stack (13-bit)
EEDATA
EEPROM Data Memory 64 x 8
EEADR
Instruction reg 5 Direct Addr
Addr Mux 7 Indirect Addr TMR0
FSR reg RA4/T0CKI STATUS reg 8
Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Power-on Reset Watchdog Timer W reg ALU
MUX 8 I/O Ports
RA3:RA0 RB7:RB1
Timing Generation
RB0/INT
OSC2/CLKOUT OSC1/CLKIN
MCLR
VDD, VSS
DS30430C-page 8
PIC16F8X
TABLE 3-1
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16F8X PINOUT DESCRIPTION

DIP No. 16 15 SOIC No. 16 15 I/O/P Type I O Buffer Type Description
ST/CMOS (3) Oscillator crystal input/external clock source input. Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port.
MCLR
I/P
ST
RA0 RA1 RA2 RA3 RA4/T0CKI
17 18 1 2 3
17 18 1 2 3
I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST Can also be selected to be the clock input to the TMR0 timer/ counter. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 VSS VDD Legend: I= input
6 7 8 9 10 11 12 13 5 14
6 7 8 9 10 11 12 13 5 14
I/O I/O I/O I/O I/O I/O I/O I/O P P
TTL/ST (1) TTL TTL TTL TTL TTL TTL/ST (2) TTL/ST
(2)
RB0/INT can also be selected as an external interrupt pin.
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
O = output I/O = Input/Output P = power = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS30430C-page 9
PIC16F8X
4.0 MEMORY ORGANIZATION
FIGURE 4-1:
There are two memory blocks in the PIC16F8X. These are the program memory and the data memory. Each block has its own bus, so that access to each block can occur during the same oscillator cycle. The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the core are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module. The data memory area also contains the data EEPROM memory. This memory is not directly mapped into the data memory, but is indirectly mapped. That is, an indirect address pointer specifies the address of the data EEPROM memory to read/write. The 64 bytes of data EEPROM memory have the address range 0h-3Fh. More details on the EEPROM memory can be found in Section 7.0.
PROGRAM MEMORY MAP AND STACK - PIC16F83/CR83
PC<12:0> 13 CALL, RETURN RETFIE, RETLW Stack Level 1

Stack Level 8 Reset Vector User Memory Space Peripheral Interrupt Vector
0000h 0004h
1FFh
4.1
Program Memory Organization

1FFFh
The PIC16FXX has a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC16F83 and PIC16CR83, the first 512 x 14 (0000h-01FFh) are physically implemented (Figure 4-1). For the PIC16F84 and PIC16CR84, the first 1K x 14 (0000h-03FFh) are physically implemented (Figure 4-2). Accessing a location above the physically implemented address will cause a wraparound. For example, for the PIC16F84 locations 20h, 420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h will be the same instruction. The reset vector is at 0000h and the interrupt vector is at 0004h.
FIGURE 4-2:
PROGRAM MEMORY MAP AND STACK - PIC16F84/CR84
PC<12:0> 13 CALL, RETURN RETFIE, RETLW Stack Level 1

Stack Level 8 Reset Vector Peripheral Interrupt Vector

0000h 0004h
User Memory Space
3FFh
1FFFh
DS30430C-page 11
PIC16F8X
4.2 Data Memory Organization
4.2.1 GENERAL PURPOSE REGISTER FILE The data memory is partitioned into two areas. The first is the Special Function Registers (SFR) area, while the second is the General Purpose Registers (GPR) area. The SFRs control the operation of the device. Portions of data memory are banked. This is for both the SFR area and the GPR area. The GPR area is banked to allow greater than 116 bytes of general purpose RAM. The banked areas of the SFR are for the registers that control the peripheral functions. Banking requires the use of control bits for bank selection. These control bits are located in the STATUS Register. Figure 4-1 and Figure 4-2 show the data memory map organization. Instructions MOVWF and MOVF can move values from the W register to any location in the register file (F), and vice-versa. The entire data memory can be accessed either directly using the absolute address of each register file or indirectly through the File Select Register (FSR) (Section 4.5). Indirect addressing uses the present value of the RP1:RP0 bits for access into the banked areas of data memory. Data memory is partitioned into two banks which contain the general purpose registers and the special function registers. Bank 0 is selected by clearing the RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank 1. Each Bank extends up to 7Fh (128 bytes). The first twelve locations of each Bank are reserved for the Special Function Registers. The remainder are General Purpose Registers implemented as static RAM. All devices have some amount of General Purpose Register (GPR) area. Each GPR is 8 bits wide and is accessed either directly or indirectly through the FSR (Section 4.5). The GPR addresses in bank 1 are mapped to addresses in bank 0. As an example, addressing location 0Ch or 8Ch will access the same GPR. 4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (Figure 4-1, Figure 4-2 and Table 4-1) are used by the CPU and Peripheral functions to control the device operation. These registers are static RAM. The special function registers can be classified into two sets, core and peripheral. Those associated with the core functions are described in this section. Those related to the operation of the peripheral features are described in the section for that specific feature.
DS30430C-page 12
PIC16F8X
FIGURE 4-1:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 36 General Purpose registers (SRAM) 2Fh 30h Mapped (accesses) in Bank 0 EEDATA EEADR PCLATH INTCON EECON1 EECON2(1) PCLATH INTCON Indirect addr. TMR0 PCL STATUS FSR PORTA PORTB
(1)
REGISTER FILE MAP PIC16F83/CR83

File Address Indirect addr. OPTION PCL STATUS FSR TRISA TRISB
(1)
FIGURE 4-2:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch
REGISTER FILE MAP PIC16F84/CR84

File Address Indirect addr.(1) OPTION PCL STATUS FSR TRISA TRISB EECON1 EECON2(1) PCLATH INTCON 80h 81h 82h 83h 84h 85h 86h 87h EEDATA EEADR PCLATH INTCON 88h 89h 8Ah 8Bh 8Ch
80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch
Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB
AFh B0h
68 General Purpose registers (SRAM)
Mapped (accesses) in Bank 0
4Fh 50h
CFh D0h
7Fh Bank 0 Bank 1
FFh
7Fh Bank 0 Bank 1
FFh
Unimplemented data memory location; read as 0. Note 1: Not a physical register.
Unimplemented data memory location; read as 0. Note 1: Not a physical register.
DS30430C-page 13
PIC16F8X
TABLE 4-1 REGISTER FILE SUMMARY
Value on Power-on Reset Value on all other resets (Note3)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 0Ah 0Bh EECON1 EECON2 PCLATH INTCON INDF OPTION_ REG PCL STATUS (2) FSR TRISA TRISB Uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 ---- ---1111 1111 0000 0000 PD Z DC C 0001 1xxx xxxx xxxx ---1 1111 1111 1111 ---- ---EEIF WRERR WREN WR RD ---0 x000 ---- ------0 0000 INTF RBIF 0000 000x ---- ---1111 1111 0000 0000 000q quuu uuuu uuuu ---1 1111 1111 1111 ---- ------0 q000 ---- ------0 0000 0000 000u EEDATA EEADR PCLATH INTCON INDF TMR0 PCL STATUS FSR PORTA PORTB
(2)
Uses contents of FSR to address data memory (not a physical register) 8-bit real-time clock/counter Low order 8 bits of the Program Counter (PC) IRP RP1 RP0 TO PD Z DC C
---- ---xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
---- ---uuuu uuuu 0000 0000 000q quuu uuuu uuuu ---u uuuu uuuu uuuu ---- ---uuuu uuuu uuuu uuuu ---0 0000 0000 000u
Indirect data memory address pointer 0 RB7 RB6 RB5 RA4/T0CKI RB4 RA3 RB3 RA2 RB2 RA1 RB1 RA0 RB0/INT
---x xxxx xxxx xxxx ---- ---xxxx xxxx xxxx xxxx
Unimplemented location, read as '0' EEPROM data register EEPROM address register GIE EEIE T0IE Write buffer for upper 5 bits of the PC (1) INTE RBIE T0IF INTF RBIF
---0 0000 0000 000x
Low order 8 bits of Program Counter (PC) IRP RP1 RP0 TO
Indirect data memory address pointer 0 PORTA data direction register
PORTB data direction register Unimplemented location, read as '0'
EEPROM control register 2 (not a physical register) GIE EEIE T0IE Write buffer for upper 5 bits of the PC (1) INTE RBIE T0IF
Legend: x = unknown, u = unchanged. - = unimplemented read as 0, q = value depends on condition. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never transferred to PCLATH. 2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset. 3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30430C-page 14
PIC16F8X
4.2.2.1 STATUS REGISTER The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bit for data memory. As with any register, the STATUS register can be the destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). Only the BCF, BSF, SWAPF and MOVWF instructions should be used to alter the STATUS register (Table 9-2) because these instructions do not affect any status bit. Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16F8X and should be programmed as cleared. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. Note 3: When the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. The specified bit(s) will be updated according to device logic
FIGURE 4-1:
R/W-0 IRP bit7
STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
R/W-0 RP1
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 0 = Bank 0, 1 (00h - FFh) 1 = Bank 2, 3 (100h - 1FFh) The IRP bit is not used by the PIC16F8X. IRP should be maintained clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h - 7Fh) 01 = Bank 1 (80h - FFh) 10 = Bank 2 (100h - 17Fh) 11 = Bank 3 (180h - 1FFh) Each bank is 128 bytes. Only bit RP0 is used by the PIC16F8X. RP1 should be maintained clear. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (for ADDWF and ADDLW instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note:For borrow the polarity is reversed. A subtraction is executed by adding the twos complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
DS30430C-page 15
PIC16F8X
4.2.2.2 OPTION_REG REGISTER Note: When the prescaler is assigned to the WDT (PSA = 1), TMR0 has a 1:1 prescaler assignment. The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 4-1:
R/W-1 RBPU bit7
OPTION_REG REGISTER (ADDRESS 81h)

R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR reset
R/W-1 INTEDG
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled (by individual port latch values) INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to TMR0
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits

Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
DS30430C-page 16
PIC16F8X
4.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The INTCON register is a readable and writable register which contains the various enable bits for all interrupt sources.
FIGURE 4-1:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR reset
R/W-0 EEIE
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts Note: For the operation of the interrupt structure, please refer to Section 8.5. EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT Interrupt Enable bit 1 = Enables the RB0/INT interrupt 0 = Disables the RB0/INT interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 overflow interrupt flag bit 1 = TMR0 has overflowed (must be cleared in software) 0 = TMR0 did not overflow INTF: RB0/INT Interrupt Flag bit 1 = The RB0/INT interrupt occurred 0 = The RB0/INT interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
DS30430C-page 17
PIC16F8X
4.5 Indirect Addressing; INDF and FSR Registers
A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2.
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
EXAMPLE 4-2:
HOW TO CLEAR RAM USING INDIRECT ADDRESSING

0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
EXAMPLE 4-1:

INDIRECT ADDRESSING
NEXT
Register file 05 contains the value 10h Register file 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h Increment the value of the FSR register by one (FSR = 06) A read of the INDF register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).
movlw movwf clrf incf btfss goto :
CONTINUE
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-1. However, IRP is not used in the PIC16F8X.
FIGURE 4-1:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing 0 IRP 7 (FSR) 0
RP1 RP0
from opcode
bank select
location select
bank select
location select
00 00h
01
10 not used
11 00h not used
0Bh 0Ch Data Memory (3) 2Fh (1) 30h (1) 4Fh (2) 50h (2) 7Fh Bank 0 Note 1: PIC16F83 and PIC16CR83 devices. 2: PIC16F84 and PIC16CR84 devices 3: For memory map detail see Figure 4-1. Bank 1 Bank 2 Bank 3 7Fh Addresses map back to Bank 0
DS30430C-page 19
PIC16F8X
6.0 TIMER0 MODULE AND TMR0 REGISTER
edge select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The prescaler is shared between the Timer0 Module and the Watchdog Timer. The prescaler assignment is controlled, in software, by control bit PSA (OPTION_REG<3>). Clearing bit PSA will assign the prescaler to the Timer0 Module. The prescaler is not readable or writable. When the prescaler (Section 6.3) is assigned to the Timer0 Module, the prescale value (1:2, 1:4, ..., 1:256) is software selectable.
The Timer0 module timer/counter has the following features: 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock
Timer mode is selected by clearing the T0CS bit (OPTION_REG<5>). In timer mode, the Timer0 module (Figure 6-1) will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode TMR0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the T0 source
6.1
TMR0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets the T0IF bit (INTCON<2>). The interrupt can be masked by clearing enable bit T0IE (INTCON<5>). The T0IF bit must be cleared in software by the Timer0 Module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt (Figure 6-4) cannot wake the processor from SLEEP since the timer is shut off during SLEEP.
FIGURE 6-1:
TMR0 BLOCK DIAGRAM

Data bus FOSC/4 0 1 1 PSout Sync with Internal clocks (2 cycle delay) Set bit T0IF on Overflow 8 TMR0 register PSout
RA4/T0CKI pin T0SE
Programmable Prescaler 3 PS2, PS1, PS0 T0CS
PSA
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION_REG register. 2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
FIGURE 6-2:
TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC Instruction Fetch T0
PC-1
PC MOVWF TMR0
PC+1
PC+2
PC+3
PC+4 MOVF TMR0,W
PC+5 MOVF TMR0,W
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
TMR0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
T0
Instruction Executed
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
DS30430C-page 27
PIC16F8X
FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction Fetch TMR0 T0 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 PC+3 PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
MOVF TMR0,W MOVF TMR0,W
T0+1
NT0
NT0+1
Instruction Execute
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
FIGURE 6-4:
TMR0 INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 CLKOUT(3) TMR0 timer T0IF bit 4 (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC +1 Inst (PC+1) Dummy cycle Interrupt Latency(2) PC +1 0004h Inst (0004h) Dummy cycle 0005h Inst (0005h) Inst (0004h) FEh 1 FFh 1 00h 01h 02h
Inst (PC)
Note 1: T0IF interrupt flag is sampled here (every Q1). 2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode. 4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit. The TMR0 register will roll over 3 Tosc cycles later.
DS30430C-page 28
PIC16F8X
6.2 Using TMR0 with External Clock
6.2.2 TMR0 INCREMENT DELAY When an external clock input is used for TMR0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of the TMR0 register after synchronization. 6.2.1 EXTERNAL CLOCK SYNCHRONIZATION Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 Module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing.
6.3
Prescaler
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of pin RA4/T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2Tosc (plus a small RC delay) and low for at least 2Tosc (plus a small RC delay). Refer to the electrical specification of the desired device. When a prescaler is used, the external clock input is divided by an asynchronous ripple counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (plus a small RC delay) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the AC Electrical Specifications of the desired device.
An 8-bit counter is available as a prescaler for the Timer0 Module, or as a postscaler for the Watchdog Timer (Figure 6-6). For simplicity, this counter is being referred to as prescaler throughout this data sheet. Note that there is only one prescaler available which is mutually exclusive between the Timer0 Module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 Module means that there is no prescaler for the Watchdog Timer, and vice-versa. The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 Module, all instructions writing to the Timer0 Module (e.g., CLRF 1, MOVWF 1, BSF 1,x ....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.
DS30430C-page 29
PIC16F8X
9.0 INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 9-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 9-1 shows the opcode field descriptions. For byte-oriented instructions, f represents a file register designator and d represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If d is zero, the result is placed in the W register. If d is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, b represents a bit field designator which selects the number of the bit affected by the operation, while f represents the number of the file in which the bit is located. For literal and control operations, k represents an eight or eleven bit constant or literal value. The instruction set is highly orthogonal and is grouped into three basic categories: Byte-oriented operations Bit-oriented operations Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 9-2 lists the instructions recognized by the MPASM assembler. Figure 9-1 shows the general formats that the instructions can have. Note: To maintain upward compatibility with future PIC16CXX products, do not use the OPTION and TRIS instructions.
TABLE 9-1
Field
f W b k x
OPCODE FIELD DESCRIPTIONS

Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
FIGURE 9-1:
GENERAL FORMAT FOR INSTRUCTIONS

0
Dont care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 Label name Top of Stack Program Counter Program Counter High Latch Global Interrupt Enable bit Watchdog Timer/Counter Time-out bit Power-down bit Destination either the W register or the specified register file location Options Contents Assigned to Register bit field In the set of User defined term (font is courier)
Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
label TOS PC
PCLATH
GIE WDT TO PD dest [ ]
( ) <>
italics
k = 11-bit immediate value
DS30430C-page 55
PIC16F8X
TABLE 9-2
Mnemonic, Operands
PIC16FXX INSTRUCTION SET

Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS 14-Bit Opcode LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z Z Z Z Z Z Z Z Z
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
DS30430C-page 56
PIC16F8X
9.1
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Instruction Descriptions
Add Literal and W [label] ADDLW 0 k 255 (W) + k (W) C, DC, Z
11 111x kkkk kkkk The contents of the W register are added to the eight bit literal k and the result is placed in the W register.
ANDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND Literal with W [label] ANDLW 0 k 255 (W) .AND. (k) (W) Z
11 1001 kkkk kkkk The contents of W register are ANDed with the eight bit literal 'k'. The result is placed in the W register.
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Words: Cycles: Q2
Read literal k
1 1 Q1
Decode
Q3
Process data
Q4
Write to W
Q Cycle Activity:
Q2
Read literal "k"
Q3
Process data
Q4
Write to W
Example:
ADDLW
0x15 W W = = 0x10 0x25
Example
ANDLW W W
0x5F = = 0xA3 0x03
Before Instruction After Instruction
ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Add W and f [label] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z
00 0111 dfff ffff Add the contents of the W register with register f. If d is 0 the result is stored in the W register. If d is 1 the result is stored back in register f.
ANDWF f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND W with f [label] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z
00 0101 dfff ffff AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
1 1 Q1
Decode
Words: Cycles: Q2
Read register f
1 1 Q1
Decode
Q3
Process data
Q4
Write to destination
Q Cycle Activity:
Q2
Read register f
Q3
Process data
Q4
Example
ADDWF
FSR, 0 W = FSR = 0x17 0xC2 0xD9 0xC2
Example
ANDWF
FSR, 1 W = FSR = 0x17 0xC2 0x17 0x02
Before Instruction
Before Instruction
After Instruction
W = FSR =
After Instruction
W = FSR =
DS30430C-page 57
PIC16F8X
BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: 1 1 Q1
Decode
Bit Clear f [label] BCF 0 f 127 0b7 0 (f<b>) None

01 00bb bfff ffff Bit b in register f is cleared.
BTFSC f,b Syntax: Operands: Operation: Status Affected: Encoding: Description:
Bit Test, Skip if Clear [label] BTFSC f,b 0 f 127 0b7 skip if (f<b>) = 0 None
01 10bb bfff ffff If bit b in register f is 1 then the next instruction is executed. If bit b, in register f, is 0 then the next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction.
Q2
Read register f
Q3
Process data
Q4
Write register f
1 1(2) Q1
Decode
Example
BCF
FLAG_REG, 7 FLAG_REG = 0xC7
Q2
Read register f
Q3
Process data
Q4
No-Operat ion

FLAG_REG = 0x47
If Skip:
(2nd Cycle) Q1 Q2
No-Operat ion
Q3
Q4
No-Operati No-Opera No-Operat on tion ion
Example
HERE FALSE TRUE
BTFSC GOTO PC =
FLAG,1 PROCESS_CODE
Before Instruction
address HERE
After Instruction BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: 1 1 Q1
Decode
Bit Set f [label] BSF 0 f 127 0b7 1 (f<b>) None

01 01bb bfff ffff Bit b in register f is set.
f,b
if FLAG<1> = 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE
Q2
Read register f
Q3
Process data
Q4
Write register f
Example
BSF
FLAG_REG,
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS30430C-page 58
PIC16F8X
BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, Skip if Set [label] BTFSS f,b 0 f 127 0b<7 skip if (f<b>) = 1 None
01 11bb bfff ffff
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None
10 0kkk kkkk kkkk Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two cycle instruction.
Status Affected: Encoding: Description:
If bit b in register f is 0 then the next instruction is executed. If bit b is 1, then the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction.
1 1(2) Q1
Decode
Words: Q2
Read register f
1 2 Q1
Decode
Q3
Process data
Q4
No-Operat ion
Cycles: Q Cycle Activity: 1st Cycle
Q2
Read literal k, Push PC to Stack
Q3
Process data
Q4
Write to PC
If Skip:
(2nd Cycle) Q1 Q2
Q3
Q4 2nd Cycle
No-Opera tion
No-Operati No-Opera No-Operat No-Operat on tion ion ion
No-Opera No-Opera No-Operat tion tion ion
Example
HERE FALSE TRUE
BTFSC GOTO PC =
FLAG,1 PROCESS_CODE
Example
HERE
CALL
THERE
Before Instruction
PC = Address HERE
After Instruction
address HERE PC = Address THERE TOS = Address HERE+1

if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE
DS30430C-page 59
PIC16F8X
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Clear f [label] CLRF 0 f 127 00h (f) 1Z Z
00 0001 1fff ffff The contents of register f are cleared and the Z bit is set.
CLRW f Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles:
Clear W [ label ] CLRW None 00h (W) 1Z Z

00 0001 0xxx xxxx W register is cleared. Zero bit (Z) is set.
1 1 Q1
Decode
1 1 Q1
Decode
Q2
Read register f
Q3
Process data
Q4
Write register f
Q Cycle Activity:
Q2
No-Opera tion
Q3
Process data
Q4
Write to W
Example
CLRF
FLAG_REG FLAG_REG = = = 0x5A 0x00 1
Example
CLRW

FLAG_REG Z
Before Instruction
W W Z = = = 0x5A 0x00 1
After Instruction
CLRWDT Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD
00 0000 0110 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
1 1 Q1
Decode
Q2
No-Opera tion
Q3
Process data
Q4
Clear WDT Counter
Example
CLRWDT
Before Instruction
WDT counter = ? 0x00 0 1 1
After Instruction
WDT counter = WDT prescaler= TO = PD =
DS30430C-page 60
PIC16F8X
COMF Syntax: Operands: Operation: Status Affected: Encoding: Description: Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z
00 1001 dfff ffff
DECFSZ f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None
00 1011 dfff ffff
The contents of register f are decremented. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f. If the result is 1, the next instruction, is executed. If the result is 0, then a NOP is executed instead making it a 2TCY instruction.
The contents of register f are complemented. If d is 0 the result is stored in W. If d is 1 the result is stored back in register f.
1 1 Q1
Decode
Q2
Read register f
Q3
Process data
Q4
1 1(2) Q1
Decode
Q2
Read register f
Q3
Process data
Q4
Example
COMF
REG1,0 REG1 = = = 0x13 0x13 0xEC

REG1 W
If Skip:
(2nd Cycle) Q1 Q2
Q3
Q4
DECF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity:
Decrement f [label] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z

00 0011 dfff ffff Decrement register f. If d is 0 the result is stored in the W register. If d is 1 the result is stored back in register f.
No-Opera No-Operat No-Operati No-Operat tion ion on ion
Example
HERE
DECFSZ GOTO CONTINUE
CNT, 1 LOOP
Before Instruction
PC =
address HERE CNT - 1 0, address CONTINUE 0, address HERE+1
After Instruction
CNT if CNT PC if CNT PC = = = =
1 1 Q1
Decode
Q2
Read register f
Q3
Process data
Q4
Example
DECF
CNT, 1 CNT Z = = = = 0x01 0 0x00 1
Before Instruction
After Instruction
CNT Z
DS30430C-page 61
PIC16F8X
GOTO Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None
10 1kkk kkkk kkkk GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction.
INCF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z

00 1010 dfff ffff The contents of register f are incremented. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f.
Words: Cycles: Q Cycle Activity: 1st Cycle 2nd Cycle
1 2 Q1
Decode
Words: Cycles: Q2
Read literal k
1 1 Q1
Decode
Q3
Process data
Q4
Write to PC
Q Cycle Activity:
Q2
Read register f
Q3
Process data
Q4
No-Operat ion
No-Operat No-Opera No-Operat ion tion ion
Example
INCF
CNT, 1 CNT Z = = = = 0xFF 0 0x00 1
Before Instruction Example

GOTO THERE
After Instruction
PC = Address THERE
After Instruction
CNT Z
DS30430C-page 62
PIC16F8X
INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None
00 1111 dfff ffff The contents of register f are incremented. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead making it a 2TCY instruction.
IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z

11 1000 kkkk kkkk The contents of the W register is ORed with the eight bit literal 'k'. The result is placed in the W register.
1 1 Q1
Decode
Q2
Read literal k
Q3
Process data
Q4
Write to W
1 1(2) Q1
Decode
Q2
Read register f
Q3
Process data
Q4
Example
IORLW W W Z
0x35 = = = 0x9A 0xBF 1
If Skip:
(2nd Cycle) Q1 Q2
Q3
Q4
No-Opera No-Opera No-Operati tion tion on No-Operat ion
Example
HERE
INCFSZ GOTO CONTINUE
CNT, 1 LOOP
Before Instruction
PC = address HERE CNT + 1 0, address CONTINUE 0, address HERE +1
After Instruction
CNT = if CNT= PC = if CNT PC =
DS30430C-page 63
PIC16F8X
IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z
00 0100 dfff ffff Inclusive OR the W register with register f. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f.
MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move Literal to W [ label ] k (W) None

11 00xx kkkk kkkk The eight bit literal k is loaded into W register. The dont cares will assemble as 0s.
MOVLW k
0 k 255
1 1 Q1
Decode
1 1 Q1
Decode
Q2
Read literal k
Q3
Process data
Q4
Write to W
Q2
Read register f
Q3
Process data
Q4
Example
RESULT, 0
MOVLW W
0x5A = 0x5A
Example
IORWF
After Instruction
Before Instruction
RESULT = W = 0x13 0x91 0x13 0x93 1
After Instruction
RESULT = W = Z =
MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (destination) Z

00 1000 dfff ffff The contents of register f is moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected.
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity:
Move W to f [ label ] (W) (f) None

00 0000 1fff ffff Move data from W register to register 'f'.
MOVWF
0 f 127
1 1 Q1
Decode
Q2
Read register f
Q3
Process data
Q4
Write register f
1 1 Q1
Decode
Q2
Read register f
Q3
Process data
Q4
Example
MOVWF
OPTION_REG OPTION = W = 0xFF 0x4F 0x4F 0x4F
Before Instruction
After Instruction Example

MOVF FSR, 0 W = value in FSR register Z =1
After Instruction
OPTION = W =
DS30430C-page 64
PIC16F8X
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: 1 1 Q1
Decode
No Operation [ label ] None No operation None

00 0000 0xx0 0000
RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return from Interrupt [ label ] None TOS PC, 1 GIE None

00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two cycle instruction.
NOP
RETFIE
No operation.
Q2
Q3
Q4 Words:
1 2 Q1
Decode
Example
NOP
Cycles: Q Cycle Activity: 1st Cycle 2nd Cycle
Q2
No-Opera tion
Q3
Set the GIE bit
Q4
Pop from the Stack
No-Operat ion
Example
RETFIE
After Interrupt
PC = GIE = TOS 1
OPTION Syntax: Operands: Operation: Encoding: Description:
Load Option Register [ label ] None (W) OPTION

00 0000 0110 0010
OPTION
Status Affected: None

The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.
Words: Cycles: Example
1 1
To maintain upward compatibility with future PIC16CXX products, do not use this instruction.
DS30430C-page 65
PIC16F8X
RETLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None
11 01xx kkkk kkkk The W register is loaded with the eight bit literal k. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.
RETURN Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return from Subroutine [ label ] None TOS PC None

00 0000 0000 1000 Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction.
RETURN
Words: Cycles: Q Cycle Activity: 1st Cycle 2nd Cycle
1 2 Q1
Decode
Words: Cycles: Q Cycle Activity: 1st Cycle
1 2 Q1
Decode
Q2
Q3
Q4
Q2
Read literal k
Q3
No-Opera tion
Q4
Write to W, Pop from the Stack
No-Opera No-Opera Pop from tion tion the Stack No-Opera No-Opera No-Opera tion tion tion
No-Operat ion
2nd Cycle
No-Operat ion
Example
RETURN
After Interrupt
PC = TOS
;W contains table ;offset value ;W now has table value
Example
CALL TABLE

TABLE ADDWF PC RETLW k1 RETLW k2
;W = offset ;Begin table ;

RETLW kn ; End of table
Before Instruction
W W = = 0x07 value of k8
After Instruction
DS30430C-page 66
PIC16F8X
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description: Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C
00 1101 dfff ffff The contents of register f are rotated one bit to the left through the Carry Flag. If d is 0 the result is placed in the W register. If d is 1 the result is stored back in register f. C Register f
RRF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C
00 1100 dfff ffff The contents of register f are rotated one bit to the right through the Carry Flag. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f. C Register f
RLF
f,d
1 1 Q1
Decode
Words: Cycles: Q2
Read register f
1 1 Q1
Decode
Q3
Process data
Q4
Q Cycle Activity:
Q2
Read register f
Q3
Process data
Q4
Example
RLF
REG1,0 REG1 C
Example
1110 0110 0 1110 0110 1100 1100 1
RRF REG1 C
REG1,0
Before Instruction
= = = = =
Before Instruction
= = = = = 1110 0110 0 1110 0110 0111 0011 0
After Instruction
REG1 W C
After Instruction
REG1 W C
DS30430C-page 67
PIC16F8X
SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD
00 0000 0110 0011 The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 14.8 for more details.
SUBLW SLEEP Syntax: Operands: Operation: Status Affected: Encoding: Description:
Subtract W from Literal [ label ] 0 k 255 k - (W) (W) C, DC, Z 11 110x kkkk kkkk
The W register is subtracted (2s complement method) from the eight bit literal 'k'. The result is placed in the W register.
SUBLW k
1 1 Q1
Decode
Q2
Read literal k
Q3
Process data
Q4
Write to W
1 1 Q1
Decode
Example 1: Q2 Q3 Q4
Go to Sleep
SUBLW Before Instruction

W C Z = = = 1 ? ?
0x02
No-Opera No-Opera tion tion
After Instruction Example: SLEEP

W C Z = = = 1 1; result is positive 0
Example 2:
Before Instruction
W C Z = = = 2 ? ?
After Instruction
W C Z = = = 0 1; result is zero 1
Example 3:
Before Instruction
W C Z = = = 3 ? ?
After Instruction
W C Z = = = 0xFF 0; result is negative 0
DS30430C-page 68
PIC16F8X
SUBWF Syntax: Operands: Operation: Encoding: Description: Subtract W from f [ label ] 0 f 127 d [0,1] (f) - (W) (destination) 00 0010 dfff ffff SUBWF f,d SWAPF Syntax: Operands: Operation: Status Affected: Encoding: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None
00
Status Affected: C, DC, Z

Subtract (2s complement method) W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
1110
dfff
ffff
1 1 Q1
Decode
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'.
Words: Q2
Read register f
1 1 Q1
Decode
Q3
Process data
Q4
Cycles: Q Cycle Activity:
Q2
Read register f
Q3
Process data
Q4
Example 1:
SUBWF Before Instruction

REG1 W C Z = = = =
REG1,1 Example
3 2 ? ? SWAPF REG, 0
Before Instruction
REG1 = 0xA5
After Instruction
REG1 W = = 0xA5 0x5A
After Instruction
REG1 W C Z = = = = 1 2 1; result is positive 0
Example 2:
Before Instruction
REG1 W C Z = = = = 2 2 ? ?
TRIS Syntax: Operands: Operation: Encoding: Description:
Load TRIS Register [label] 5f7 (W) TRIS register f;

00
TRIS
After Instruction
REG1 W C Z = = = = 0 2 1; result is zero 1
Status Affected: None 0000 0110 0fff

The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them.
Example 3:
Before Instruction
REG1 W C Z = = = = 1 2 ? ?
Words: Cycles: Example
1 1
To maintain upward compatibility with future PIC16CXX products, do not use this instruction.
After Instruction
REG1 W C Z = = = = 0xFF 2 0; result is negative 0
DS30430C-page 69
PIC16F8X
XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR Literal with W [label] XORLW k 0 k 255 (W) .XOR. k (W) Z 11 1010 kkkk kkkk
The contents of the W register are XORed with the eight bit literal 'k'. The result is placed in the W register.
XORWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR W with f [label] XORWF f,d 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z
00 0110 dfff ffff Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
1 1 Q1
Decode
Words: Q2
Read literal k
1 1 Q1
Decode
Q3
Process data
Q4
Write to W
Cycles: Q Cycle Activity:
Q2
Read register f
Q3
Process data
Q4
Example:
XORLW Before Instruction

W =
0xAF Example
0xB5
XORWF
REG
Before Instruction
REG W = = 0xAF 0xB5
After Instruction
W = 0x1A
After Instruction
REG W = = 0x1A 0xB5
DS30430C-page 70

PIC16F84X

Încărcat de

Informații document

Descriere originală:

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

PIC16F84X

Încărcat de

Drepturi de autor:

Formate disponibile

PIC16F8X

18-pin Flash/EEPROM 8-Bit Microcontrollers

RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4

High Performance RISC CPU Features:

Special Microcontroller Features:

PIC16CR83 512 ROM PIC16CR84 1 K ROM

CMOS Flash/EEPROM Technology:

1998 Microchip Technology Inc.

Family and Upward Compatibility

1998 Microchip Technology Inc.

1998 Microchip Technology Inc.

1998 Microchip Technology Inc.

PIC16F8X BLOCK DIAGRAM

Flash/ROM Program Memory PIC16F83/CR83 512 x 14 PIC16F84/CR84 1K x 14 Program Bus 14

8 Level Stack (13-bit)

EEPROM Data Memory 64 x 8

Instruction reg 5 Direct Addr

Addr Mux 7 Indirect Addr TMR0

FSR reg RA4/T0CKI STATUS reg 8

MUX 8 I/O Ports

1998 Microchip Technology Inc.

PIC16F8X PINOUT DESCRIPTION

RA0 RA1 RA2 RA3 RA4/T0CKI

I/O I/O I/O I/O I/O

I/O I/O I/O I/O I/O I/O I/O I/O P P

RB0/INT can also be selected as an external interrupt pin.

1998 Microchip Technology Inc.

PROGRAM MEMORY MAP AND STACK - PIC16F83/CR83

PC<12:0> 13 CALL, RETURN RETFIE, RETLW Stack Level 1

Program Memory Organization

PROGRAM MEMORY MAP AND STACK - PIC16F84/CR84

PC<12:0> 13 CALL, RETURN RETFIE, RETLW Stack Level 1

Stack Level 8 Reset Vector Peripheral Interrupt Vector

User Memory Space

1998 Microchip Technology Inc.

1998 Microchip Technology Inc.

REGISTER FILE MAP PIC16F83/CR83

REGISTER FILE MAP PIC16F84/CR84

Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB

68 General Purpose registers (SRAM)

Mapped (accesses) in Bank 0

7Fh Bank 0 Bank 1

7Fh Bank 0 Bank 1

Unimplemented data memory location; read as 0. Note 1: Not a physical register.

Unimplemented data memory location; read as 0. Note 1: Not a physical register.

1998 Microchip Technology Inc.

---- ---xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx

---x xxxx xxxx xxxx ---- ---xxxx xxxx xxxx xxxx

---0 0000 0000 000x

Low order 8 bits of Program Counter (PC) IRP RP1 RP0 TO

Indirect data memory address pointer 0 PORTA data direction register

PORTB data direction register Unimplemented location, read as '0'

1998 Microchip Technology Inc.

STATUS REGISTER (ADDRESS 03h, 83h)

1998 Microchip Technology Inc.

OPTION_REG REGISTER (ADDRESS 81h)

bit 2-0: PS2:PS0: Prescaler Rate Select bits

1998 Microchip Technology Inc.

INTCON REGISTER (ADDRESS 0Bh, 8Bh)

1998 Microchip Technology Inc.

HOW TO CLEAR RAM USING INDIRECT ADDRESSING

movlw movwf clrf incf btfss goto :

11 00h not used