MOTOROlA

ISEMICO]UDUGTOR
TECHNICALDATA
MC68030

TechnicalSummary
SECOND.GENERATION
32.BITENHANCED
MICROPROCESSOR
The MC68030is a 32-bit Virtual memory microprocessorthat integr
functionalityof an MC68020core with the added capabilitiesof an
pagedmemory managementunit (MMU) and an oh-chip256-bytedat
Additionally,the MC68030is enhancedwith multipleinternaladdressi
busesas well as a more versatilebus controllerthat can supporttwo-c
accessesand one-clockburst accessesto maximizeperformance.The
struction set and addressingmode capabilitiesof the MC68020ha'
maintained,allowinga clearmigrationpath for M68000systems.For
information oD the MC68030,refer to MC68030UM/AD, MC68030Er
32-Bit Microproce.ssor User's Manual.
i
, ,

The main feature$of the Mc68030are as folfows:

o Object-CodeCompatiblewith the MC6802O
and EarlierM6S000M
cessors
. Complete32-BitNonmultiplexedAddressand Data Buses
. 16 32-BitGeneraf-Purpose
Data and AddressRegisters
. '
o Two 32-BitSupervisorStackPointersand 10 Special-Purpose
Cont
isters
. 256-ByteInstructionCache and 256-ByteData Cach:eCan Be A
Simuftaneously
o PagedMMU TranslatesAddressesin Parallelwith InstructionExe
Two'TransparentSegmentsAllow UntranslatedBlocksTo Be Defined
Systems That Transfer,LargeB'locksof Data to PredefinedAddresser
i,e,, GraphicsApplications
PipelinedArchitecturewith IncreasedParallelismAllows Accessesfr
InternalCachesto Occur in Parallelwith Bus Transfersand Instrucl
ExecutionTo Be Overlapped

This documentcontainsinformationon a new product.Specifications

and informationhereinare subjectto changewit

MOTOROLA MSMOO,FAIIfiILV
REFERENCE
MANUAL 3-211
 EnhaneedBusControllerSupportsAsynchronous BusCycles,{th
ree'clc
minimurn),Synchronous (two
Bus Cycles, clocksminimum),'and Br
(onecockminumum),alf to the Physical
DataTransfers AddressSpac
Memoriesand Peripherals
DynamicBusSizingSupports8/16-132-Bit
CompleteSupportfor Coprocessors In
with the M68000Coprocessor
face
fnternalStatusIndication
for HardwareEmulationSupport
o 4-GbyteDirectAddressing
Range
o lmplemented ThatAllowsCMOSi
in Motorola'sHCMOSTechnology
HMOS(High-Density
NMOS)GatesTo BeCombined
for MaximumSpt
Low Power,and SmallDieSize
Processor
SpeedsBeyond 20 MHz

INTRODUCTION
The MC68030is an integratedprocessorthat incorporatesthe capab
the MC68020microprocessor,the memory managementstructuredei
the MC68851paged memory managementunit (PMMU),data cacht
structioncache,and an irnprovedbus controlleron one VLSIdevice.lt m
the 32-bit registersavailablewith the entire M68000 Family as wel
32-bitaddressand data paths,rich instructionset,versatileaddressing
and flexiblecoprocessorinterfaceprovidedwith the MC68020.Inaddir
internal operationsof this integratedprocessorare designedto op
parallel,allowing rnultipleinstructionsto be executedconcurrently.I
instructionexecutionto proceedin parallelwith accessesto the internal
the on-chipMMU, and the bus controller.

The MC68030fulfy supports the nonmultiplexedasynchronousbur

MC68020as well as the dynamic bus sizing mechanismthat allows
cessor to transfer operands to or from external devices while auton
determiningdeviceport sizeon a cycle-by-cycle basis.ln additionto tl
chronous bus, the MC68030also supports a fast synchronousbus for
cachesand fast memories.Furthermore,the MC68030bus is capableof
up to four long words of data in a burst mode compatiblewith DRA
that have burst capability.Burst mode can reduce(up to 50 percent)1
necessaryto fetch the four long words. The four fong words are usedt
the on-chip instructionand data cachesso that the hit ratio of the c
improved and the averageaccesstime for operandfetchesis minimi:

3-212 ]Y6EPOFAMILY REFERENGE

MANUAL MOTOROLA
 The blockdiagramshown in Figure1 depictsthe major sectionsof the
and illustratesthe autonomousnatureof these blocks.The bus contrr
sistsof the addressand data pads,the multiplexersrequiredto support
bus sizing,and a microbuscontrollerthat schedulesthe bus cycleson
of priority.The micromachinecontainsthe executionunit and all relate
logic.Microcodecontrol is providedby a modifiedtwo-levelstore of m
and nanoROMcontainedin the micromachine.Programmedlogicarra
are used to provide instructiondecode and sequencinginformatior
struction pipe and other individualcontrol sectionsprovide the secol
code of instructionsand generatethe actual control signals that res
decodingand interpretationof nanoROMand microRoM informatior

The instructionand data cache blocks operate independentlyfrom tl

the machine,storing informationread by the bus controllerfor future
very fast accesstime. Eachcacheresideson its own addressbus and
allowing simuftaneousaccessto both" Both cachesare organizedas
64 long-word entries (256 bytes)with a line size of four fong words.
,,cacheusesa write-throughpolicywith programmablewrite allocation
misses.

Finally,the MMU controlsthe mapping of addressesfor page sizes

from 256 bytesto 32K bytes.Mapping information stored in descriptor
in translationtablesin memorythat are automaticallysearchedby the I
on demand. Recentlyused descriptorsare maintained in a 22-entry
sociativecache cafled the addresstranslationcache (ATC),allowing
translationand other MC68030functionsto occursimultaneously. Adc
the MC68030containstwo transparenttranslation registersthat can
to define a one-to-onemapping for two segments ranging in size
Mbytes to 2 Gbytes each.

MOTOROLA M68O(pFAMITYREFERENCE
TVIANUAI 3-213
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crr=
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o

3-214 MSMN .FA]UIILYREFERENGE

MANUAL MOTOROLA
 PROGRAMMING
MODEL
As shown in the programmingmodels (seeFigures2 and 3), the MC68
1632-bitgeneral-purposeregisters,a32-bit program counter,two 32-b|
visor stack pointers,a 16-bitstatus register,a 32-bitvector base regis
3-bit alternatefunctioncode registers,two 32-bitcachehandling(addr
control) registers,two 64-bit root pointer registersused by the MMU,
translationcontrol register,two 32-bittransparenttranslationregister
16-bitMMU statusregister.RegistersD0-D7 are used as data register
and bit field (t to 32 bit), byte (g bit), word (16 bit), long-word |.32t
quad-word (6+ bit) operations.RegistersA0-AO and the user, interrr
masterstackpointersare addressregistersthat may be used as softwa
pointersor base addressregisters.In addition,the addressregisters
used for word and long-word operations.All 16 general-purposer
(D0-D7,A0- A7l can used as index registers.

16 15

D1

DATA
REGISTERS

16 15

A1

ADDRESS
REGISTERS

I
I
A7 STACK
USER
I
(usP) POINTER

PROGRAM
COUNTER

CONDITION
CODE
REGISTER

Figure 2. User ProgrammingModel

MOTOROLA M68OOO
FAMILYREFERENCE
MANUAL 3-215
 15
A7 NTERRTJPT
(rsP) POINTER
STACK
15
AT MASTER
(MSP) PONNTER
STACI(

(ccR) STAruS
REGISTER

vBR Xi!lt*!.rsTER

sFc R,NCTtr)N
ALTEtr.IATE
DFC CODEREGISIERS

COI,IIROL
CACHE
REGISTER

CACIIEADDRESS
REGISTER

CPUROOT
POINTER
REGISTER

ROOT
SUPERVISOR
POINTER
REGISTER

CONTROL
TMNST.ATION
REGISTER

TMNSLANON
TRANSPARENT
REGISTER
O

TMNSTATION
TRANSPARENT
1
REGISTER

MMUSTATUS
REGISTER

Figure 3. Supervisor Programming Model Supplement

The status register(see Figure4l containsthe interrupt priority mas

bits)as well as the followingconditioncodes:extend(X),negate(N),:
overflow (V), and carry (C).Additionalcontrol bits indicatethat the pr
is in the trace mode (T1 or T0), supervisor/user
state (S),and masterlir
state(M).

3-216 M68OOO MANUAL

FAMILYREFERENCE MOTOROLA
 SYSTEM
BYTE USERBYTE

14

\-\t/.-/
--/
_l INTERRUPT
PRIORITY
MASK

( EXTEND
I
I NEGAnVE
coNDrTroN
--"coDES
/ zERo
1
ovERFLow
I
t cARRY

Figure4. StatusRegister

All microprocessors of the M68000Familysupport instructiontracing (via the

T0 statusbit in the MC68030) whereeachexecutedinstructionis followed by
a trap to a user-definedtraceroutine.The MC68030also has the capabilityto
traceonly on change-of-flow (branch,juffip, subroutinecall and
instructions
return,etc.)usingthe T1 statusbit. Thesefeaturesare important for software
programdevelopment and debug.

Sincethe vector baseregisteris usedto determinethe run-timelocatio

exceptionvectortable in memory,it supportsmultiplevectortablesithr
processor task can properlymanageexceptionsindependentof each

The M68000Familyprocessorsdistinguishaddressspacesas supervis

program/data,and CPU space.Thesefive combinationsare specifiec
function code pins (FC0/FC11FC2\ during bus cycles,indicatingthe pi
addressspace.Using the function codes,the memory subsystem(ha
can distinguish between superuisoraccessesand user accessesas
program accesses,data accesses,and CPU space accesses.Additioni
system softwarecan configurethe on-chip MMU so that supervisor/ur
ilege checkingis performed by the addresstranslationmechanism,
lookup of translationdescriptorscan be differentiatedon the basisof 1
code. To support the full privilegesof the supervisor,the alternate1
code registersallow the supervisorto specifythe function code for ar
by appropriatelypreloadingthe SFC/DFCregisters.

The cache registersallow supervisorsoftware manipulationof the

instruction and data caches.Control and status accessesto the cac
providedby the cachecontrofregister(CACR);the cacheaddressregister
specifiesthe addressforthose cachecontrolfunctionsthat requirean i

MOTOROTA M68OM FAMILYREFERENCE

MANUAL 3-217
 All MMU registers(CRP,SRP,TC, TT0, TT1, and MMUSR) are acces
the supervisoronly. The centralprocessorunit (cpu) root pointer co
descriptorfor the first pointer to be used in the translationtable se
page descriptorspertainingto the current task. lf the supervisorroot
enable (SRE)bit of the translationcontrol registeris set, the supervi
pointeris usedas a pointerto the transfationtablesfor all supervisor?r
lf the SREbit is clear,this registeris unused,and the CPUroot pointer
for both supervisorand user translations.The translationcontrol regis
figuresthe table lookup mechanismto be used for afl table searches
as the pagesizeand any initialshiftof logicaladdressrequiredbythe og
system,In addition,this registerhas an enablebit that enablesthe Ml
transparenttranslationregisterscan be usedto definetwo transparentrn
for transferringlarge blocksof data with untranslatedaddresses.Fini
MMU statusregister(MMUSR)containsstatusinformationrelatedto a
addresstransfationand the resultsgeneratedby the PTESTinstructir
informationcan be usefulin locatingthe causeof an MMU fault.

DATATYPESANDADDRESSING
MODES
Seven basic data types are supportedby the MC68030:
1. Bits
2. Bit Fields(Stringof consecutivebits, 1-32 bits long)
3. BCDDigits (Packed:2 digits/byte,Unpacked:1 digiUbyte)
4. Byte Integers(8 bits)
5. Word Integers(16 bits)
6. Long-WordIntegers(32 bits)
7. Ouad-WordIntegers(04 bits)
In addition,operationson other data types,such as memory addressel
word data,etc., areprovidedin the instructionset.The coprocessorme(
allows direct support of ffoating-pointdata types with the MC68881/tV
floating-pointcoprocessorsas well as specializeduser-defineddata ty
fu nctions.

The 18 addressingmodes listedin Table l includenine basictypes:

1. RegisterDirect
2. RegisterIndirect
3. RegisterIndirectwith fndex
4. Memory Indirect
5. ProgramCounterIndirectwith Displacement
6. ProgramCounterIndirectwith Index
7. ProgramCounterMemory Indirect
8. Absolute
9. lmmediate

3-218 M68OOO
FAMILYREFERENCE
MANUAL MOTOROLA
 Theregisterindirectaddressing modessupportpostincrement, predec
offset,and indexing.Thesecapabilitiesare particularlrT
usefulfor f
advanced datastructures commonto sophisticated andhi
applications
languages. The programcounterrelativemodealso has indexand o
pabilities;this addressingmode is generallyreq$iredto supportf
independent software.In additionto theseaddressingmodes,the t!
providesdataoperandsizingandscaling;thesefeaturesprovideperfr
enhancements for the programmer.

Table 1. Addressing Modes

RegisterDirect
AddressingModes Syrtax I
DataRegisterDirect Dn
AddressRegisterDirect An
;t
RegisterIndiree
AddressRegister ndirect (An)
AddressRegister ndirectwith Postincrement (An)+
Addressgegjster ndirectwith Predecrement - (An)
AddressRegister ndirectwith Displacement (dt6,An)

RegisterIndirectwith Index
AddressRegisterIndirectwith Index(8-BitDisplacement) (dg,An,Xn)
AddressRegisterIndirectwith Index(BaseDisplacement) (bd,An,Xn)
MemoryIndirect
Memory Indirect Postindexed ([bd,Anl,Xn,od)
Memory IndirectPreindexed ([bd,An,Xn],od]

ProgramCounterlndirectwith Displacement (dt6,PC)

ProgramCounterIndirectwith Index
PCIndirectwith Index(8-BitDisplacement) (dg,PC,Xn)
'PC (bd,PC,Xn)
lndirectwith Index(BaseDisplacement)
ProgramCounterMemory Indirect
PCMemoryIndirectPostindexed ([bd,PC],Xn,od)
PCMemoryIndinectPreindexed ([bd,PC,Xn],od]

Absolute
Abs0luteShort (xxx).W
AbsoluteLong (xxx).1

lmmediate #(data)

NOTES:
Dn - DataRegister,D0-D7
An - AddresJRegister,A0-A7
dg, d16 * A,twos-complement or sign-extended displacement; addedas partof the
effectiveaddresscalculation; sizeis 8 (dg)or 16 (dtO)bits;when omitted,
'.assemblers use a valueof zero.
Xn'='Address or dataregisterusedasan indexregister;form is Xn.SIZE*SCALE,
whereSIZEis .W or .L (indicates indexregiste,size)and SCALEis 1, 2, 4,
or I (indexregisteris multipliedby SCALE);use of SIZEand/orSCALEis
optional.
bd: A:twos-complernent basedisplacement; when present,sizecan be 16 or
32 bits.

MOTOROLA II'IANUAL
M68U}OFAMILYREFEREI$CE 3-219
 Tabfe1. AddressingModes(continued)
od = Outer displacement,added as part of effectiveaddresscalculationafter
any menlgfyindirection;use is optionalwith a sizeof 16 or 32 bits.
PC= ProgramCounter
(data)= lmmediatevalueof 8, 16,or 32 bits
()=EffectiveAddress
I I = Useas indirectaccessto long-wordaddress.

INSTRUCTION
SETOVERVIEW
The MC68030instruction set is listed in Tabfe 2. Each instruction,v
exceptions,operateson bytes,words, and long words, and most inst
can use any of the 18 addressingmodes.The MC68030is upward sou
object-codecompatiblewith the M68000Familybecauseit supportsafl
tions of previbusfamify members.Includedin this set are the bit fiek
t i o n s , b i n a r y - c o d e dd e c i m a l s u p p o r t , b o u n d s c h e c k i n g ,o d d i t i o r
conditions,and additionalmultiprocessingsupport (CAS and CAS2
tions)offeredby the MC68020.Thenew instructionssupportedby the M
a subset of the instructionsintroducedby the MC68851PMMU, are
communicatewith the MMU. For detailedinformationon the Mc68030
tion set, refer to M68000 PM/AD, M68000Programmer's ReferenceM,

Table2. InstructionSet
Mnemonic Description Mnemonic Desqiption
ABCD Add Decimalwith Extend tCAS Compareand SwapOperands
ADD Add cAs2 Compareand SwapDualOperands
ADDA Add Address CHK CheckRegisterAgainstBound
ADDI Add lmmediate CHK2 CheckRegisterAgainstUpperand
ADDQ :AddOuick LowerBounds
ADDX Add with Extend CLR Cleai
AND LogicalAND CMP Compare
ANDI LogicalAND lmmediate CMPA CompareAddress
ASL.ASR ArithmeticShift Left and Riqht CMPI Comparelmmediate
Bcc BranchGonditionalfy CMPM CompareMemoryto Memory
BCHG Test Bit and Change CMP2 CompareRegisterAgainstUpper
BCLR Test Bit and Cfear and LowerBounds
BFCHG Test Bit Fieldand Change DBcc TestCondition,Decrement and
BFCLR Test Bit Fieldand Clear Branch
BFEXTS SignedBit FieldExtract DIVS,DIVSL SignedDivide
BFEXTU UnsignedBit FieldExtract DIVU,DIVUL UnsisnedDivide
BFFFO Bit FieldFind Firstone EOR LogicalExclusve OR
BFINS Bit FieldInsert
EORI LogicalExclusve OR lmmediate
BFSET Test Bit Fieldand Set
EXG ExchangeRegsters
BFTST Test Bit Fiefd
EXT,EXTB Sisn Extend
BKPT Breakpoint
BRA Branch ILLEGAL T a k e l l l e q a l I n s t r u c t i o nT r a p
BSET Test Bit and Set JMP Jump
BSR Branchto Subroutine JSR Jump to Subroutine
BTST Test Bit

3-220 IT,168000
FAIffitY REFERENCE
MANUAI MOTOROLA
 Table2. lnstructionSet (Continuedl

Mnemonic Description' Mnemonic Description

LEA Load EffectiveAddress PFLUSH FlushEntry(ies)in the ATC
LINK Linkand Allocate PFTUSHA FlushAll Entriesin the ATC
LSL,LSR LoqicalShift Leftand Riqht PLOADR, LoadEntry into the ATC
PLOADW
MOVE Move
PMOVE Move to/from MMU Registers
MOVEA Move Address
PMOVEFD Move to/from MMU Registerswith
MOVECCR Move ConditionCodeRegister
FlushDisable
MOVESR Move StatusRegister
PTESTR, Test a LogicalAddress
MOVEUSP Move UserStackPointer PTESTW
MOVEC
MOVEM
MOVEP
MOVEO
MoveControlRegister
Move MultipleRegisters
Move Peripheral
Move Ouick
RESET ResetExternalDevices
ROL,ROR RotateLeft and Right
ROXL,ROXR Rotatewith ExtendLeft and Right
RTD Returnand Deallocate
I
MOVES Move AlternateAddressSpace
RTE Returnfrom Exception
MULS SignedMultiply
RTR Returnand RestoreCodes
MULU . UnsignedMultiply
RTS Returnfrom Subroutine
NBCD Negate Decimal with Extend
SBCD SubtractDecimalwith Extend
N E G. Negate
Scc Set Conditionally
NEGX Negate with Extend
STOF Stop
NOP No Operation
SUB Subtract
NOT Looical Comolement
SUBA SubtractAddress
OR LogicalInclusiveOR SUBI Subtractlmmediate
oRl LogicalInclusiveOR lmmediate SUBO SubtractOuick
oRrccR LogicalInclusiveOR lmmediateto SUBX Subtractwith Extend
ConditionCodes SWAP Swap ReqisterWords
ORISR LogicalInclusiveOR lmmediateto TAS Test Operandand Set
Status,Reqister TRAP Trap
PACK PackBCD TRAPcc TrapConditionally
PEA PushEffectiveAddress TRAPV Trap on Overflow
TST Test Operand
UNLK Unlink
UNPK UnpackBCD

CoprocessorInstructions
cpBCC I BranchConditionally cpRESTOREI RestoreInternalStateof Coproces
cpDBcc lTest CoprocessorCondition, sor
Decrementand Branch cpSAVE I SaveInternalStateof Coprocessor
coGEN I CoprutessorGeneralInstruction cpScc I Set Conditionally
TRAPcc lTrap Conditionall

MOTOROIA NfrAflt'A1
REFERENCE
ilFS(ru}FAMTLY 3-221
 IN$TRUCTI.Of\|
ASIDDATACACHES
Studies'have:shownthht typical programsspend most of their execut
in a few main routines.ortight loops.This phenomenor,known as lo
reference,has an impacton program performance.The MC68010taker
advantageof this phenomenonwith the loop mode of operationtha:
usedwith the DBccin'struction. The MC68030takesfurther advantager
technologyto providethe systemwith two o'n-chipcaches,one for inst
and one for data. '

MC68O3O
CACHEGOALS
Similarto the MC68020, therewere two primarydesigngoalsfor t
microprocessorcaches.The first desig,ngoal was to reducethe pr
ternal bus activityeven more than whit *as accomplishedwith ih
The second design goal was to increaseeffectiveCPU throughp
memory sizesor sfower memoriesincreasedaverageaccesstime
a high-speedcachebetweenthe processorand the restof the meff
the effectivememory accesstime becomes:
tacc- h*tcachs* (t - h)*text
where tacc is the effectivesystemaccesstime, tcacheis the cache,
text is the accesstime of the rest of the system, ond h is the hit
percentageof time that the data is found in the cache.Thus,for:a'g
design,two MC68030on-chip cachesprovide an even more subx
perforrnanceincreaseover that obtainablewith the MC68O20 instru
Alternately,slower and less expensivememories can be used ft
procbssorperfoimanCe.

The throughput increasein the MC68030is gained in three way

MC68030cachesare accessedin lesstime than is requiredfor extern
providing improvement in the accesstime for items residing in
Second,the burstfilling of the cachesallows instructionand dita'
found in th'e on-chip:cachesthe first time they are accessedbt
m a c h i n e ,m i n i m i z i n gt i m e r e q u i r e dt o b r i n g t h o s e i t e m s i n t o t h e r
filling lowersthe averageaccesstime for itemsfound in the cachese
Third,the autonomousnatureof the cachesallows instructionstre
data fetches,and a third externalaccessto occur simultaneouslyv
tion execution.Forexample,if the MC68030requiresboth an instruc
accessand an externalperipheralaccessand if the instructionis
the on-chipcache,the peripheralaccessproceedsunimpededrathei
queuedbehindthe instructionfetch.lf a data operandis also reql
residentin the data cache,it can also be accessedwithout hinderin

3-222 LY.RgtrEREHbEMA NI'AL

IUI68{X}$-#AMI MOTOROLA
 accessor the externalperipheral
instruction Theparallelis
access.
intothe MC68030 alsoallowsmultipleinstructionsto executecon
(thosethat do not requireany
that severalinternalinstructions
cesses)canexecutewhilethe processor is performingan externi
a previousinstruction.

INSTRUCTION
CACHE
The MC68030instructioncache is a 256-bytedirect-mappedcach
as 16 lines consistingof four long words per line. Each long w
pendentlyaccessible, yielding64 possibleentries,with addressbit
the correctword during an access.Thus, each line has a tag fielt
24 addressbits, the FC2(supervisor/user) value, four valid bits (c
long-wordentry),and the four long-wordentries(seeFigure5).Thr
cache is automaticallyfilled by the MC68030whenevera cache r
using the burst transfercapability,up to four long words can be
burstoperation.The cachescan not be manipulateddirectlyby the I
exceptby the use of the CACR,which providescacheclearingand
clearingfacilities.The cachescan also be enabled/disabled by t
Finally,the system hardwarecan disablethe on-chip cachesat
assertingof the mls signal.

MOTOROLA M68OOO MANUAL

FAMILYREFERENCE 3-223
 A A A A A A A AA A A A A A A A A A A A A A A A
3 . . . 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 ACCESS
0 0 ADDESS
1 3 2 1 0 9 8 7 56 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

DATAFROIT
IIISTRrcNON
CACT{E
DATABt.|S
DATATOllrlsTRtCTpf,l
CAC}EHOI.OI{G REGISIER
CAO{ECONTROL
LOGIC

CACHESIZE= A[ (LOf,lcWORDS]
UNESIZE= 4 (LONG WORDS)
SETSIZE= 1

Figure5. On-GhipInstructionCacheOrganization

DATACACHE
The organizationof the data cache (see Figure6) is similar to th
struction cache.However,the tag is composed of the upper 24 a
the four valid bits, and all three function code bits, explicitlysp
address space associatedwith each line. The data cache emplt
through policywith programmablewrite allocationof datawrites i.
hit occurs on a write cycfe, both the data cache and the externa
updatedwith the new data. lf a write cyclegeneratesa cachemiss,
device is updated,and a new data cacheentry can be replacedor .
that address,dependingon the stateof the write-allocate(WAl bit i

3-224 1I[68{POFAMILY REFERENCE

MANUAT MOTOROLA
 A A A A A AA A A A A A A A A AA A A A A A A A A
3 o . . 2 2 2 2 1 11 1 1 11 1 1 1 0 0 0 0 0 0 0 0 00 ACCESS
ADDRESS
1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 87 ' 65 1 3 2 1 0

10F16
SETECT

DATAFROMDATA
CACfiIE
DATABUS

DATATOEXECITIONUI,ST

cAcHECOI.|TROL
LOGTC

CACrES|ZE= 64(LOt'tcWOHDS)
LINESIZE= 4 (LOlrlG
WORDS)
SETSIZE= 1

Figure6, On-ChipDataCacheOrganization

MECHANISM
TRANSFER
OPERAND
The MC68030offers three different mechanismsby which data can b
ferred into and out of the chip. Asynchronousbus cycles,compatible'
asynchronousbus on the MC68020,can transferdata in a minimum
clock cycles; the amount of data transferredon each cycle is determ
the dynamic bus sizing mechanismon a cycle-by-cyclebasis with t
transfer and size acknowledge(DffiK) signals.Synchronousbus cy
terminatedwith the synchronoustermination(STEffi) signaland alwal
fer 3}-bits of data in a minimum of two clock cycles,increasingthe bt
width availablefor other bus masters,thereforeincreasingpossibleperfo
Burstmode transferscan be usedto fill linesof the instructionand datt
when the MC68030assertscache burst request (mFm). After comple
first cyclewith ffiffi, subsequentcyclesmay acceptdata on every clc
where SIFffi is asserteduntil the burst is compfeted.Use of this m

MOTOROLA M68(X}OFAMILYREFERENCE
MANUAL 3-225
 further increasethe availablebus bandwidthin systemsthat use I
page,nibble,or static-columnmode operation.

ASYNCHRONOUS
TRANSFERS

Though the MC68030has a full 32-bit data bus, it offers the ability
maticallyand dynamicallydownsizeits bus to 8 or 16 bits if peripheral
are unabfeto accommodatethe entire 32 bits. This featureallows ,
grammer to write code that is not bus-widthspecific.For example,lor
(32 bit) accessesto peripheralsmay be used in the code; yet, the MCOI
transferonly the amount of data that the peripheralcan manageat or
This featureallowsthe peripheralto defineits port sizeas 8, 16,or 32bi
and the MC68030will dynamicallysize the data transferaccordingl'
multiple bus cycleswhen necessary.Hence,programmersare not req
program for each deviceport sizeor know the specificport size before
hardwaredesignershave the flexibilityto choosehardwareimpleme
regardlessof softwareimplementations.

The dynamic bus sizing mechanismis invoked by ffieKx and occr

cycle-by-cycle basis.For example,if the processoris executingan ins
that requiresthe readingof a long-wordoperand,it will attemptto rea(
duringthe first bus cycleto a long-wordaddressboundary.lf the port rt
that it is 32 bits wide, the MC68030latchesall 32 bits of data and cont
the port respondsthat it is 16 bits wide, the MC68030latchesthe 16 v
of data and runs a secondcycleto obtainthe remaining16 bits of dat
bit port is handledsimilarlybut has four bus read cycles.Eachport is
the assignmentto particularsectionsof the data bus. However,the tV
has no restrictionsconcerningthe alignmentof operandsin memor
word operandsneed not be alignedto long-wordaddressboundarie:
misaligneddata requiresmultiplebus cycles,the MC6S030automatica
t h e m i n i m u m n u m b e ro f b u s c y c l e s I. n s t r u c t i o nm
s u s t s t i l lb e a l i g n e d
boundaries.

The timing of asynchronousbus cyclesis also determinedby the ass€

the DSACKxsignalson a cycle-by-cycle basis.lf the D9A,eKxsignalsa
1.5clocksafterthebeginningof the bus cycle(withthe appropriatesetu
t h e c y c l et e r m i n a t e si n t h e m i n i m u m a m o u n to f t i m e ( c o r r e s p o n d i n g
c|ockcyc|estota|).Thecyc|ecanbe|engthenedbyde|ayingffiKx(ef|
insertingwait statesin one-clockincrements)until the devicebeing a
is able to terminatethe cycle.This flexibilitygivesthe processorthe a
communicatewith devicesof varyingspeedswhile operatingat the fast
possiblefor each device.

3-226 M68OOO
FAMILYREFERENCE
MANUAL MOTOROLA
 The asynchronous transfermechanismallowsexternalerrorsto
uponthe assertion of bus error(BERE),or allowsindividualbus
retrledwith the simultaneous assertion,of
BEffi'and FI,AF.

SYNCHRONOUS
TRANSFERS
Synchronousbus cyclesare terminated by assertingS-TEHM, which a
icbfly indicatesthat the port size is 32 bits. Since ttris is asynchronou
two-clock-cycle bus accessescan be performedif the signal is valid or
Afterthe beginning of the bus cyclewith the appropriatJsetuptime. H
the bus cycle may be lengthenedby delayingSTEFM.(insertf ng wait r
one-clockincrements)until the devicebeing accessedis able to termir
cycle.Additionally,these cyclesmay be aUorteOupon the assertionc
or they may be retriedwith the simultaneousassertionof BEREand I

BURSTREADCYCLES
The MC68030providessupport for burst filling of its on-chip instruc
data caches,adding to the overall system performance.The on-chig
are organizedwith a line sizeof four long words with one tag for the f
words in a line. Since localityof referenceis presentto some degree
programs,filling of all four entries,when a singleentry rnissesqan b{
tageous,especiallyif the time spent filling the additionalentries is I
When the caches,areburst filled, data can be latched by the proeesr
little hs one clockfor each32 bits.

Burst readcyclescan be performedonly when the MC68ffi0reques

(wittrtheassertionofffio}and'.on|ywhenthefirstcyc|eisa.sr7nc|
cycleas previouslydescribed. lf the,cacheburst'acknowledge'(CBAC
is valid at the appropriate
tlme in the synchronous bus cycle,the pr
keepsthe'original/F, DS,'RAff,address,functioncode,and sizeoutl
sertedand latches32,bitsfrom the data bus at the end of 'eachsub
clockcyclethat,hasSFEFNIa$serted, Thisprocedureeontinuesuntiltl
is's'omplete (theentireblockhasbeentransferred), BEm is'asserted il
orafterffi.M,thecacheinhibitin(ffi}inputisasserted,orthemt
is negated.

MOTOROLA M68OOO
FAfr'IILYREFERENCE
MANUAL 3'227
 EXCEPTIONS
Thetypesof exceptions andthe exceptionprocessing
sequence
ar
in the followingparagraphs.

TYPESOF EXCEPTIONS
Exceptionscan be generatedby either internalor externalcauser
nally generatedexceptionsare interrupts-, bus error (BEffi), and re
Interruptsqle requestsfrom peripheraldevicesfor processoractic
BERRand RESETafe used for accesscontrol and processorrestal
nally generatedexceptionscome from instructions,addresserrorr
breakpoints.The TRAP, TRAPcc,TRAPVcc,cpTRAPcc,CKH, CKI
instructionscan all generateexceptionsas partof instructionexecur
behaveslike a very high-priority,internallygeneratedinterruptwl
processed.The other internallygeneratedexeptionsare causedI
structions,instructionfetchesfrom odd addresses,and privilegr
Finally,the MMU can generateexceptionswhen it detectsan invdlir
in the addresstranslationcache (ATC)and an accessto the co
addressis attempted,
' : or when it is unableto locatea valid transl
i..

addressin the translationtables.

EXCEPTION
PROCESSING
SEOUENCEI
Exeeption processing occurs in four steps, During the first step,
copy is made of the statusregister,After the copy is made,the speci
state bits in the status registerare changed.The S bit is set, putt
'c€ssor 'intothe supenrisorstate.,Also,the T1 and T0 bits are negatr
the exception handler to execute unhi,nderedby tracing. For th
interrupt exceptions,the interrupt prnior.ity
mask is also updated.
,{
'ln the tecond step, the vector number of the exception is dete
interrupts,the,vectornumber is obtainedby a processorread that
as an interrupt acknowledgecycle. For coprocessor-detectedexc
vector n"urnberis included in the coprocessorexception primitiv
For a,fl'other exceptions,internallogic providesthe vector number,
number is then used to generatethe addressof the exception.ve(

The third step is to savethe currentprocessorstatus.The exception

is createdand filled on the currentsupervisorstack.To minimize
of machine state that is saved,vorious stack frame sizesare usel
the processorstate,dependingon the type of exceptionand whert

g-228 FAMILYREFERENGE
MOSOOO MANUAL MOTOROLA
 during instructionexecution.ff the exceptionis an interrupt and thr
set, the M bit is then cleared,and the short four-word exception stt
that is saved on the master stack is also saved on the interrupt str
exceptionis a reset,the M bit is simply cleared,and the resetvector is I

The MC68030providesthe same extensionsto the exeption stackinl

as the MC68020.lf the M bit is set, the masterstackpointer (MSP)is
all task-relatedexceptions.When a nontask'relatedexceptionoccur
interrupt),the M bit is cleared,and the interruptstack pointer (lSP
This feature allows all the task's stackarea to be carriedwithin a si
cessor control block, and new tasks can be initiated by simply reloi
masterstackpointerand settingthe M bit. I
The fourth and last step of exceptionprocessingis the samefor all el
The exceptionvector offset is determined by mutliplying the vecto
by four. This offset is then added to the contents of the vector bas,
(VBR)to determine the memory address of the exception vector.
program counter is fetched from the exceptionvector. The instructi
addressgiven in the exceptionvector is fetched,and normal instrr
coding and executionis started.

STATUSand REFILL
The MC68030provides the m=f|.JS and FEFttt signals to ider
microsequencer activityassociatedwith the processingof p-ipeline(
bus cyclesare independentlycontrolledand scheduledby the bu
informationconcerningthe processingstateof the microsequencel
able by monitoring bus signalsby themselves.The internalactivi
by the ST-A=ru'S and FEFffi signals include instructionboundarie
ceptionconditions,when the microsequencer has halted,and instr
line refills.SfNfLiS and FEm track only the internalmicroseque
and are not directly relatedto bus activity. :

MEMORYMANAGEMENT
ON-CH}P UNIT
The full addressing range of the MC68030is 4 Gbytes (4,294,967,296
,however,most MC68030systemsimplementa sm&llerphysicalmemon
theless,by using virtual memory techniques,the systemcan be madetc
to have the full 4 Gbytesof physicalmemory availableto each user p
In a similar fashion, a virtual systern provides user-programaccess
devicesnot physicallypresent in the system,such as tape drives, disl

MOTOROTA M68qN FAMILYREFERENCE

MANUAL 3-229
 printers,or termlnals.The MC68030MMU providessupportfoia vit
and virtual rnemory. ln addition,'itprotectssupervisorareasfrom
user programsand provideswrite protectionon a pagebasis.All th
is provided,aswell as maximum performancebecauseaddress
occur in parallelwith other processoractivities.
:

IMPLEMENTATION
DEMAND-PAGED :
A typical MC68030system with a large addressingrange provid
physicalmemory that can be accesseddir
amount of l'righ-speed
processorwhile maintainingan image of a much largervirtual
secondarystoragedevicessuch as large-capacity disk drives.Wl
cessor attemptsto accessa location in the virtual memory ma[
residentin physicalmemory, the accessto that locationis teml
pendedwhiie the necessarydata is fetchedfrom secondarystoragr
in physicalmemory;the suspendedaccessis then eitherrestartedo

A pagedsystemis one in which the physicalmemory is subdivider

'(untranslated)
sized blocks called page frames and the logical ad
of a task is divided into pages having the same size as the page
operatingsystemcontrolsthe allocationof pagesto page frames
data on a page basisas it is neededfrom the secondarry storage
MC68030memory managementschemeis calleda demand imp
becausea processdoes not need to specify in advancethe requi
its logicaladdressspace.An accessto _.logicaladdressis interp
syslem as a requestfor the correspondingpage.

The MCOS030 MMU employsthe same addresstranslationmech

ducedby the MC68851PMMU,with possiblepagesizes,rangingfrc
to 32K bytes.
'
:
TRANSI.^ATION
MECHANISM
Since logical-to-physical addresstranslation!s the most frequen
operationof'the MC68030MMU, this task,hasbeen'optimizedand
autonomously.The MMU initiatesaddresstranslationby searc
{a page descriptor}in the on:chipar
addresstransfation i,nfor'mation
lation cache(ATC).Th,eATC is a very fast fully associativecache t
stores recentlyused page,descriptors.lf the descriptordoes not
ATC,then the MMU requestsexternalbus cyclesof the bus contro
the transJationtables in physical memory. After being located,l
scriptor is loaded into the ATC, and the address is ,correctlytrans
accessif no exceptionconditionsare encountered.

3-230 MAilIUAT
FAMILY HEFERENCE
M68OOO MOTOROLA
 The statusof the pagein questionis easilymaintainedin the transl
When a page must be brought in from a secondarystoragedevi
entry can signalthat this descriptoris invalidso that the table s(
in an invaliddescriptorbeing loadedinto the ATC. In this way, t
the page is aborted,and the processorinitiatesbus error exceptior
for this address.The operatingsystemcan then controlthe allocat
p a g ei n p h y s i c a m
l e m o r ya n d c a n l o a dt h e p a g ed u r i n gt h e b u s e r
routine.

ADDRESSTRANSLATIONCACHE
An integralpart of the translationfunction previouslydescribed
memory that stores recentlyused logical-to-physical addresstri
formation or page descriptors.This cache consistsof 22 entries
associative.The ATC comparesthe logicaladdressand function
incomingaccessagainstits entries.lf one of the entriesmatches,t
and the ATCsendsthe physicaladdressto the bus controller,whic
the externalbus cycle(providedno hit occurredin the instructionor
for the access).

The ATC is composedof three major components:the content-

memory (CAM)containingthe logicaladdressand functioncode
to be comparedagainstincominglogicaladdresses, the physicala
containingthe physicaladdressassociatedwith a particularCAI\
the controlsectioncontainingthe entry replacementcircuitrythat
the replacementalgorithm(a variationof the leastrecentlyused i

TRANSLATION
TABLES
The translationtables supportedby the MC68030have a tree strr
mizingthe amountof memorynecessary to set up the tablesfor mo
sinceonly a portionof the completetree needsto exist at any or
root of a translationtabletree is pointedto by one ortwo root poin
t h a t a r e p a r to f t h e p r o g r a m m e r ' m
s o d e l : t h eC P Ua n d s u p e r v i s o rI .
at the higherlevelsof the tree (pointertables)containpointersto r
Entriesat the leaf level(pagetables)containpagedescriptors. The
for performingtable searchesuses portionsof the logicaladdres
f o r e a c h l e v e lo f t h e l o o k u p . A l la d d r e s s e si n t h e t r a n s l a t i o nt a b l r
physicaladdresses.

MOTOROLA M68OOO
FAMILYREFERENCE
MANUAL 3-231
 Figure 7 illustratesthe translationtable structure.Severaldeterminanl
detailedtable structureare softwareselectable.The first level of looku
table normallyusesthe fun6fioncodesas an index,but this may be sup
if desired.In addition,up to 15 of the logicaladdresslinescan be ign,
the purposesof the table searching,The number of levelsin the table
by the logicaladdresscan be set from one to four, ?nd up to 15 logical
bits can be used as an index at each level.A major advantageto us
tree structureforthe translationtablesis the abilityto deallocatelargeI
of the logicaladdressspacewith a singleentry at the higher levelsof t
Additionally,portionsof the tree itselfmay resideon a secondarystorag
or may not exist at all until they are requiredby the system.

I*.*-TABLES

:
I
I

I
rrt-lI
r-l
-
t l

I,^.,TABLES

l_t ,|

Figure 7. MMU Translation Table Structure

The entries in the translationtables contain status informationperta

the pointersfor the next level of lookup or for the pagesthemselves
bits can be used to designatecertainpagesor blocksof pagesas sup
only, write-protected,or noncachable.lf a page is marked as nonci
accesseswithin the page will not be cachedby the instructionor data
andthecacheinhibitout(ffi)signa|isassertedforthoseacce
addition,the MMU automatically maintainshistoryinformationfor the I
and pagesin the descriptorsvia the used (U) and modified(M) bits.

3-232 M68OOO
FAMILYREFERENCE
MANUAL MOTOROLA
MMUTNSTRUCTTPNS
/
TheMMUinstructions supportedby the MC68030, the PMOVE, PTI
PFLUSH,and PFLUSHA instructions,
arecompletely compatible v
respondinginstructionsintroducedby the MC68851PMMU.V
MC68851requiredthe coprocessor interfaceto executeits instr
MC68030 MMU instructions executejust like all other CPUinstr
MMU instructionsareprivileged (canbe executed by the supervis
aresummarized as follows:
PMOVE Usedto movedatato or from MMU registers.
PTEST Takesan addressand functioncode and searchesthe ATC or the
translationtablesfor the correspondingentry.The resultsof the
searchare availablein the MMU statusregister(MfUUSR) and are
often useful in determiningthe causeof a fault.
PLOAD Takesan addressand functioncode and searchesthe translation
tables for the correspondingpage descriptor.lt then loads the
ATC with the appropriateinformation.
PFLUSH Flushesthe ATC by function code or function code and I
address.
PFLUSHA Flushesall ATC entries.

TRANSPARENT
TRANSI.^ATION
Two transparenttranslation registersare provided on the MC68(
allow portions of the logical addressspaceto be transparentlyr
accessedwithout correspondingentries residentin the ATC. Eac
used to define a range of logicaladdressesfrom 16 Mbytesto 2
a base address and a mask. All addresseswithin these ranges
mapped,and protectionis providedonly on a basisof read/writei
code.

INTERFACE
COPROCESSOR
The coprocessorinterfaceis a mechanismfor extendingthe instructic
the M68000Family.The interfaceprovidedon the MC68030is the sarn(
on the MC68020.Examplesof these extensionsare the additionof spt
data operandsfor the existing data types or, for the caseof floating p{
inclusion of new data types and operationsimplementedby the M
MC68882floating-point coprocessors.

MOTOROLA M68(XNFAMILYREFERENGE
MANUAL 3-233
 Coprocessors are dividedinto two types by their bus-utilization
characl
A DMA coprocessorcan controlthe bus independentof the main pr(
A non-DMAcoprocessorcanrrotcontrolthe bus. Both coprocessortype
the same protocoland main processorresources.lmplementationof i
cessoras a DMA or non-DMAis basedprimariVon coprocessor bus bat
requirements,performance,and cost.

The communicationprotocolbetweenthe main procbssorand the copr

necessaryto executea coprocessorinstructionis basedon a group o
cessorinterfaceregisters(ClRs),which are definedfor the M68000Fan
Table 3) and are implementedon the coprocessor.The MC68030hi
uses standardread and write cyclesto accessthe registers.Thus, tht
cessorinterfacedoes not requirespecialbus hardware;the bus interl
plementedby a coprocessorfor its interfaceregisterset must only sat
MC68030address,data, and control signaltiming to guaranteeprop
municationwith the CPU.Sincethe MC68030implementsthe commu
protocolwith all coprocessorsin hardware(and microcode)and har
operationsautomaticaf ly, the programmeris only concernedwith the
tions and datatypes providedby the coprocessoras extensionsto the [V
instructionset and data types.

Table 3. CoprocessorInterface Registers

Reqister Function RruV
Response Requests
Actionfrom CPU R
Control CPUDirectedControl W
Save Initiate Save of Internal State R
Restore fnitiate Restore of Internal State nlw
Operation Word CurrentCoprocessor
Instruction W
Command Word CoprocessorSpecific Command W
C o n d i t i o nW o r d Condition to be Evaluated w
Ooerand 32-BitOperand nnru
Reqister Select SoecifiesCPUReqisteror Mask R
Instruction
Address Po nter to Coprocessor Instruction nnrV
Operand Address Po nter to CoorocessorOoerand R^ru

Sincethe ClRsare accessedvia normal read and write cycles,copro

can be used as peripheraldevicesby other M68000Familymembers
not support the coprocessorinterface.The communicationprotocol
easilyemulatedby appropriatelyaddressingthe ClRsand by passing
quired coprocessorcommandsand operands.In additionto the ClRs,
processorcontainsthoseregistersaddedto the MC68030programmer'

3-234 M68OOO
FAMILYREFERENCE
MANUAL MOTOROLA
 for specificcoprocessor For exarnple,
operations. t,heMotorolafloatit
coprocessors d
containthe ClRsas well as eight80-bitfloating-point
istersandthree32-bitcontro|/statusregisters.

Up to eight coprocessorsare supported in a single MC68030syl

system-uniquecoprolessor identifierencodedin the coprocessor
, 'When accessinga coprocessor,the MC68030executesstandard b
CPU addressspace,'osencodedby the function codes,and placer
cessor identifieron the addressbus to be used by chip-selectlot
the particularcoprocessor.Sincestandardbus cyclesare used,the r
may be locatedaccordingto systemdesign requiremeRts, whether
on the microprocessorlocal bus, on anotherboard on the system
other placesupportedby the chip-selectand coprocessorprotocolr
ard bus cycles

COPROCESSOR
PROTOCOL ,

transfersare all initiatedby the main processordr

Interprocessor
cessorinstructionexecution.When processinga coprocessorins
main processortransfersinstructioninformationand data to tht
coprocessorand receivesdata, requests,and status information1
processor.Thesetransfersare all basedon standardreadand writr

The typical coprocessorprotocolfor the main processoris as foll

A. The main processorinitiatesthe communicationby writing c,
formationto a locationin the coprocessorinterface.
B. The main processorreadsthe coprocessorresponseto that in
1. The responsemay indicatethat the coprocessoris busy, a
processorshouldrequerythe coprocessor,allowingthe main process{
and coprocessorto synchronizetheir concurrentoperations.
2. The responsemay indicatesome exceptioncondition;th
cessoracknowledgesthe exceptionand beginsexceptionprocessing
3. The responsemay indicatethat the coprocessorneedsth
cessorto performsome servicesuch as transferringdatato or from tl
coprocessor.'The may also requestthat the main procsssr
coproces-sor
requerythe coprocessorafter the serviceis complete.
4. The responsemay indicatethat the main processoris no
furtherprocessingof the instruction.The communicationis terminate
and the main processoris freeto beginexecutionof the next instructio
At this point in the coprocessorprotocol,as the main processorconti
ues to executethe instructionstream,the main processormay opera
concurrentlywith the coprocessor.

MOTOROLA FAMILYREFERENGE
M68OT}0. MANUAT 3-235
 When the main processorfencountersthe next coprocessorinsl
main processorqueriesthe coprocessoruntil the coprocessoris rt
while, the main processorcan serviceinterruptsand perform a co
to executeother tasks.

Each coprocessorinstruction type has specific requirements ba

simplified protocol. The coprocessorinterface may use as man
words as requiredto implement a coprocessorinstruction.

PRIMITIVE/RESPONSE

Thecoprocessor responseregistercommunicates servicerequests

processor.The contentof the coprocessor responseregisteris
to the mainprocessor,
instruction whichis readduringcoproc€sr
nicationby the main processor.
The rnainprocessorexecutesth
therebyprovidingtheservicesrequiredbythecoprocessor. Table4
the coprocessorprimitivesacceptedby the MC68030.

Table 4. CoprocessorPrimitives
Primitive Function
Processor
Synchronization Busywith CurrentInstruction
Proceedwith Next Instructionlf No Trace
ServiceInterruptsand Requerylf TraceEnabled
Proceedwith Execution,ConditionTrue/False
InstructionManipulation TransferOperationWord
TransferWords from InstructionStream
Exception
Handling TakePrivilegeViolationlf S Bit Not Set
TakePre-lnstruction
Exception
TakeMid-lnstructionException
TakePost-lnstruction
Exception
GeneralOperandTransfer Evaluate and Pass (ea)
Evaluate (ea) and Transfer Data
Write to Previously Evaluated (ea)
Take Address and Transfer Data
Transfer to/from Top of Stack
Register"Transfer TransferCPURegilter
TransferCPUControlRegister
TransferMultipleCPURegisters
TransferMultipleCoprocessor
Registers
TransferCPUSR and/orScanPC

3-236 M68U}OFAI'IITYREFERSNGE
MANUAL MOTOROLA
 SIGNALDESGRIPTION
the functionalsignalgroups,and Table5 descri
Figure8 illustrates
signalsandtheirfunction.

IPLO
Fts'lcTtoN
CODES rF[r )
ADDRESS rFP \ rmennupr
zus imD colrTRol
DATA nv-vec )r
BUs
BR
/ srz0
BG
TRANSFER
/ srzl \ trt ARBTTRATT'N
gze\ mreR comnol
\ /

oc-s FESET
E6 flr \ ausExcEPnoN
ffiHn cofirTRoL
/
m
ASYNCHRONOT,IS AS STERM sYhtcHRoNous
zuscoNrRoL DS BUSCONTrcL
DBEN REFITI
oSKo STAruS
cDrs \ ,u*ro*
suPPoRT
MMUDIS /

CLK
(10)

Figure 8. FunctionalSignal Groups

MOTOROLA tt,ffig}O0FAMITYREFERENCE]
MAil\IUAL 3-237
 r " ,r Table 5. Signal lndex -
SignalName Mnemonic Function
j

FunctionCodes FCo-FC2 3-bitfunctioncode usedto identifythe addressspace

of eachbus cycle.
AddressBus A0-A31 32-bitaddressbus.
DataBus D0-D31 32-bitdatabus usedto transJer8, 16, 24,or 32 bits of
data per bus cyclb.
Size stz0/slz1 Indicatesthe numberof bytesremainingto be trans-
ferredfor this cycle.Thesesignals,togetherwith A0
and At, definethe activesectionsof the databus.
OperandCycleStart ocs ldenticaloperationto that of ECSexceptthat OCSis
assertedonly duringthe first bus cycleof an operand
transfer.
ExternalCycleStart BeS that a bus cycleis beginning.
an indication
Provides
ReadAtVrite R/W Definesthe bus transferas a processorreador write.
Cycle
Read:Modify-Write FMc Providesan indicatorthatthe currentbuscycleis part
operation.
of an indivisi'bleread-modify-write
AddressStrobe re Indicatesthat a valid addressis on the bus.
Data Strobe DS Indicatesthat valid data is to be placedon the data
bus by -an'externaldeviceor has beenplacedon the
data bus by the Mc68030.
Data Buffer Enable DBM Provides an enable signal for external data buffers.
DataTransferand Size DSACKO/ Busresponsesignalsthat indicatethe requested data
Acknowledge ffiT transferoperationhas been completed.In addition,
thesetwo lines indicatethe sizeof the externalbus
port on'a cycle-by-cyclebasisand are usedfor asyn-
chronoustransfers.
SynchronousTermination .,STffi Bus responseqigrnalthat indicatesa port size of 32
bits and that data may be latchedon the next falling
clockedge.
C a c h eI n h i b i t I n m Preventsdata from being loaded into the MC68030
instructionand datacaches.
C a c h eI n h i b i O
t ut CIOUT Reflectsthe Cl bit in ATC entriesor TTx register;in-
dicatesthat externalcachesshouldignoretheseac-
cesses.
CacheBurstRequest GFM Indicatesa burst requestfor the instructionor data
cache.
Cache Burst Acknowledge FAEK Indicatesthat the accesseddevice can operate in burst
mode.
Interrupt Priority Level IPLO-IPL2 Providesan encodedinterruptlevelto the processor.
InterruptPending IPEND I n d i c a t e st h a t a n i n t e r r u p t i s p e n d i n g .
Autovector AVEC Requestsan autovector during an interrupt acknowl-
edge cycle.
BusRequest BR Indicatesthat an external device requires bus master-
s hi p .
B u sG r a n t BG Indicates that an external device may assume bus
mastership.

3-238 MASIUAL
FAMILY,REFERENCE
M68OOO' MOTOROLA
 Table 5. Signal Index (Continuedl
SignalName Mnemonic Function
Bus GrantAcknowledge BGACK Indicatesthat an externaldevicehas assumedbus
mastership.
Reset FFtr System reset.
Halt HALT I n d i c a t e st h a t t h e p r o c e s s o r s h o u l d s u s p e n d b u s a c -
tivity.
BusError BERR I n d i c a t e st h a t a n e r r o n e o u s b u s o p e r a t i o n i s b e i n g a t -
tempted.
CacheDisable CDIS D y n a m i c a l l yd i s a b l e st h e o n - c h i p c a c h e t o a s s i s t e m -
ulator support.
MMU Disable MMUDIS D y n a m i c a l l yd i s a b l e st h e t r a n s l a t i o nm e c h a n i s mo f t h e
MMU.
PipeRefill REFILL I n d i c a t e sw h e n t h e M C 6 8 0 3 0i s b e g i n n i n g t o f i l l p i p e -
line.
Microsequencer
Status mrus Indicatesthe state of the microsequencer.
Clock CLK Clock input to the processor.
PowerSupply Vcc Powersupply.
Ground GND Ground connection.

MOTOROLA M68OOO
FAMILYREFERENCE
MANUAL 3-239
 ELECTRICAL FICATIONS
SPECI

- MC68O3O
MAXIMUMRATINGS
This device contains protectivecir-
Rating Symbol Value Unit
cuitry against damage due to high
SupplyVoltage* vcc - 0.3 to + 7.0 V static voltages or electrical fields;
however, it is advised that normal
Input Voltage vin - 0.5 to + 7.0 V precautionsbe takento avoid appli-
OperatingTemperatureRange oc cation of any voltages higher than
MinimumAmbientTemperature T4 0 maximum-ratedvoltagesto this high-
Maximum AmbientTemperature T4 impedancecircuit.Reliabilityof op-
PGA| = 33 MHz*, PPGA 70 erationis enhancedif unusedinputs
MaximumJunctionTemperature Tg are tied to an appropriatelogic volt-
PGA40 and 50 MHz* TBD age level (e.9.,eitherGND or Vg6).
COFP TBD
StorageTemperatureRange Tstq - 55 to 150 oc

*Ratedclock speedof device(not operatingfreguency)

THERMAL
CHARACTERISTICS
Gharacteristic Symbol Value Rating
- Junctionto Ambient
ThermalResistance "CAIV
oJA
PGA Package 30*
PPGAPackage TBD
COFPPackage TBD

- Junctionto Case
ThermalResistance otc
PGAPackage 15*
PPGAPackage TBD
COFPPackage TBD
*Estimated

POWERCONSIDERATIONS
The averagechip-junctiontemperature,T3, in oCcan be obtained
TJ-T4+(Pp.OJA) (1)
where:
T4 _ Ambient Temperature,oC
otR - PackageThermal Resistance,
J u nction-to-Ambient,"CAff
Pp : Plrut+PflO
Prrut - ICCx VCC,Watts- ChipInternalPower
Pyo = PowerDissipation
on InputandOutputPins
- UserDetermined
Formostapplications
PllOcPlNTand can be neglected.

3-240 M68(x'OFAMILYREFERENCE
MANUAL MOTOROIA
 The followingis an approximaterelationshipbetweenPp and T.1(if PyOis
neglected):
P D - K + ( T l+ 2 7 3 ' C l (21

(1)and (21tor K gives:

Solvingequations
K - Pp ' (Tn+273'C)+ ote . PD2 (3)
where K is a constantpertainingto the particularpart. K can be detr
from equation(3) by measuringPp (at equilibrium)for a known T4. Ur
value of K, the values of Pg and T; can be obtained by solving equal
and (21iterativefyfor any value of T4.

The total thermal resistanceof apackage(0.1A)can be separatedi

components,0.1gand OCA,representingthe barrierto heat flow from t
iconductorjunction to the package(case)surface (0lC) and from the
the outsideambient (eCR).Theseterms are relatedby the equation:
0.lR-eJC+OCA (4)

0.lC is device related and cannot be influencedby the user. How

user dependentand can be minimized by such thermal manag
niquesas heat sinks,ambientair cooling,and thermal convection,
thermaf managementon the part of the user can significantlyre(
that OtR approximatelyequals0;9. Substitutionof 0-;Cfor 0;4 in
will result in a lower semiconductorjunctiontemperature.

Valuesfor thermal resistancepresentedin this document,unlesr

were derivedusingthe proceduredescribedin MotorolaReliabilityI
','Thermal
ResistanceMeasurementMethod for MC68XXMicrocor
vices,"and are providedfor designpurposesonly. Thermalmeasu
cornplexand dependenton procedureand setup.User-derived val
mal resistancemay differ.

AC ELECTRICAL DEFINITIONS
SPECIFICATIONS
The AC specificationspresentedconsistof output delays,input sel
times,and signalskewtimes.All signalsare specifiedrelativeto an
edge of the Mc68030clock input and, possibly,relativeto one or
signals.

The measurementof the AC specificationsis definedby the wavefor

9. To test the parametersguaranteedby Motorola, inputs must I
the voltage levelsspecifiedin Figure9. Outputsof the MC68030t
with minimum and/or maximum limits,as appropriate,and are r
shown.Inputsto the MC68030are specifiedwith minimum and,as

MOTOROLA M6&XIOFAMILY REFERENCE

MANUAT 3-241
 maximumsetupand hold times,and are measuredas shown.
measurements
for signal-to-signal
specifications
arealsoshown.

Notethat the testinglevelsusedto verifyconformance

of the MC
AC specificationsdoesnot affectthe guaranteed
DCoperationof t
specifiedin the DCelectrical
characteristics.

DC ELECTRICALSPECIFICATIONSNss: 8.0vdc+-Soloi
GND =oVdc;
rempe
ranges)
Charasteristh Symbol Min Max Unit
fnput High Voltage vrs 2.0 vcc v
Input Low Voltage V11 GND 0.8 V
- 0.5

Input LeakageCurrent Em, m,EmK,cLK,

m-iFiZ,Nm, lin -2.5 2.5 trA
GND=Vin=VCC eDis,@
HALT,RESET -20 20
Hi-Z (Off-StatelLeakageCurrent
(u 2.4 V/0.5V
Ao-A31'
As'Dm'ofdt-#:'rii3:5ir?
I tsr -20 20 ttA

Output High Voltage Ao-A3r,F, BG,Do-Dgl.1leeg_F,ecs,Rffi,iFEm, von 2.4 V

loH = 4oo PA ocs,RMc,slzo-slzl,Fco-Fc2,
eER'm,
em,=r, FEFm
srA=rre,
Ot rtputLowVoltage Vot- V
loL= 3.2mA A0-A31,Fco-Fc2,
srzo-srzl,BG,D0-D3r 0.5
loL= 5.3mA CE-HEO,
AS,D6,RiW,m, DEm,iFmE 0.5
loL= 2'omA SfA'filS,FEm, ei6rUi,@ 0.5
IOL=10.7mA RESET 0.5
Power Dissipation(T4 = 0'C) Ps 2.6 W
Capacitance(see Note) cin 20 pF
Vio = 0 V, TA= 25oC,f = 1 MHz
Load Capacitance m,dG C1 50 pF
emr, snA=Rls,
HEFm 70
All Other 130
NOTE: Capacitanceis periodicallysampledratherthan 100"/o
tested.

3-242 M68(x'OFAMILYREFERENCE
MANUAL MOTOROLA
 2.OV

VALID
2.0v 2'ov vALrD
ourPuTs(l)cLK OI'TPUTn otJTPUT[ + 1
0.8v 0.8v

2.0v VALID
ouIPuTS{z)CLK n+l
OUTPIJT
0.8v

TO ->
DRIVE
2.4V 2.0v 2.0v
TNPUTS(3)CLK VALID
INPUT
DRIVE
TO -> o.sv o.sv
0,5v

*?3'15,
TNPUTS{4)CLK
* ?3'X5u

ALLSTGMLS(5)

NOTES:
1. This output timing is applicable to all pararneters specified relative to the rising edge of the clock.
2. This output timing is applicable to all paranreters specified relative trothe fallirg edge of the clock.
3. This input timing is applicable to all parameters specified relative to tre rising edge of the clock.
4. fhis inpt timing is appficable to all parameters specified relative to tre falling edge of the clock.
5. This tirntng is applicaHe to all paranreters specified relative to the assertior/negation of another signal.
LEGEND:
A. Maximum output delay specification.
B. Minimum output hold time.
C. Minimum input searp time specification.
D. Minimum input hold time specification.
E. Signal valid b signal valid specification (maximum or minimum).
F. signal valid to slgnal invalid specification (maximum or minimum).

Figure 9. Drive Levels and Test Points for AC Specifications

MOTOROLA FAMILY.REFERENCC
M68OOO' IYIAIW'AI 3-243
 - CLOCKINPUT (see
SPECIFICATIONS
AC ELECTRIGAL FigurE
20 MHz 25 MHz 33.33MHz 40 MHz 50 MHz
Unit
Num. Characteristic Min Max Min Max Min Max
Min Max Min Max

12.5 20 12.5 25 20 3if:33 25 40 25 50 MHz

Frequencyof Operation
50 80 40 80 30 50 25 40 20 40 ns
1 CycleTime Clock
19 61 14 36 11 . 5 29 9.5 30.5 ns
2,3 ClockPulseWidth Measuied 23 57
f r o m 1 . 5V t o 1 . 5V
5 4 3 2 2 ns
4s and FallTimes
Clock,Rise

a high
NoTE: Timingmeasurenrenlsare referencedto and from a low voltageof 0.8 V and
voltageat 2.OV, unlesso$rerwisenoted. The voltiagoswing trrough stis raqge
linear
should start ouBide and pass throughthe rangesuch that the rise or lall will be
between0.8 V and ?.0 V.

Figure10.GlockInput TimingDiagram

3-2M tYffi .FA{Tf Ii'IANUAL

ItY REFERENCB. MOTOROtTA
AC ELECTRICAL rrrrrir:READAND
SPECIFICATIONS WRITEGY(
(VCC=:?,0
Vdc t5%; GND=0 V9t, Temperature
in definedranges)

20 MHz 25 MHz 33.33MHz lO lUlHzr 50 MHz

Num. CharactOristic Unit
Min Max Min Max Min Max Min Max Min Max
6 Clock Hlgh '!o Fiinbtion Code, 0 25 0 20 0 14 0 14 0 14 ns
Size,R[MC,IPEND,
m, Addressvalid
6A ClockHigh to EG, 0G Asserted 0 15 0 15 0 12 0 r0 0 10 ns
6B FunctionCode,Size,n'Nie, 4 3 3 3 3 ns
.iFEim,ebTf, Address
Validto Negating
Edgeof EG
7 Clock"Highto Function.Code,Size, 0 50 0 40 0 30 0 25 0 2A ns
RMC,CIOUT,Address,
DataHigh lmpedance
8 Clock Hjg!-.11o
FunctionCode, 0 0 0 0 0 ns
Size,RMC,IPEND,
emf, AddressInvalid
I ClockLow to IF, DS Asserted, 3 20 3 18 2 10 2 10 , 2 10 ns
eEFmvafid
gAl AS to DE AssertionSkew {Read) - 10 10 - 10 10 -8 I -6 6 6 6 ns
gg'tc AS Assertedto DS Asserted 32 27 22 16 14 ns
{Write}
10 EG Width Asserted 15 10 8 5 4 ns
r0A 6ffi width Asserted 15 10 8 5 4 ns
t o B T ECS,OCSWidth Negated 10 5 5 5 4 ns
11 FunctionCode,Size,Filie, emf, 10 7 5 5 3 ns
' AddressValidto AssertingEdgeol
AS Asserted{and ffi Asserted,
Read) :
12 ClockLow'toIF; m, mHm 0 20 0 18 0 10 0 10 0 10 ns
Negated

124 ClockLow to ECS/OCSNegated 0 20 0 18 0 15 0 12 o 11 ns

13 AS, DS Negatedto Function 10 7 5 3 3 ns
Code,Size,RMC,CIOUT,
;AddressInvalid
14 IF (anODE ReaO)WiOttrAsserted 85 70 45 30 25 ns
(Asynchronous
Cycle)
14A11 DS Width Asserted(Write) 38 30 23 18 13 ns
148 FS (ano D3, Read)wid*r Asserted 35 30 23 18 13 ns
(SynchronousCycle)
15 AS, DS Width Negated 38 30 23 18 13 ns
t sAe F rvegaiedto AS Asserted 30 25 18 16 14 ns
16 ClockHigtrto AS, DS, RAff, 50 40 30 25 20 ns
DBEN,CBREQHighlrnpedance
17 AE, DS"wegatedto nAil hvalid 10 7 5 3 3 ns
18 ClockHigh to R/WHigh 0 25 0 20 0 15 0 14 0 14 ns
20 ClockHigh to R/WLow 0 25 0 2A 0 15 0 14 0 14 ns
21 RAIVHigh to AS Asserted 10 7 5 5 3 ns

MOTOROLA M6fr}OOFAMITYNEfERENCEMANUAL 3-2:45

 ffiAL'$PECIFICATIONS (conti
AC ELEGT,,' nued)
20 MHz 25 MHz Unit
Num. Characteristic Max Min Max Min Max Min Max
Min Max Min

(Write) 60 47 35 24 23 ns
22 nArutow to FE Asserted
20 14 14 14 ns
23 ClockHighto Data-OutValid 25
5 3 3 3 ns
24 Data-OutValidto Negating 8
Edgeof hS
7 5 3 3 ns
zsl1 AS, m Negatedto Data-Out 10
lnvalid
7 5 3 3 ns
to Dm
2 5 4 9 , 1 1 Ds tttegated Negated 10

H
(Write)
7 5 3 3 ns
2611 Data-OutValidto AssertingEdge 10
of DS Asserted(Write)
2 1 1 1 ns
27 Data-ln Valid to Clock Low 4
(S e tu P l
5 3 3 3 ns
274 Assertedto
Late,BERR/HALT 10
ClockLow (SetuPl
0 40 0 30 0 20 0 15 ns
zg12 F, 6-sn{ggr,"qto DsACKx, 0 50
BERR,HALT,AVEC
Negated(Asynchronous
Hold)
8 70 6 50 6 40 6 35 ns
zBA12 Clock Low to Dffi, B-ER-R, 12 85
mLT,A\reeNesated
(synchronous
Hold)
0 0 0 0 ns
2912: AF, Ds Negatedto Data-ln 0
Invalid(AsynchronousHold)
40 30 25 20 ns
29A12 K, OS Negatedto Data-ln 50
High lmpedance
I 6 6 6 ns
3ol2 Cl o ck L o w to Data- ln Invalid 12
(syn ch ro n ous Hold)
75 60 45 30 25 ns
3 0A 1 2 Clock Low to Data-ln High
lmpedance (Read followed
by Write)
28 20 14 13 ns
312 DSAR; Assertedto Data-ln 43
Valid(AsynchronousDataSetuP)
7 5 3 3 ns
3t A3 mRxAssertedto6ffi 10
Valid(Skew)
1.5 1.5 1.5 1.5 1 . 5 Clks
32 ffi Input TransitionTime
20 0 15 0 14 0 14 ns
33 ClockLow to BG Asserted 0 25 0
0 20 0 15 0 14 0 14 ns
34 Clock Low to BG Negated 0 25
1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 Clks
35 BF Assertedto BG Asserted 1.5 3.5
lffie Not Asserted)
1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 Clks
37 mffi Assertedto ffi Negated 1.5 3.5
1.5 0 1.5 0 1.5 0 1.5 0 1 . 5 Clks
gzAo EmR Assertedto BR Negated 0
60 45 30 30 ns
39 BG Width Negated 75
60 45 30 30 ns
39A EGwiO*rAsserted 75
20 0 18 0 16 0 14 ns
40 CtockHigh to DEf trtAsserted 0 25 0
(Read)

MANUAL
FAMILYREFERENCE
M68OOO MOTOROLA
3.246
AC ELECTRICAL
SPECIFICATIONS
{continued)
20 MHz 25 MHz 33.33MHz 40 MHz 50 MHzr
Num. Charasteristic Unit
Min Max Min Max Min Max Min Max Min Mox
41 ClockLow to mm Negated 0 25 0 20 0 18 0 16 0 14 ns
(Read)
42 ClockLow to DBENAsserted 0 25 0 20 0 18 0 16 0 14 ns
(Write)
43 ClockHigh to Dgffi Negated 0 25 0 20 0 18 0 16 0 14 ns
(Write)
M RIW tow to DggtrtAsserted 10 7 5 5 5 ns

I
{Write}
4s5 DEm width Asserted
Asynchronous
Read 50 40 30 22 20 ns
Asynchronous
Write 100 80 60 45 N
csAe Dm'Width Asserted
Synchronous
Read 1 0 5 5 5 5 ns
Synchronous
Write 50 40 30 22 20
46 nlW wioth Asserted 125 100 75 50 40 ns
(AsynchronousWriteor Read)
46A nffi WiCthAsserted(Synchronous 75 60 45 30 25 ns
Write or Read)
474 AsynchronousInput SetupTime 4 2 2 2 2 ns
to ClockLow
478 AsynchronousInput Hold Time 12 8 6 6 6 ns
from ClockLow
4ga DffiKx Assertedto 6EFF, 20 25 18 14 13 ns
Fm Asserted
53 Data-OutHold from ClockHigh 3 3 2 2 2 ns
55 RIW Rssertedto Data Bus 25 20 15 11 11 ns
lmpedanceChange
56 FFtr PulseWidth 512 512 512 512 512 Clks
(Reset
Instruction)
57 BERRNegatedto HALT 0 0 0 0 0 ns
Negated(Rerun)
s8lo BGACKNegatedto Bus Driven 1 1 1 1 1 Clks
sglo BG Negatedto Bus Driven 1 1 1 1 1 Clks
6 0 1 3 SynchronousInput Validto 4 2 2 2 2 ns
ClockHigh (SetupTime)
6113 ClockHigh to Synchronous 12 8 6 6 6 ns
InputInvalid(HoldTime)
62 ClockLow to STATUS, 0 25 0 20 0 15 0 15 0 15 ns
HEm Asserted
63 ClockLow to STATUS, 0 25 0 20 0 15 0 15 0 15 ns
HEFitt Negated

MOTOROLA M68{'OOFAMILY REFERENGE

MANUAL 3-247
AC ELECTRICALSPEC|FICATIONS(concruded)
NOTES:
Temperature
must be in rangedescribedin the MaximumRatings.
1. This numbercan be reducedto 5 ns if strobeshaveequalloads.
2. lf the asynchronoussetup time (#47Aj requirementsare satisfied,tne DffiK low to data setr
DSACKxlow to BERRlow setuptime (#4Bl can be ignored.The data must only satisfythe data-
time (#271forthe followingclockcycle,and BERRmustonly satisfythe lateBERRlow to clocklow
for the followingclockcycle.
3. This parameterspecifiesthe maximumallowableskew betweenDSieROto DSRC-K|assertedor D
asserted;specification#47A must be met by Dffiffi or DffiKI.
4. This specificationappliesto the first tDffiK or DffiKTt DffiRx signal asserted.In the absence
is an asynchronous input usingthe asynchronous inputsetuptime l#47All.
5. DBENmay stay assertedon consecutivewrite cycles.
6. The minimumvaluesmust be met to guaranteeproperoperation.lf this maximumvalue is exct
reasserted.
7. This specificationindicatesthe minimum high time for ECSand 0G in the eventof an int€rnol,
immediatelyby anothercachehit, a cachemiss,or an operandcycle.
8. This specificationguaranteesoperationwith the MC68881/MC68882, which specifiesa minimum tir
to AS asserted(specification #13A in the MC688811MC68882 lJser'sManuatl.Without this spec
interpretationof specifications #9A and #15 would indicatethat the MCOS030 does not meetthe n
requirements.
9. This specificationaflows a systemdestgnglto guaranteedata hold times on the output side of dati
outputenablesignalsgenerated with DBEN.Thetiming on DBENprecludesits usefor synchronous
no wait states.
10. Thesespecifications allow systemdesignersto guaranteethat an alternatebus masterhas stoppr
when the MC68030regainscontrolof the bus after an arbitrationsequence.
t t. DS will not be assertedfor synchronouswrite cycleswith no wait states.
12. Thesehold times are specifiedwith respectto strobes(asynchronous) and with respectto the clc
The designeris free to use eithertime.
13. Synchronousinputs must meet specifications #60 and #61 with stablelogic levelstor atl rising r
while AS is asserted.Thesevaluesare specifiedrelativeto the high levelof the risingclockedge.Th
publishedwere specifiedrelativeto the low levelof the risingclockedge.
14. This specificationallows systemdesignersto qualifythe CS signalof an MC688811MC68882 with
for a gatedelay)and still meetthe CSto DS setuptime requirement(specification 88 of the MC688t
Manual).

3-248 M68OOO
FAMILY REFERENCE
MANUAL MOTOROI-A
 FCz-FCo,
A31-A0,
slzl-slzo

ffi

tr

RIil

0m

osncKo

DSMRi

031-00

HIm
AU_
ASYNCHRONOTJS
INPUTS

0iiN

Figure 11. AsynchronousReadCycleTiming Diagram

MOTOROLA MANUAL
FAMILYREFERENCE
M68OOO 3-249
 ctJ(

431-AO,
FCGFCz
stzl-sm

nm
+

ECS

tr

Rnil

m
Mdm

NMRi

081-00

ffi

FmT

MT

Figure12.Asynchronous
Write GycfeTimingDiagram

3-250 M68OOO
FAMILYREFERENCE
MANUAL MOTOROLA
 FC2-FC0
A31-A0,
sE1-SlZ0

nTe

ec-cs

FS

AS

DS

R/W

DEEF

cffiT

CgREO

DSACKO/DSACKl

srEnu

mreR

m1-D0

Figure13, SynchronousReadCycleTiming Diagram

MOTOROLA FAMILYREF€RENCE
M68OOO MANUAL 3-251
 ctJ(

ml-Aq Fc2-FCo
stzl-stzo

RMC
.'.,

ffi

is

DS

Rnil

DBEN

ml-00

oWoffiRi

STERM

6m

ffi

Figure 14. SynchronousWrite Cycle Timing Diagram

3-252 M68{'OO'FAMILY
REFERENCE
MANUAL MOTOROLA
 cu(

431-40

001-00

FC2-F@

stzl-stzo

m
m

AS

os

Rn[

DSACKO

DSACKl

BR

BG

BGACK

NOTE: Timingmeasurementsare referencedto and from a low voltageof 0.8 V and a high voltage
of 2.0 V, unlessothenrisenoted. The voltageswing frrougrhthis rangeshouldstartoutside
and pass trrough the rangesuchSrat tre rise or fall will be linearbetween0.8 V and 2.0 V.

Figure 15. Bus Arbitration Timing Diagram

MOTOROLA NfrANt.}AL
M6EX} FAMILV REFERENCE 3-253
 ctJ(

iPExD

ME

cors

srnm

REFtfL

Figure 16. Other Signal Timings

3-254 "FAMILYREFERENCE
ril68OOO MANUAL MOTOROLA
 PINASSIGNMENTS
128.LEADPIN GRIDARRAY(RCAND RPSUFFIX}

N o o o o o o o o o o o o o
031 D28 026 025 Dn D21 D19 018 Dl6 015 013 011 D8
M o o o o o o o o o o o o o
DDmeG oeg DzTD24Dn 020 017 014 D12 Dg D6 D3
L o o a_o o o o o o o o o o

I
ilnn gzo nfr m0 GNDvs6 GNoGNDGND010 D7 tX D2
K o o o o o o o o o
CBREODS SlZl V6s NC V6s D5 Dl D0
J o Q _ o o o o
CBACKAS GND GNDSTAruSREFILL
H o o o o o o
BERRHALTVgC v6s cm im
G o _Q_o o o - a
RMDSACI(1GND GNDIru PTl
F o o o o o o o
DmereVssGNDNc NCV6gRESET
E o o o o o o
CI.J(AVECGND GND ]'tC lPEltD
D o o 0 , 6 0 o o o o
FCz FCOOCS Vsc NC Vsc A6 A3 tC
c o o,o o o o o o o o o o o
rq cEIFffiKlt GNDv6c GNDA18 GNDAll A9 As A4
B --O.-,O O O O O O O O OO O O
mffi i m $1 A29 A2t A2s A22 A20 A16 014 D12 D8 A7
A o io o o o o o o o o o o o
En I no $0 A2oA2Gtcl An A21A19 A17A15 A13A10
1 2 3 4 5 6 7 8 9 1011 12 13

MOTOROLA MANUAL
FAMILYREFERENCE
M68OOO 3-255
132.LEAD MOUNT(FESUFFIX}
SURFACE
CERAMIC

.
22G
. ( f
H F a l a x l E F F P p pffi16|glElars
$ 8 F l H2 2 i 2 , - t u , 2 9 e b
9('olri<lo(,(,E.z.

17 | 132 117
NC' 18 o r16 Nc.
BGAC 031
BR DS
AO D29
A1 028
A31 D27
430 026
AA D25
428 D24
427 or3
426 DN
M5 021
424 020
M3 Dr9
Faz D18
421 017
420 TOPVIEW 016
419 GND
A18 GNO
Ai7 Ivoo
Voo lvoo
Voo lots
GND lou
GND lots
416 lorz
A15 lorr
414 loro
413 lDe
412 los
A11 loz
A10 lD6
NC' Ittc'
NC' 50 84 I Nc'
51 83

F
? t s s S l g l EE
g gE H E E s 2
( ' >
8 I

'NC - Do not connect to this

Pin.

3-256 MANUAL
FAMITYREFERENCE
M68OOO MOTOROLA