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The Design and Construction of a DDS based Waveform Generator

Darrell Harmon

Abstract A direct digital synthesis (DDS) based signal generator was designed and constructed to cover the frequency range of DC to 20 MHz. The generator is capable of producing Sine and Square waves up to 20 MHz, and can produce arbitrary waveforms whose frequency is limited by a 23 MHz low pass lter. The arbitrary waveform generator is capable of generating Triangle waves at frequencies up to 7 MHz. This signal generator has very high frequency accuracy due to the use of direct digital synthesis. The signal generator is easy to modify due to the FPGA based architecture. Also, many different types of modulation are possible. Index Terms DDS, CORDIC, FPGA, DSP, Signal Generator

II. S PECIFICATIONS The signal generator will be able to generate sine, square and triangle waves from 1 Hz to 20 MHz. The output will have a 50 ohm impedance. The peak output voltage into a 50 ohm load will be variable from 50 mV to 5 V. The signal generator is to have the ability to be controlled by a computer. DAC aliases should be at least 60 dB below the carrier. Harmonics should be kept 40dB below the carrier for frequencies greater that 1 MHz and 60 dB below the carrier for frequencies less than 1 MHz. III. S YSTEM OVERVIEW The signal generator consists of 5 major parts: the

I. I NTRODUCTION

computer used for control, the microcontroller, the

signal generator is useful for testing many FPGA, the DAC and the analog signal processing types of circuits. Most low cost signal gensection. A computer running control software sends

erators drift signicantly in frequency, and cannot commands via a RS232 serial port to the microbe controlled by a computer. Recently, high speed DACs and FPGAs capable of generating high frecontroller in the signal generator. The microcontroller passes these commands to the FPGA. The

quency signals in real time have become available microcontroller is also responsible for initializing [1]. This report discuses the design and construction the FPGA and loading the conguration bitstream. of an FPGA based signal generator. The FPGA is responsible for the digital signal

processing. The FPGA outputs data to a high speed

80 MHz sampling rate chosen and the 32 phase

80106 f tw . 232

parallel DAC, and the output of this DAC is sent to accumulator chosen, f = the analog signal processing board. The analog sig-

Two methods of converting the phase value to

nal processing board provides ltering, switchable a sample value are used. The rst is by using the attenuation, amplication and sine to square wave conversion. CORDIC (COordinate Rotation Digital Computer) algorithm. CORDIC allows high speed vector rotation in FPGAs and ASICs. CORDIC is very efcient IV. D IRECT D IGITAL S YNTHESIS The signal generator uses Direct Digital Synthesis (DDS) techniques to generate the desired waveforms. As a compromise between an attainable sampling rate and the complexity of the required reconstruction lter, a sampling rate of 80 MHz was chosen. The phase accumulator is the basis of the DDS system. Every clock cycle, the phase accumulator is incremented resulting in linearly increasing phase both in terms of gates and power. Vector rotation can be used both to generate sinusoids and perform modulation [2]. A 14 bit CORDIC will be used. This will provide for 14 bit amplitude and phase resolution. With CORDIC, setting the input to a constant while linearly increasing phase produces a sine wave. Applying a signal to the input modulates the signal. Alternately, a look up table can be used to convert

and this phase value is converted to an amplitude phase values to amplitude values. The most signifvalue which is output to the DAC. The rate of the increase of phase determines the frequency. In the icant 10 bits of the phase accumulator are used to address a ROM to provide output samples. In place

FPGA, the phase is represented by a 32 bit unsigned of a ROM, a dual port SRAM can be used allowing integer. In the FPGA implementation, a phase value the waveform to be modied at any time. The of 360 degrees is represented by 232 . This causes the phase accumulator overow to occur at the same time as the phase reaches 360 degrees. The phase accumulator overow can be ignored due the overows occurring simultaneously. The frequency can be determined by formula f =
fs f tw where 2n

second port is connected to a microcontroller which is capable of generating and loading waveforms. A 16384x14 SRAM was used. This SRAM was made up of 14 16384x1 Xilinx blockram blocks. The Xilinx Spartan 3 XC3S400 FPGA contains 16 blockram blocks. The use of a look up table has the

ftw

is the value added to the phase accumulator every advantage of being capable of generating arbitrary cycle, fs is the sampling rate and where n is the number of bits in the phase accumulator. For the waveforms. When sine wave or square wave is selected,

the CORDIC is used. For the generation of other

modulating signal to the phase. A full scale modu-

waveforms such as triangle, the lookup table is lating signal will shift the phase from +180 degrees loaded with samples of the wave to be generated. V. M ODULATION Several modulation types can be achieved by implementing a modulator in the FPGA. AM, FM to -180 degrees. VI. DAC, F ILTER The Burr Brown DAC904E was used in the signal generator. This part is a 14 bit current steering

and PM were included. The modulation source is parallel DAC capable of operating at up to a 160 a second CORDIC and phase accumulator. This MHz sampling rate. The clock frequency of 80 MHz provides a complex sinusoid which can be varied was chosen to allow for a realizable reconstruction in amplitude. Single sideband modulation can be lter to be used. The DAC has a 20 mA differential

achieved by simply connecting complex modulating current output, and only one half of the differential signal to the modulator CORDIC. Double sideband output was used. This output was terminated to can be achieved by connecting the real part of the ground with 50 ohms and connected to a BNC

modulating signal to the real input of the modulator connector on the DAC board. The other output CORDIC and setting the imaginary input of the was grounded. This conguration results in a signal

modulator CORDIC to 0. An adjustable offset to which swings from 0V to 0.5 V when connected to the real input of the modulator CORDIC is provided a 50 ohm load. and allows for adding a carrier. This allows both DSB-SC and DSB-LC modulation. The percentage An reconstruction lter is required to remove the aliases generated by the DAC. It was desired that

of modulation is fully adjustable from 0% to 200% all aliases be at least 60 dB below the fundamental (overmodulation) for the DSB-LC case. If amplitude output power. It was determined that the worst case modulation is not desired, the input to the mod- alias would result at an output frequency of 20 MHz, ulating CORDIC is set to a constant resulting in producing a 60 MHz alias at -10.16 dBc. This meant sinusoidal output. Frequency modulation is achieved a lter would be required which would pass 20 MHz by adding the modulating signal to the frequency relatively unattenuated, but attenuate by at least

tuning word. The modulating signal is divided by 50 dB at 60 MHz. A 5th order active Chebyshev 256 so that the maximum frequency deviation is lter was considered, but the phase distortion of 156.25 kHz. The frequency deviation can be scaled the arbitrary waveforms could not be tolerated.

by adjusting the modulating CORDIC amplitude. The reconstruction lter was implemented as a 7th Phase modulation is implemented by adding the order Butterworth lter. Due to the high cost and

complexity of an active lter at these frequencies and the small size of the inductors required, a passive LC lter was used. Surface mount inductors and capacitors were used. The values of the components were calculated from a table found in appendix H of [3]. The 560 nH inductors were 0805 size wirewounds, and the 150 nH inductors were 0603 size wirewounds. The capacitors were all NP0 dielectric 0603 size multilayer ceramic capacitors. Exact capacitor and inductor values were unavailable. The closest available capacitors and inductors to the required values were used resulting in a cutoff frequency of 23 MHz. The attenuation of 50 dB at 60 MHz is maintained using these values. See Table I or Figure 1 for the lter schematic and values. The lter has a 50 ohm input and output impedance. The input impedance is matched to the output impedance of the DAC board and the impedance of the interThe output of the lter was connected to an OPA695 current feedback amplier in an inverting
Fig. 1. 20 MHz 7th Order Butterworth LC Lowpass Filter TABLE I 20 MH Z 7 TH O RDER LC L OWPASS F ILTER C OMPONENT VALUES
C1 180pF C2 270pF C3 180pF L1 150nH L2 560nH L3 560nH L4 150nH

Component Calculated Value L1, L4 177 nH L2, L3 717 nH C1, C3 198 pF C2 242 pF

Value Used 150 nH 560 nH 180 pF 270 pF

connecting cable. Figures 2 and 3 were obtained conguration with a gain of 8.43 with an input using a HP4195A network analyzer, and show that impedance of 50 ohms. A DC offset was also the lter meets the specication. The attenuation provided at this point so that the 0 to 0.5 V signal at 60 MHz is 57.3 dB. The attenuation is greater from the DAC swings from -2V to +2V at the output

than 60 dB for all frequencies above 63 MHz up to of the amplier. The OPA695 provides a bandwidth the 500 MHz maximum frequency of the network of 450 MHz at a gain of 8 which is far greater than analyzer. The lter has an 0.6 dB loss at DC due to the required bandwidth of 20 MHz. the inductor resistance and a 1.2 dB loss at 20 MHz due to the skin effect in the wirewound inductors. The DC loss will be compensated for by amplier gain. The AC loss could be corrected in software by increasing the gain as frequency increases. It was decided that the best way to produce sine waves would be to pass the sine wave through a comparator. Several alternatives were considered including switching between two voltage sources, VII. S INE TO S QUARE WAVE C ONVERSION

DC offset of the resultant square wave. VIII. M ULTIPLEXER Both sine/arbitrary and square waves are produced by the preceding circuitry. A multiplexor is needed to select which signal should be sent to the output amplier. Also, attenuation is needed to provide for lower output levels. The Analog Devices AD8184 4 input video multiplexor was selected for
Fig. 2. Reconstruction lter response - sweep from 0 to 500 MHz. 10 dB/div. The marker is placed at 60 MHz where the attenuation is 57.3 dB.

this purpose. This part has a bandwidth of 700 MHz and has a built in buffer amplier. The input impedance is very high. A pair of 20 dB attenuators were constructed from 180 and 20 resistors. Both attenuated and unattenuated square wave and sine wave/arbitrary waveform inputs were connected to the multiplexor. Any of the four inputs can be selected via software. IX. P OWER A MPLIFIER The power amplier must be able to swing from +10 V to -10 V into a 100 ohm load. This is

Fig. 3. Reconstruction lter response - sweep from 0 to 30 MHz. 1 dB/div. The diagonal line is the phase shift.

necessitated by the need to swing from +5 V to -5 V into a 50 ohm load while providing a 50 ohm

directly using a comparator and limiting ampliers. output impedance. A 50 ohm series resistor is used The Texas Instruments OPA699 limiting amp was chosen. It provides extremely high speed with a gain bandwidth product of 1 GHz. This amplier on the output of the amplier to set the output impedance. This resistor is outside the feedback loop. The amplier needs a slew rate of at least

provides upper and lower limit inputs, and clips 4000 V/s to be able to achieve a 5 ns rise and fall the output signal to these limits. The limit inputs time. were driven using a pair of slow serial DACs. The DACs allow for adjustment of both amplitude and Originally, the Texas Instruments THS3061 current feedback amplier was selected as the power

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amplier. This amplier is capable of being powered by a 15 V supply and providing an output current of 145 mA. The high power dissipation is handled by a heat sink tab on the bottom of the package. The device has a bandwidth of 260 MHz at the required non inverting gain of 5. The slew rate of the THS3061 is 7000 V/s. The opamp is unprotected, so external protection will be required in order to not exceed any absolute maximum ratings in the event of an output short. This opamp appeared to be exactly what was needed on paper and in SPICE, but latched up in operation. It appeared that the latchups

3 4

U4 THS3061

-15V

Fig. 4. The current limiting circuit for the negative supply used with the THS3061

were caused by too high slew rate. The peak voltage amplier was used as the power amplier. This across the opamp inputs would increase to 150 amplier uses a 5 V power supply, and the output millivolts when the slew rate of the output reached can swing from +4 V to -4 V. The slew rate is approximately 7000 V/s. Any increase in the input 4300 V/s. The amplier has a bandwidth of 1.4 slew rate from this point would cause a latchup GHz at a non inverting gain of 2. The amplier was and the amplier would draw approximately 150 used in a non inverting conguration with a gain of mA from the power supply. The addition of an 2.25. While the signal generator was unable to meet RC lowpass lter prior to the power amp resulted the output voltage specication using the OPA695, in either too much rounding of the square wave all other specications were preserved with this edges or was ineffective at solving the problem substitution. The OPA695 is able to safely drive a depending on the value of the capacitor. Current 50 ohm load, so in the event of an output short, it limiters were added to the THS3061 supplies to will be protected by the 50 ohm series termination. prevent it from being destroyed upon latchup. The were implemented as shown in Figure 4. There were no other ampliers that could be found to meet the supply voltage, output current and slew rate specications simultaneously. The Texas Instruments OPA695 current feedback The measured output frequency error was extremely small. An Instek GFC-8131H frequency counter was used for these measurements. The counter has an uncertainty of 5 ppm which is greater than the measured errors. It is possible X. R ESULTS

the the errors are higher than as measured. More

in gure 6. Using a 1.8V peak setting results in

accurate equipment was unavailable. The results an acceptable distortion level. The minimum output are presented in Table II. The large error at 1 Hz amplitude of 50mV into 50 ohms was veried as

is due to rounding of the frequency tuning word. seen in Figure 7. The signal generator is capable of The resolution is approximately 0.018 Hz. All other producing smaller signals, but the noise level will

frequencies measured resulted in an error of less increase as amplitude decreases as less bits are used than 4 parts per million. The clock oscillator used is of the DAC. only specied to be within 30ppm of 80 MHz. The maximum frequency error is the oscillator frequency error plus the rounding error of up to 0.018 Hz.
TABLE II F REQUENCY ACCURACY Setting 1 Hz 1 kHz 100 kHz 1 MHz 10 MHz 20 MHz 12.345678 MHz 3.333333 MHz 1.22 MHz Measured 0.9872 Hz 1.000002 kHz 100.0003 kHz 1.000003 MHz 10.000038 MHz 20.000076 MHz 12.345722 MHz 3.333344 MHz 1.220004 MHz Error (Hz) 0.0128 0.002 0.3 3 38 76 44 11 4 Error (ppm) 12800 2.0 3.0 3.0 3.8 3.8 3.6 3.3 3.3 Fig. 5. 20 MHz Sine wave

The output of the signal generator was measured in the time domain using a Tektronix 7903 oscilloscope with 7A19 and 7B92A plugins. This oscilloscope has a bandwidth of 500 MHz and a risetime of 800 picoseconds. The output was measured in the frequency domain using an HP 4195A spectrum and network analyzer. This instrument provides resolution bandwidths down to 3Hz and very good frequency accuracy. The signal generator was determined to clip at The spectrum of the sinusoidal output is shown in gures 8, 9 and 10. Figure 8 shows the generation
Fig. 6. 1 MHz Sine wave : Amplitude = 2 V peak

1.9 volts into a 50 ohm load. This is illustrated of a 12.345678 MHz sine wave at 1 Volt peak (10

Fig. 7.

1 MHz Sine wave : 50 mV peak

Fig. 8. 12.345678 MHz Sine wave : 1 V peak, sweep from DC to 50MHz

dBm). There is a second harmonic approximately 60 dB below the carrier. This is due to distortion in the ampliers. There is also a signal at 6.375 MHz which is also approximately 60dB below the carrier. The origin of this signal is unknown. It may be due to rounding error. Figure 9 displays the spectrum of a 19 MHz sine wave. The 135 kHz modulation that is seen was determined to be due to the 1.2V FPGA core voltage switching power supply which operates at 135 kHz. The modulation is 53 dB below the carrier. This problem could be can be seen in Figures 11 and 12. The risetime is
Fig. 9. 19 MHz 1 V peak Sine wave spectrum - 1 MHz span

solved at the cost of power consumption by using slightly longer at lower frequencies increasing to a linear regulator. Figure 10 shows that the carrier 100 ns at 1 kHz. This could be improved by using

itself is very clean. The noise oor is much lower the arbitrary mode and generating an approximate due to the small resolution bandwidth of 10 Hz used. square wave as input to the comparator. Using this resolution bandwidth with a larger span would take too long to be practical. Figure 13 is the spectrum of a 20 MHz square wave generated by the signal generator. The 13th

The square wave function worked as expected. harmonic is clearly visible. There is a signicant The rise and fall times of a 20 MHz 1 volt peak amount of power in even harmonics. This is due

square wave were measured at 3 nanoseconds. This to the square wave being non-symmetric which is

Fig. 10.

19 MHz 1 V peak Sine wave spectrum - 1 kHz span

Fig. 12.

20 MHz Square wave risetime detail

Fig. 11.

20 MHz Square wave - 1 volt peak

Fig. 13.

20 MHz Square wave spectrum

caused by an offset error at the comparator input.

Figure 15 illustrates a 5 MHz triangle wave. The

The 2nd harmonic is approximately 35 dB below 5th and higher harmonics were greatly attenuated by the fundamental. Triangle waves were generated by using the arbitrary waveform generator mode. The lookup table was loaded with a triangle wave calculated by Fourier series. The number of harmonics was selected so that none would alias. Figure 14 was the reconstruction lowpass lter. The lookup table was loaded with harmonics through the 7th. A sawtooth wave was also used to demonstrate the arbitrary waveform generator. Figure 16 demonstrates the generation of a 1 MHz sawtooth wave. Figure 17 demonstrates a 1 MHz square wave band

generated using 39 harmonics in the look up table. limited to 19 MHz. The lookup table values were The harmonics above 23 MHz were attenuated by calculated by Fourier series. the lter. Figure 18 show the signal generator outputting

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Fig. 14.

1 MHz Triangle wave

Fig. 16.

1 MHz Sawtooth wave

Fig. 15.

5 MHz Triangle wave

Fig. 17.

1 MHz square wave limited to 19th harmonic

double sideband large carrier with 100% modula- sidebands. Figure 22 is the spectrum of the signal tion. The carrier frequency is 1 MHz and the mod- generator output when performing double sideband ulating frequency is 10 kHz. Figure 19 is the same suppressed carrier modulation. This modulation is

except for the modulation was changed to 50%. the same as AM with the carrier removed. The Figure 20 illustrates double sideband suppressed same distortion exists. Figure 23 is the spectrum carrier. Figure 21 is the spectrum of the signal generator output when performing double sideband large carof a wideband FM signal generated with the signal generator. The frequency deviation is set to 75 kHz which is the same as used in broadcast FM radio.

rier modulation (AM). The spectrum is as expected No measurable distortion was noted. The AM and with the addition of second harmonic distortion of the modulating signal 55 dB below the power of the FM modulation was also tested successfully using a radio receiver.

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Fig. 18.

1 MHz DSB-LC with 10 kHz 100% modulation

Fig. 20.

1 MHz DSB-SC with 10 kHz modulation

Fig. 19.

1 MHz DSB-LC with 10 kHz 50% modulation

Fig. 21.

1 MHz DSB-LC with 5 kHz modulation

XI. C ONCLUSION

interface could be changed from RS232 serial to

The use of Direct Digital Synthesis provides USB. many advantages over a traditional signal generator. These include excellent accuracy of output frequency and extreme exibility for modulation. 1. The use of the FPGA allows the user to make any changes desired. There are still many things 2. that could be improved about the signal generator. 3. The user interface could be made simpler than the 4. XII. A PPENDICES Schematics (Analog board, DAC board, DSPcard) FPGA logic Verilog listing AD8184 Multiplexor datasheet OPA695 Opamp datasheet DAC904E DAC datasheet OPA699 Opamp datasheet

current command line program. A physical control 5. panel could be constructed if desired. The computer 6.

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Fig. 22.

1 MHz DSB-SC with 5 kHz modulation

Fig. 23. 1 MHz wideband FM with 15 kHz modulation and 75 kHz deviation

R EFERENCES
[1] G.-J. van Rooyen and J. G. Lourens, A quadrature baseband approach to direct digital fm synthesis, IEEE Transactions on Broadcasting, vol. 46, no. 3, Sep. 2000. [2] Ray Andraka, A survey of cordic algorithms for fpga based computers, ACM/SIGDA sixth international symposium on Field programmable gate arrays, Monterey, CA, Feb. 1998. [3] Paul Horrowith and Wineld Hill, The Art of Electronics,

Cambridge University Press, second edition, 1989.