Chapter 10

FIELD EFFECT TRANSISTORS: MOSFET

The following overview gures describe important issues related to the most important electronic device.

MOORE'S LAW

Gordon Moore, co-founder of Intel: 1st law: Complexity (number of active devices) of a chip doubles every 18 months. 2nd law: Cost of a fabrication facility grows on a semi-log scale with time. Complexity increases at ~59% per year! At current pace, semiconductor fabrication facilities will cost $250 billion by 2010!

108 107

NUMBER OF ACTIVE DEVICES/CHIPS

106 105 104 103 102 101 1960 1970 1980 YEAR 1990 2000 2010

Prof. Jasprit Singh

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AN OVERVIEW OF THE MOSFET STURCTURE

idth, Z Gate w

Polysilicon or metal Oxide n-type semiconductor

D n-source Gate n-drain p-substrate G S (a) STRUCTURE Gate, G n-type polysilicon Deposited insulator Schematic symbol B L

Metal source contact S

Metal source drain D

SiO2 Field oxide

n+ Source Channel region

dox

n+ Drain

SiO2 p+

L Silicon dioxide Channel length L p-type body, B

(b) CROSS-SECTIONAL VIEW Modern MOSFETs are enormously complex devices with great care taken to reduce parasitic elements.

Prof. Jasprit Singh

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A SIMPLE SCHEMATIC OF PROCESSES IN A MOSFET FABRICATION

Coat the entire wafer with Si3N4. Si3N4 is impervious to dopants.

Si3N4

n+ source and drain are produced by ion implantation.

p-Si

n+ p-Si

p+

(a)

(d)

First mask: Define transistor area and remove Si3N4. Implant p+ regions to serve as device isolation. Grow thick field oxide.

SiO2 is deposited on the entire structure. A mask is used to open windows for contacts. Al is evaporated. B S G D SiO2

p+

(b) Etch Si3N4 and grow thin gate oxide. On the gate oxide, grow polysilicon and define the gate via a mask. polysilicon gate SiO2 p+ p-Si B S

(e) Top view of the device G

(c)

(f)

Prof. Jasprit Singh

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BAND PROFILES IN A METAL, OXIDE, SEMICONDUCTOR, AND A MOS

Metal Oxide (insulator) p-type semiconductor (a) Evac Band profiles in a metal, SiO2, and p-Si. em dox Metal EF Oxide (b) Semi-conductor Evac Ec (oxide) es es Ec Evac

EF Ev

eVfb Band profile in a MOS structure em es Ec es EF Metal Oxide Semiconductor (c) EF Ev eVfb = em es Evac

Prof. Jasprit Singh

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BAND PROFILES AND CARRIER DENSITY IN ACCUMULATION,

DEPLETION AND INVERSION

Electric field F VGS < 0

Accumulation

p p0

EF eVGS
+ ++

Ec EFi EF O S Electric field F Ev (a) n0 n z W

Carrier density

Depletion
Ec VGS > 0 EFi EF Ev O S (b) W Na p0

p n

Carrier density

eVGS EF M

Electric field F

Inversion
n (interface) > po VGS >> 0 Ec EFi EF Ev Na p n n0 z (c) W p0

Carrier density

eVGS EF M O S

Prof. Jasprit Singh

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AN MOS STRUCTURE UNDER INVERSION

V >> 0

Ec d Ei EF eVGS Ev

O EF M Qm

Semiconductor z Q (charge per unit area)

Charge density
W z

Qd: charge from background dopants

Qn: free carrier charge Fox

Electric field

Fs W z

V(x)

Electrostatic potential

Vox VGS = Vfb + V = Vfb + Vox + Vs z

Vs W

Wmax =

4s F 1/2 | | ; F = EF EFi eNa

VT = Vfb 2F + [2esNa | 2F + VSB |]1/2 C C ss ox ox Qss = interface areal charge density

Prof. Jasprit Singh

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CAPACITANCE-VOLTAGE RELATION IN

Oxide

Semiconductor C = Cox Cmos(fb) Accumulation C

Low frequency (~1Hz) C = Cox (i) High frequency (103 Hz) Cmos(min) Inversion Vfb 0 VGS Flat band Accumulation Depletion region VT (ii)

Cox

Cs

Weak inversion

Strong inversion

AREAL CHARGE DENSITY, |Qs| (C/cm2)

Once the MOS is in inversion, the sheet charge density increases rapidly with bias.

105

106

107

2F

108

109 0.2

1.0

1.0

0.2

0.3

0.4

SURFACE VOLTAGE, Vs (volt)

Prof. Jasprit Singh

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EFFECT OF BODY BIAS ON MOSFET PROPERTIES

VGS S n+ p-substrate G D + n n-MOSFET with VSB bias VDS

(a)

VSB nversion condition when VSB = 0

Ec EFi eVs = 2eF EF Ev

(b)

Wmax nversion condition when VSB > 0

W(VSB)

Ec EFi EF Ev

eVs = e(2F + VSB)

EFn

Electron quasiFermi level

(c) Shift in threshold voltage VT =

2esNa Cox

2F +VSB

2F

Prof. Jasprit Singh

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Ohmic region

A typical n-channel depletion-mode device

Prof. Jasprit Singh

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Drain current I

COMLIMENTARY MOSFET: LOW POWER FET

By combining an NMOS and a PMOS a CMOS is constructed. Since only one device (NMOS or PMOS) conducts for any gate bias the CMOS does not draw any current and is very useful for low power applications. PMOS Source + SiO2 Gate NMOS Gate p well Source

Output Drain Drain p+ SiO2 n+

p+ + + ++

n+ SiO2

Hole conduction

Electron conduction

(a)

n-type body +VDD PMOS

NMOS

(b)

SCHEMATIC SYMBOL

(a) A cross-section of a CMOS device. (b) Symbol representing the CMOS.

+V Vin Vout Vin t ID (a) t (b) t S p-channel D Vout D n-channel S

(a) A complimentary MOS structure shown to function as an inverter. The circuit draws current only during the input voltage switching. (b) A schematic of the CMOS structure.

Prof. Jasprit Singh

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LATCHUP PROBLEM

IN

CMOS TECHNOLOGY

The presence of npn, pnp bipolar pathways in a CMOS can lead to parasitic transistor action and unintentional current flows.

A + I D p+ S p+ n+ R2 n substrate pnp

B V S p+ R1 npn R4 R3 n+ D n+ p well

(a)

CURRENT, I

Slope =

1 R3||R4

(b)

VOLTAGE, V

VL

(a) A schematic of the parasitic effects that lead to CMOS latch-up problems. (b) Current versus voltage effect. The onset of latch-up is represented by a sharp rise in the parasitic current.

Prof. Jasprit Singh

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CAPACITANCES OF IMPORTANCE IN A MOSFET

Gate Source CGSO
n+ + n+

Oxide CGC

Channel Drain CGDO CBD1

(a)

n n n n+ n+ n n n+ n+ p p p n + n + p pCBC1 CGB CBS1 p p p p p p p p p p p Bulk (substrate) p p p

d2 LD Z Source L d1 (b) Gate Region Cutoff CGD CGS CBG CBD CBS (c) Cox Z LD Cox Z LD Cox Z L CBD1 CBS1 CBD1 + Ohmic Cox Z LD + 1/2 ZL Cox Cox Z LD + 1/2 Z LCox 0 CBC1
2 2

LD Drain

Saturation Cox Z LD Cox Z LD + 2/3 Z LCox 0 CBD1 CBS1 + 2/3 CBC1

CBS1 + CBC1

A CIRUIT MODEL FOR A MOSFET Total gate capacitance includes overlay effects (CGS) S G Gate-drain capacitance includes parasitic effects (CGD) D

Miller capacitance: CM + CGD(1+gmRL) Cutoff frequency: fT =

gm 2(CGS+CM)

Source-body capacitance

n+ RS CBS

' gmVGS

RD n+ CBD

p-substrate

Drain-body capacitance

Self-aligned gate technology to minimize CM or CGD.

Prof. Jasprit Singh

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SCALING ISSUES IN MOSFET TECHNOLOGY

PARAMETER Gate width, Z Gate length, L Oxide thickness, dox Drain bias, VDS Threshold bias, VT Oxide capacitance for the device Drain current, ID DC power consumption Device switching time Power-delay product

FULL SCALING CONSTANT-VOLTAGE SCALING 1/S 1/S

1/S

1/S ~1/S ~1/S2 ~1/S ~1/S3

1/S ~S ~S ~1/S2 ~1/S

Prof. Jasprit Singh

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SEMICONDUCTOR INDUSTRY ASSOCIATES ROADMAP

YEAR DRAM cell half-pitch (nm) Gate length for MPU (nm) Maximum substrate diameter (mm) Acceptable defect density at 60% yield for DRAM Defect density for MPU Power supply (V) Power dissipation with heat sink (W) Power dissipation without heat sink (for portable electronics) (W) Cost per function DRAM (cents/function) Cost per function MPU (cents/function)

1997 250

1999 180

2001 150

2003 130

2006 100

2009 70

2012 50

200

140

120

100

70

50

35

200

300

300

300

300

450

450

2080

1455

1310

1040

735

520

370

1940 1.8-2.5 70

1710 1.5-1.8 90

1510 1.2-1.5 110

1355 1.2-1.5 130

1120 0.9-1.2 160

940 0.6-0.9 170

775 0.5-0.6 175

1.2

1.4

1.7

2.0

2.4

2.8

3.2

120 3000

60 1735

30 1000

15 580

5.3 255

1.9 110

0.66 49

KEY ISSUES: Gate tunneling current Defect density Interconnect delays will dominate

Prof. Jasprit Singh

www.eecs.umich.edu/~singh