Design and Implementation of Reversible Watermarking for JPEG2000 Compression Standard on FPGA

By M.Shoba Rani Reg. No. 09C41D5511

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

JAYAMUKHI INSTITUTE OF TECHNOLOGY & SCIENCE NARSAMPET, WARANGAL 2010

ABSTRACT
With the result of advancement in todays technology, digital content can be easily copied, modified, or distributed. Digital watermarking provides the solution to this problem. Most of the digital watermarking methods are divided into two categories: Robust watermarking and fragile watermarking. As a special subset of fragile watermarking, reversible watermarking (lossless or invertible watermarking) enables us to recover the image which is same as the original image pixel by pixel after the content is authenticated. This type of lossless recovery is compulsory in sensitive imagery applications like medical and military purposes. An efficient watermarking algorithm has been implemented using Matlab which uses the concept of difference expansion of high pass transform coefficients with watermark bits. This work was to find a reversible watermarking algorithm for JPEG2000 standard for medical applications, a (5,3) wavelet transform is used which is considered as lossless transform in the JPEG2000 standard. In the algorithm, (5,3) Integer wavelet transformed high pass coefficients are difference expanded instead of Haar wavelet transformed coefficients in Mark Tians algorithm. Based on the Algorithm developed for Matlab modeling, a new architecture for Reversible watermarking was designed and the hardware modeling for that architecture was done using Verilog HDL. By difference expanding the high pass coefficients of the image and embedding the watermark in those high pass coefficient, maximum embedding capacity over 90000 bits is achieved for a 256x256 image. The Watermark embedding block is synthesized using Xilinx ISE and implemented on Spartan3 FPGA. The Reversible Watermarking Block operates at a maximum clock frequency of 62.073 MHz with a minimum period of 16.110ns. The Latency of the system is N+2 clock cycles for a total of N pixels macro block. The embedding capacity of 2bits at a time are used to embed in the high frequency coefficients, as number of bits to be embedded increases the Peak Signal to Noise Ratio decreases up to 31.3%.

REAL TIME IMPLEMENTATION OF BCH CODES ON SPARTAN-3 DSP PROTOTYPE KIT

By M.Shoba Rani Reg. No. 09C41D5511

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

JAYAMUKHI INSTITUTE OF TECHNOLOGY & SCIENCE NARSAMPET, WARANGAL 2010

REAL TIME IMPLEMENTATION OF BCH CODES ON SPARTAN-3 DSP PROTOTYPE KIT

In recent years there has been an increasing demand for efficient and reliable digital data transmission and storage systems. This demand has been accelerated by the emergence of largescale, high speed data networks for the exchange, processing, and storage of digital information in the commercial, governmental, and military spheres. A merging of communications and computer technology is required in the design of these systems. A major concern of the system designer is the control of errors so that the data can be reliably reproduced. On memoryless channels, the noise affects each transmitted symbol independently. Hence, transmission errors occur randomly in the received sequence, and memoryless channels are called random-error channels. Good examples of random error channels are the deep-space channel and many satellite channels. Most line of sight transmission facilities, as well, are primarily affected by random errors. Codes designed to correct random errors are called random-error correcting codes. On channels with memory, the noise is not independent from transmission to transmission. The channel is in the good state most of the time but on occasion shifts to the bad state owing to a change in the transmission characteristic of the channel. As a consequence, transmission errors occur in clusters or bursts because of the high transition probability in the bad state, and channels with memory are called burst-error channels. Codes designed to correct burst errors are called burst-error correcting codes. The simplest block codes are Hamming codes. They are capable of correcting only one random error and therefore are not practically useful, unless a simple error control circuit is required. More sophisticated error correcting codes are the Bose, Chaudhuri and Hocquenghem (BCH) codes that are a generalisation of the Hamming codes for multiple-error correction. In this report the subclass of binary, random error correcting BCH codes is considered. BCH codes operate over finite fields or Galois fields. This project is concerned with (15, 7) double error correcting BCH code and its implementation in real time using FPGA. The brief description of the project is as follows. In this project we are considering a sinusoidal signal of frequency 200Hz as the input signal and this is applied as the input to 12-bit ADC(AD-7891). The ADC will sample the sinusoidal signal and it will give 12 bit representation of the sample as the output. The output of ADC is given as the input to the BCH encoder circuit. The output of the encoder is passed through the channel where random errors are

introduced. The output of the channel is given as the input to the decoder circuit. The decoder will correct these random errors and will give back the original message bits as the input to the DAC. The DAC will convert the digital signal into an analog signal. The output of the DAC is observed in the oscilloscope. Here the sampling frequency of ADC can be varied through the switches and we have observed that the minimum sampling frequency to get back the original sinusoidal signal will be around 4KHz. The remainder of this report is organized as follows. In section 2, The Bose-ChaudhuriHocquenghem (BCH) codes have been described. In section 3, we will discuss Overview of SPARTAN-3 FPGA kit. Section 4 describes the design flow of Xilinx software. Section 5 provides results of the BCH codes.

FPGA IMPLEMENTATION OF UTMI WITH USB 2.0 SPECIFICATIONS

By M.Shoba Rani Reg. No. 09C41D5511

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

JAYAMUKHI INSTITUTE OF TECHNOLOGY & SCIENCE NARSAMPET, WARANGAL 2010

ABSTRACT
As operating frequencies go up it becomes more difficult to compile VHDL code without modification. This document defines an interface to which ASIC and peripheral vendors can develop. The figure1 shows the block diagram of USB controller, which is present in every USB device. There are three major functional blocks in a USB 2.0controller. the USB 2.0 Transceiver Macrocell Interface (UTMI), the Serial Interface Engine (SIE), and the device specific logic.

Figure1: Block diagram of USB controller. UTMI This block handles the low level USB protocol and signaling. This includes features such as; data serialization and deserialization, bit stuffing and clock recovery and synchronization. The primary focus of this block is to shift the clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic in the ASIC. The UTMI is designed to support HS/FS, FS Only and LS Only UTM implementations. The three options allow a single SIE implementation to be used with any speed USB transceiver. A vendor can choose the transceiver performance that best meets their needs. A HS/FS implementation of the transceiver can operate at either a 480 Mb/s or a 12 Mb/s rate. Two modes of operation are required to properly emulate High-speed device connection and suspend/resume features of USB 2.0, as well as Full-speed connections if implementing a DualMode device.

FS Only and LS Only UTM implementations do not require the speed selection signals since there is no alternate speed to switch to. Serial Interface Engine This block can be further sub-divided into 2 types of sub-blocks; the SIE Control Logic and the Endpoint logic. The SIE Control Logic contains the USB PID and address recognition logic, and other sequencing and state machine logic to handle USB packets and transactions. The Endpoint Logic contains the endpoint specific logic: endpoint number recognition, FIFOs and FIFO control, etc. Generally the SIE Control Logic is required for any USB implementation while the number and types of endpoints will vary as function of application and performance requirements. SIE logic module can be developed by peripheral vendors or purchased from IP vendors. The standardization of the UTMI allows compatible SIE VHDL to drop into an ASIC that provides the macro cell. Device Specific Logic: This is the glue that ties the USB interface to the specific application of the device.