EE3013

SEMICONDUCTOR DEVICES AND PROCESSING

(Pre requisite: EE 2003)
Dr Wang Hong Associate Professor Microelectronics Division School of EEE, NTU S2.1-B2-12 Tel: 6790 4358, email: ewanghong@ntu.edu.sg Consultation hours: Wed: 1:30 pm 3:30 pm Thu: 1:30 pm 3:30 pm
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Wang Hong, EEE

School of EEE, NTU

EE3013

Course Content
Fundamentals of Bipolar Devices MOS Devices Diffusion and thermal oxidation Ion implantation Deposition Techniques Lithography Etching (4 hours) (4 hours) (4 hours) (3 hours) (4 hours) (4 hours) (3 hours)

WH

TBK

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TEXTBOOK
1. Stephen A Campbell The Science and Engineering of Microelectronic Fabrication, Oxford University Press, 2001 (TK7871.85.C191 2001)

REFERENCE
1. Richard C Jaegar, Introduction to Microelectronic Fabrication: Vol 5 of Modular Series in Solid State Devices, Prentice Hall, 2002. (TK7874.J22 2002 ) 2. Michael Quirk and Julian Serda, Semiconductor Manufacturing Technology, Prentice Hall, 2003 (TK7836.Q93 )
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EE3013

What are Semiconductor Devices?

Semiconductor device - a component made from semiconductor material deals with electronic (or optoelectronic) process or manipulate electrons (maybe photons) to achieve certain electric functions,

The Fairchilds 1st commercial planar transistor (2N1613), marketed in April 1960 4
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0.13 m MOSFET
(Courtesy of Chartered Semiconductor Mfg Pte Ltd, Singapore)

65 nm MOS transistor with L-shaped spacer

(Courtesy of UMC Ltd, Singapore branch)

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Why Semiconductor Devices?

Semiconductor devices are everywhere

Electronic engine Electronic dashboard control LED illumination

Radio & CD-player

Data transmission

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Example of Semiconductor Devices

Semiconductor Devices, Diode & single Transistor

Small (<100 transistors/chip) to Medium (100-1000 transistors/chip) scale ICs

LSI: 1000-10000 Transistors VLSI : 10000-1 M transistors 6

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ULSI: > 1 M Transistors

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Semiconductor transistors
What is the commonest human artifact today? Not plastic bag! It is transistor! Not metal screw! Not cigarette butt!

Gordon Moore made an educated guess several years ago: 1018 (one quintillion) transistors are produced annually.

We make more transistors per year than the number of printed characters in all the newspapers, magazines, books, photocopies, and computer printouts,; And we sell these transistors for less than the cost of a character in the Sunday New York Times.
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Gordon Moore Intel Co-Founder and Chairman Emeritus

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Making Semiconductor Devices From macro to nano

Bridges Airplanes Cars Human beings Birds 8

Snails Rice Ants Watch gears

Sand Hair Dust Pollen Cells Bacteria

Viruses Nuclei Transistors Cell apparatus Proteins

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How to manufacture in the micro and nano world?

We must learn how to Build Em Small

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Conventional manufacturing
Assembly - Primary method of manufacturing for engineered systems 1. Materials are processed, formed into components 2. Components are assembled together to build more complex modules 3. Materials are standardized 4. Interfaces are standardized 5. Manufacturing methods are standardized 6. Design method is mature 7. Test methods are mature

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Electronic Device Manufacturing

Batch fabrication is primarily used method for manufacturing microelectronic devices and systems. 1. Materials are processed in batch 2. New materials are layered and patterned over other materials 3. Final devices are packaged and assembled on host system

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EE3013

Clean rooms for micro and nano fabrication

Semiconductor processing facilities in clean room

Clean room for mercury program, 1960s

Semiconductor clean room facility, today (IBM 300 mm fab)

Originally developed by NASA and the aerospace industry for satellite manufacturing. Cleanrooms now in use for all semiconductor and MEMS manufacturing.
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Semiconductor Processing
The current Si IC fabrication is using planar fabrication process Planar fabrication process: Simultaneous fabrication of many chips on a wafer, each comprising an integrated circuit (e.g. a microprocessor or memory chip) containing millions or billions of transistors
300mm Si wafer Method: Sequentially lay down and pattern thin films of semiconductors, metals and insulators.

In EE3013, starting from the basic semiconductor devices, we are going to learn the fabrication process for semicondctor devices and ICs
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Chapter 1 p-n Junction Diodes

Recap of what was done in EE2003: Semiconductor Si P-type semiconductor N-type semiconductor P-N junction Transistor IC Semiconductor processing
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--- Hole --- Electron

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p-n Junction Diodes

Importance of p-n Junction Diodes p-n junction serves an important role both in modern electronic applications (being used in rectification, switching and other operations), and in understanding other semiconductor devices because it is the key building block for most of devices, such as BJTs, etc.

Red LED

Photodetector

Intels 65nm MOSFET

IBMs SiGe Bipolar Transistor

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School of EEE, NTU

EE3013

Basic Fabrication Steps of p-n Junction

Planar technology is used extensively for integrated circuit (IC) fabrication. The major steps (Fig.1 and 2) to make a Si p-n junction include oxidation to form SiO2 on the Si surface lithography to create photoresist patterns etch to remove unwanted materials, e.g. SiO2, etc. diffusion or ion implantation to dope the Si and metallization to form metal contacts

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A p-n junction in Thermal equilibrium.

A p-n junction allows current to flow easily in only one direction. - Forward bias: p-side positive, voltage < 1V; - Reverse bias: p-side negative, current nearly 0 till junction breakdown.

Fig. 3. Current voltage characteristics of a typical Si p-n junction.

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Carrier Concentration and Fermi Level

Two regions of p- and n-type semiconductor materials that are uniformly doped and physically separated before the junction is formed. Relationship between hole or electron concentration and Fermi level

Separated p- and n- regions and their energy band diagrams

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Formation of p-n junction and band diagram

Consider the equilibrium pn junction (no bias).

EC

N
Ei EV

_ + _ +

N
p n

Majority carriers diffuse across the junction, leaving ionized dopants - establishing a field. The field causes drift currents and opposes diffusion, so that the net current is zero.
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Carrier Drift
minority

E
e e

majority electron diffusion e EC

p-region

qVbi

EF
majority hole diffusion

h h h

n-region
minority

EV

The built in field will sweep minority carriers across the junction. Electrons drift from p to n, shown below). Drift velocities are ve = e E , vh = h E Drift current densities are of the form

J e = qnve
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Note: In equilibrium, Fermi levels are aligned

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Carrier Diffusion
Carriers diffuse from high to low concentrations (so n to p for electrons).

F = D
For holes and electrons

dC dx
dp dn , J e ( diff ) = qD e dx dx

J h ( diff ) = qD h

The positive and negative signs indicate the direction of the current with respect to the carrier gradient - Recall: De = e(kBT/q) (Einstein relation), where me, electron mobility is a measurable parameter.
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Net Current under Equilibrium

Consider both drift and diffusion currents, dp J h = J h ( drift ) + J h ( diff ) = q h pE qDh ,
dx dn J e = J e ( drift ) + J e ( diff ) = q e nE + qDe dx

where m is the mobility of the carriers, (measured in cm2V-1 s-1), and n and p are carrier densities (cm-3), J is current per unit area. In equilibrium, no net charge accumulation J h = J e = 0 We know the number of electrons in p-type and n-type material. In equilibrium, it is possible to derive the expression to show that Fermi level in the p-n junction is constant at thermal equilibrium. (See notes page 4)
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Built-in potential Vbi

The constant Fermi level required at thermal equilibrium results in a unique space charge distribution at the junction. The total electrostatic potential difference between the p-side and n-side neutral regions at thermal equilibrium is called the built-in potential Vbi.

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Built-in potential Vbi (Contd)

For p, consider the neutral region of the p-side and apply charge neutrality, p = NA, Substituting in equation From band diagram,
Or

Similarly, Therefore,
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Space charge region P

_ _ + +

Transition region: the space charges of impurity ions are partially compensated by the mobile carriers. The transition region is thin can be neglected Rectangular Approximation of Space-charge region or depletion region: mobile carrier densities are zero.

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Depletion Region
Abrupt junction: Formed when there is an abrupt transition of doping between n- and p- regions; Linearly graded junction: Formed when the impurity distribution varies linearly across the junction.
Abrupt junction

Solvinging Poissons equation in the depletion region,

the electric field profile at the junction can be determined.

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Maximum Electric Field

Overall space charge neutrality requires: The total depletion layer width is given by

The maximum electric field m that exists at x = 0 is given by This can be derived using Poissons equation.

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EE3013

Depletion Layer Width

The built-in potential is given by Vbi = (1/2) mW The total depletion layer width as a function of the builtin potential, can be given by

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One-sided abrupt junction

When the impurity concentration on one side of an abrupt junction is much higher than that of the other side, the junction is called a one-sided abrupt junction. Like, n+-p or n-p+ junctions. In this case, xp << xn, and the W can be simplified to

The maximum electric field is

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Where NB is the lightly doped bulk concentration (= ND)

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p-n junction at bias

Forward bias: A positive voltage VF is applied to the p-side with respect to the n-side. The total electrostatic potential across the junction decreases by VF, that is, it is replaced by VbiVF. Thus, forward bias reduces the depletion layer width. Reverse bias: A positive voltage VR is applied to the n-side with respect to the p-side. The total electrostatic potential across the junction increases by VR, that is, it is replaced by Vbi + VR. The reverse bias increases the depletion layer width. The depletion layer width as a function of the applied voltage, V

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p-n junction under forward bias

Under forward bias, VF > 0, and decreases by Vbias. A increased dominate. Barrier height is W
p

the barrier height diffusion currents

q(Vbi VF )

+
minority e

_
VF
e Majority diffusion e EC FN

p-region
FP h Majority diffusion h

n-region
h minority EV

qV =F F F N P
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p-n Junction under reverse bias

Under reverse bias, and the barrier increases in height by VR. Diffusion current minimised, leaving very small (reverse) drift current. W
p n

I V

_
minority e

+
VR
q(Vbi+VR) EC FN EV School of EEE, NTU

p-region
FP h majority h h minority

majority e

n-region

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EE3013

Depletion capacitance
The depletion capacitance per unit area is defined as

Cj = dQ/dV,
where dQ is the incremental change in depletion layer charge per unit area for an incremental change in the applied voltage dV.

This equation for the depletion capacitance per unit area is the same as the standard expression for a parallel-plate capacitor where the spacing between the two plates represents the depletion layer width. This equation is valid for any arbitrary impurity distribution.
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Capacitance-Voltage characteristics
For one-sided abrupt junction,

Or

A plot of 1/Cj2 versus V produces a straight line for a onesided abrupt junction. The slope links to the impurity concentration NB and the intercept (at 1/Cj2 = 0) gives Vbi.
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