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LogicComponents&QMLogic Minimization
Out e Outline
Karnaugh mapwith>=5variable StudyofComponents d f
Multiplexor,Decoder LogicImplementationUsingMUX&Decoder Mux: 7 Segment Display Mux:7SegmentDisplay 4BitAdder
(a)
3
(b)
Decoder
Receptioncounter:Whenyoureacha AcademicInstitute Academic Institute
ReceptionistAsk:WhichDepttoGo? Receptionist Redirect you to some building ReceptionistRedirectyoutosomebuilding accordingtoyourAnswer.
Decoder : knows what to do with this: Decode Decoder:knowswhattodowiththis:Decode Ninput:2N output MemoryAddressing
Addresstoaparticularlocation
4
Decoders
Decoder:Popularcombinationallogicbuilding block,inadditiontologicgates block in addition to logic gates
Convertsinputbinarynumbertoonehighoutput
1 0 0 0 1 0 i0 i1
d0 d1 d2 d3
0 1 0 0 0 1 i0 i1
d0 d1 d2 d3
0 0 1 0 1 1 i0 i1
d0 d1 d2 d3
0 0 0 1
Internaldesign
ANDgateforeachoutputtodetectinputcombination
Decoderwithenablee
Outputsall0ife=0,Regularbehaviorife=1
ninputdecoder:2n outputs i d d 2
1 i0 i1 e 1
d0 d1 d2 d3 1
0 0 0 1
d0 d1 d d2 d3
d0 1 1 i0 i1 e 0 d1 d2 d3
0 0 0 0
i1
6
i0
4to16Decoderusingtwo3to8 Decoders d
D0toD7
D8toD15
BooleanFunctionImplementation usingDecoders d
Using a nto2n decoder and OR gates any Usingan to 2ndecoderandORgatesany functionsofnvariablescanbeimplemented. Example: Example:
S(x,y,z)= (1,2,4,7),C(x,y,z)=(3,5,6,7)
FunctionsSandCcanbeimplementedusinga 3to8decoderandtwo4inputORgates
Decoder:CoversAllMinterms Decoder: Covers All Minterms
X Y Z
ConfigurableFunctionusingDecoder &Memory
1 0 1 1 0 0 1 1
a b c
Decod er
8rowx1col memory
10
i0 (1*i0=i0) 1
d
21 i0 i1 d s0 0 i0 i1
21 d s0 0 0 i0 i1
21
i1
d s0 0 1 0s0
0
a
i0 (0+i0= i0)
4x1mux
s1 1 s0 0
CoversAll Minterms
Ex:Two4bitinputs,A(a3a2a1a0),andB(b3b2b1b0)
4bit2x1mux (justfour2x1muxes sharingaselectline)can selectbetweenAorB
MIN
HR2
MUX
MIN1 4 4
7 Segment Decoder D d
DEMUX
MIN2
15
ImplementinglogicFunctionusing MUX
4 1 1 0 1 0 i0 i1 i2 i3 s1 s0
A B
F(A,B)=m(0,2) F (A B) (0 2)
4x1mux
16